JPH0319243A - Manufacture of field-effect transistor - Google Patents
Manufacture of field-effect transistorInfo
- Publication number
- JPH0319243A JPH0319243A JP15342089A JP15342089A JPH0319243A JP H0319243 A JPH0319243 A JP H0319243A JP 15342089 A JP15342089 A JP 15342089A JP 15342089 A JP15342089 A JP 15342089A JP H0319243 A JPH0319243 A JP H0319243A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- etching
- semiconductor
- effect transistor
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract 9
- 238000000034 method Methods 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は，高周波帯で使用できる電界効果トランジスタ
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a field effect transistor that can be used in a high frequency band.
従来の技術
高周波帯で使用するＦＩＴの特性を良くする方法の一つ
は、ゲート長（Ｌｇ）の短縮である，従って近年短ゲー
ト長を実現する多くの方法が提案されている。BACKGROUND OF THE INVENTION One method for improving the characteristics of FITs used in high frequency bands is to shorten the gate length (Lg). Therefore, many methods for achieving short gate lengths have been proposed in recent years.
第３図は従来の電界効果トランジスタ製造方法の概略図
である。第３図にかいて６はレジスト、６はＧａＡｓ基
板、７はゲート電極である。FIG. 3 is a schematic diagram of a conventional field effect transistor manufacturing method. In FIG. 3, 6 is a resist, 6 is a GaAs substrate, and 7 is a gate electrode.
以上のように構成された電界効果トランジスタ製造方法
のゲート形成について、以下その動作を説明する。The operation of gate formation in the field effect transistor manufacturing method configured as above will be described below.
１ず、（ａ） ＧａＡｓ基板にレジストを塗布し次に（
ｂｌ電子ビーム露光法によりレジストにパターンニング
を行なった後現像し０．３μｍのゲートパターンを形成
する、そして（Ｃ）ゲート電極を実現する。1. (a) Apply resist to the GaAs substrate and then (
After patterning the resist using the bl electron beam exposure method, it is developed to form a gate pattern of 0.3 μm, and (C) a gate electrode is realized.
発明が解決しようとする課題
しかしながら上記のような構成では、製造装置も大がか
りで、しかもその工程に長時間を要するという欠点を有
していた。Problems to be Solved by the Invention However, the above configuration has the disadvantage that the manufacturing equipment is large-scale and the process requires a long time.
本発明は上記欠点に鑑み、容易に、短ゲート長のＦＩＣ
Ｔを実現できる電界効果トランジスタの製造方法を提供
するものである。In view of the above-mentioned drawbacks, the present invention facilitates short gate length FIC.
The present invention provides a method for manufacturing a field effect transistor that can realize T.
課題を解決するための手段
上記問題点を解決するために、本発明の電界効果トラン
ジスタでは、ゲートを形成する部分の上に単結晶層を形
成し、通常のフォトリングラフ法と異方性エッチングに
よう選択的に上記単結晶層の一部分を取り除き、ゲート
形成を行なうという構成となっている。Means for Solving the Problems In order to solve the above problems, in the field effect transistor of the present invention, a single crystal layer is formed on the part where the gate is to be formed, and a conventional photolithographic method and anisotropic etching are used. The structure is such that a portion of the single crystal layer is selectively removed to form a gate.
作用
この構成によって、単結晶のエッチングの異方性により
、フォトリングラフ法で形成したゲート長より短いゲー
ト形成ができることとなる。Effect: With this configuration, due to the anisotropy of single-crystal etching, it is possible to form a gate with a length shorter than that formed by the photolithographic method.
実施例
以下、本発明の実施例について第１図，第２図を参照し
ながら説明する。Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2.
第１図は、本発明の第１の実施例における電界効果トラ
ンジスタ製造工程の概略図かよび同要部を示す図である
。FIG. 1 is a schematic diagram of the manufacturing process of a field effect transistor in a first embodiment of the present invention, and a diagram showing the essential parts thereof.
第１図に釦いて、１はＧａＡｓ基板、２ぱ▲７ｉＧａＡ
ｓ層、３はフォトレジスト，４はゲート電極である。Click the button in Figure 1, 1 is GaAs substrate, 2 is ▲7iGaA.
s layer, 3 is a photoresist, and 4 is a gate electrode.
以上のように構成された電界効果トランジスタのゲート
形成工程について、以下その動作を説明する。１ず第１
図ａのように（ １ ００ ） ＧａＡｓ基板上にＡＪ
ＧａＡｓ層を形成する。本実施例では、膜厚の制御性の
良い，分子線エビタキシャル法で行った。次に同図ｂの
ようにフォトレジストを選択的に形成し、（１００〉面
のエッチング速度に比べて（１ １ １）面のエッチン
グ速度が遅いエッチング液を用いて同図Ｃのようにエッ
チングを行なう。このときの各部分の寸法は第２図のよ
うになる。（１１１）面と（１ｏｏＸＩｆｉのなす角は
、５４．７°であるのでゲート長Ｌｇｕレジスト長ＬＲ
と人βＧａＡｓ層の厚みｄを用いて
Ｌｇ：ＬＲ−２ｄｃｏｔ （６４．７°）で表わせる。The operation of the gate forming process of the field effect transistor configured as described above will be described below. 1st 1st
As shown in figure a, AJ is placed on a (100) GaAs substrate.
Form a GaAs layer. In this example, the molecular beam epitaxial method, which provides good controllability of film thickness, was used. Next, as shown in Figure B, a photoresist is selectively formed, and etching is performed as shown in Figure C using an etching solution that etches the (1 1 1) plane at a slower rate than the (100> plane). The dimensions of each part at this time are as shown in Figure 2.The angle formed by the (111) plane and (1ooXIfi is 54.7°, so the gate length Lgu resist length LR
It can be expressed as Lg:LR-2dcot (64.7°) using the thickness d of the βGaAs layer.
従って本実施例ではＬＲを７ォトレジストで容易に実現
可能な１μｍとしＬｇ＝０．２６μｍにしたいので、
ｄ＝ − （ＬｙＩ−ＬＧ）ｔａｎ（６４．７°）−４
−０．６３μｍ２
とした。Therefore, in this example, we want to set LR to 1 μm, which can be easily realized with 7 photoresists, and Lg = 0.26 μm, so d= − (LyI−LG) tan (64.7°) −4
-0.63 μm2.
次に同図ｄのようにゲート電極を形成丁るとこのゲート
長は０．２６μｍとなっている。Next, a gate electrode is formed as shown in d of the same figure, and the gate length is 0.26 μm.
なか、本実施例では、▲ＪＧａＡｓをゲート形成部分上
の単結晶層に用いたが、これは五ｌＧａＡｓに限定され
るものではなく単結晶となる材料ならば何でもよい。In this embodiment, ▲JGaAs was used for the single crystal layer on the gate forming portion, but this is not limited to 51GaAs, and any single crystal material may be used.
発明の効果
以上のように本発明は、ゲート形成部分の上に単結晶層
を形成しその異方性エッチングにより短ゲート長ゲート
形成が容易に行うことができ、その実用的効果は犬なる
ものがある。Effects of the Invention As described above, the present invention can easily form a gate with a short gate length by forming a single crystal layer on the gate formation part and anisotropically etching it, and its practical effects are outstanding. There is.
第１図は本発明の実施例にかける電界効果トヲンジスタ
製造方法の工程断面図、第２図は要部拡大図、第３図は
従来の電解効果トランジスタの工程断面図である。
１・・・・・・ＧａＡＳ基板、２・・・・・・▲ＪＧａ
Ａｓ層、３・・・・・・レジスト，４・・・・・・ゲー
ト電極。FIG. 1 is a process sectional view of a method for manufacturing a field effect transistor according to an embodiment of the present invention, FIG. 2 is an enlarged view of the main part, and FIG. 3 is a process sectional view of a conventional field effect transistor. 1...GaAS substrate, 2...▲JGa
As layer, 3...Resist, 4...Gate electrode.
Claims (1)
体を形成し、その一部を選択的に異方性エッチングして
、上記第２の半導体底部の開孔幅が上部開孔幅より小さ
くなるように除去し上記第１の半導体上にゲートを形成
することを特徴とする電界効果トランジスタの製造方法
。A second single crystal semiconductor different from the first is formed on the first semiconductor substrate, and a part of the single crystal semiconductor is selectively anisotropically etched so that the width of the opening at the bottom of the second semiconductor is the same as that at the top. A method of manufacturing a field effect transistor, comprising forming a gate on the first semiconductor by removing the first semiconductor so that the width of the opening is smaller than the width of the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15342089A JPH0319243A (en) | 1989-06-15 | 1989-06-15 | Manufacture of field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15342089A JPH0319243A (en) | 1989-06-15 | 1989-06-15 | Manufacture of field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319243A true JPH0319243A (en) | 1991-01-28 |
Family
ID=15562114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15342089A Pending JPH0319243A (en) | 1989-06-15 | 1989-06-15 | Manufacture of field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319243A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6057979A (en) * | 1983-09-09 | 1985-04-03 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62274675A (en) * | 1986-05-22 | 1987-11-28 | Mitsubishi Electric Corp | Manufacture of field-effect transistor |
| JPH01168069A (en) * | 1987-12-24 | 1989-07-03 | New Japan Radio Co Ltd | Manufacture of semiconductor device |
-
1989
- 1989-06-15 JP JP15342089A patent/JPH0319243A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6057979A (en) * | 1983-09-09 | 1985-04-03 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62274675A (en) * | 1986-05-22 | 1987-11-28 | Mitsubishi Electric Corp | Manufacture of field-effect transistor |
| JPH01168069A (en) * | 1987-12-24 | 1989-07-03 | New Japan Radio Co Ltd | Manufacture of semiconductor device |
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