JPS5947771A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5947771A JPS5947771A JP15746482A JP15746482A JPS5947771A JP S5947771 A JPS5947771 A JP S5947771A JP 15746482 A JP15746482 A JP 15746482A JP 15746482 A JP15746482 A JP 15746482A JP S5947771 A JPS5947771 A JP S5947771A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- ohmic
- electrode
- spacer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title description 2
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 238000004070 electrodeposition Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 5
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 102000016942 Elastin Human genes 0.000 description 1
- 108010014258 Elastin Proteins 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 229920002549 elastin Polymers 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は超高周波帯で動作するＧ ａ Ａｓ電電界効果
上トランジスタ以下Ｇ ａ Ａ ｓ Ｆ Ｅ Ｔ と称
す）の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a GaAs field effect transistor (hereinafter referred to as GaAsFET) that operates in an ultra-high frequency band.
現在、ＧＨｚ 以上の超高周波帯において商業的５ ベ
ースでＧａＡｓＦＥＴが生産され、さらに１０ Ｇｌ（
ｚの如く高い周波数の素子のｆｌｉｔ究がす＼められて
いる。これらの超高周波ＧａＡｓＦＥＴはゲート電極に
ショットキーバリアｒ利用し、逆方向電圧忙印加するこ
とで、オーム接触？なすソース・ケート間の電流ｒ制御
するという簡単な原理による。従ってまたゲート電極の
信頼度が直ちに１” Ｅ Ｔの信頼度に影響するから、
ゲート電極形成時に半導体基板にいささかも汚染があっ
てはならない。その意味で有機物汚染の源泉となる可能
性の強いホトレジスタの使用ケ避けたゲート形成法が必
要になる。また出力の大きいＦＥＴＩ得るには現在では
単一のＦＥＴ１並列動作させるが、入力および出力のイ
ンビーターンス特性が揃っていなければならない。この
入出力ｌｒケ性は主として、ゲート電（執とオーミック
電極（ソースおよびゲートｍ；極）との間隔によって支
配される。ｇにゲート・ソース間の抵抗値は重要である
。Currently, GaAsFETs are produced commercially on a commercial basis in the ultra-high frequency band above GHz, and even more so on a 10 Gl (
Flit research for high frequency elements such as Z is progressing. These ultra-high frequency GaAsFETs use a Schottky barrier at the gate electrode and apply a reverse voltage to create ohmic contact. This is based on the simple principle of controlling the current r between the source and gate. Therefore, since the reliability of the gate electrode immediately affects the reliability of 1" ET,
The semiconductor substrate must not be contaminated at all during the formation of the gate electrode. In this sense, there is a need for a gate formation method that avoids the use of photoresists, which are likely to be a source of organic contamination. Furthermore, in order to obtain a FETI with a large output, one single FET is currently operated in parallel, but input and output interference characteristics must be the same. This input/output lr characteristic is mainly controlled by the distance between the gate electrode and the ohmic electrode (source and gate m; pole).The resistance value between the gate and the source is important in g.
Ｊ、 ＯＧｌ（ｚ ｌｂ作のＧ ａ Ａ ｓ Ｆ ＥＴ
の寸法は１例としてゲート長０．５μｍ、ソース・ゲー
ト間０．５μｍ の如く極めて小であるから寸法のバラ
ツキの＋＋＋＋ＩＶ＋＋は特別に難しく、通常行なわれ
るマスク１合わせなどでは制御は困難であり、当然セル
フアジイメント方式の製法になる。J, OGl (G a As F ET by z lb
For example, the dimensions are extremely small, such as the gate length of 0.5 μm and the source-to-gate distance of 0.5 μm, so it is particularly difficult to control the variation in dimensions by one mask alignment, etc. Naturally, it will be manufactured using a self-adjustment method.
本発明の目的は上記の欠点？除去し、信頼性が高く、か
つ歩留りのよい超高周波Ｇ ａ Ａ ｓ Ｆ Ｅ Ｔ
ｋ製造する新規の製造方法？提供することにある。Is the purpose of the present invention the above drawbacks? ultra-high frequency G
K new manufacturing method? It is about providing.
以下図面？参照して本発明の詳細な説明する。Is the drawing below? The present invention will be described in detail with reference to the following.
図においては、ゲート電極と一つのオーミック電極の製
造工程ｒ示すが、他のオーミック電極も同時に行えばよ
いから省略しである。Ｇ ａ Ａ ｓ基板１上に５ｒＵ
ｚ膜２を成長させ、さらにその上に５ｉａＮ４膜３ケ成
長させる。（図ａ）。次にホトレジスト４’に所定の泣
面４”＋ ４ｂ、４ｃに塗布密着（図１））後、ドラ
イエツチングで５ｉ３Ｎ４−８ｉ（Ｊｚ膜ヤケ除去た後
、弗酸・弗化アンモニウム混そ、蛾でウエットエッチン
グオ行なうと、Ｓｉ３Ｎ４とＳｉ（〕２ とはウェット
エツチングに対して、エラチンクレートの差が太きいた
めエツチング後ホトレジスト加工くと、上層の５ｉ３Ｎ
４１１りが下層の５ｉ（Ｊ２１１１７、ｒ、 、ｖ）は
り出シｉｔ Ｓ ｉ ３Ｎ４−８１ｏ２１１Ｌ５Ｅｒｆ
ｒ定’７Ｊ（ｎ１＃４ａ、４ｂ、４ｃに生ずる（ Ｉｌ
ｌ ｃ ）。Ｃの特殊の形状膜が本発明におけるゲート
電極及びオーミック電極形成時のスペーサとしての役割
ｒなすものである。以下、ゲート電極形成・オーミック
電極形成４涸別に順次行なう。４ａ１４ｂ間にゲート電
極に、４ ｂ＋ ４ Ｃ間にオーミック電極形成ｒ行
なうのであるが、先ずゲート電極形成〒図ｄ〜図ｅにて
説明する。ゲート電極形成部分以外忙ホトレジスト１４
でおおい、燐酸系エツチング液によｐＧａＡｓ基板１ｒ
エツチングしてリセス構造ケ形成するとともに、ＧａＡ
ｓの活性層１′の厚みヶ調整しゲート電極として所定の
ピンチオフ電圧が得られるようにする（（９）ｄ）。ホ
トレジスト１４’？除去した後、ゲート金属としてＡ４
まｔはＡｄ／Ｔｉｋ蒸着する（図ｅ）。このゲート電極
の寸法は図Ｃのスペーサのうち上層のＳ ｉ ３Ｎ４膜
の形状・寸法によりで５まる。次にオーミック電極形成
企図ｆ〜図りにて説明する。オーミック〒に極形成部分
以外忙ホトレジスト２４でおおい、オーミック形成部分
に被着しているＡｌ″！、たはＡ ｅ ／ Ｔ ｉ ２
エツチングで除去後、オーミックメタル６としてＡｕＧ
ｅ／Ｎｉｖ？！着する（図ｆ入この際もスペーサのうぢ
Ｓｉ３Ｎ４膜の形状・寸法によりオーミック電極の寸法
がさだまる。ホトレジスト２４孕除去した（図ｇ）後、
既に形成されたゲートおよびオーミック電極のみｒおお
うようにホトレジスト３４の加工４行なう。スペーサの
８ｉ０ａ膜２の厚みが十分とってあれば８ｉａｌｑ４膜
５と電極との間には充分の間隔がとれるからホトレジス
ト３４はその間に入りこみ、各電極紫完全におおい保護
する。次にホトレジスト３４ｒマスクとして不必要なゲ
ートメタル５ｒエツチングにより除去した後。In the figure, the manufacturing process r of the gate electrode and one ohmic electrode is shown, but it is omitted because it is sufficient to perform the manufacturing process for other ohmic electrodes at the same time. 5rU on GaAs substrate 1
The Z film 2 is grown, and three 5iaN4 films are further grown on it. (Figure a). Next, after coating the photoresist 4' on the predetermined critical surfaces 4"+ 4b and 4c (Fig. 1)), dry etching 5i3N4-8i (after removing the Jz film discoloration, adding a mixture of hydrofluoric acid and ammonium fluoride, When wet etching is performed, Si3N4 and Si(]2 have a large difference in elastin rate compared to wet etching, so when photoresist is applied after etching, the upper layer 5i3N
411 beam is the lower layer 5i (J21117, r, , v) protruding sheet S i 3N4-81o211L5Erf
r constant '7J (occurs in n1 #4a, 4b, 4c (Il
lc). The specially shaped film C plays a role as a spacer when forming the gate electrode and ohmic electrode in the present invention. Hereinafter, the formation of the gate electrode and the formation of the ohmic electrode will be performed in sequence. A gate electrode is formed between 4a and 14b, and an ohmic electrode is formed between 4b+4c. First, the formation of the gate electrode will be explained with reference to FIGS. d to e. Busy photoresist 14 except for the gate electrode formation area
The pGaAs substrate 1r is covered with a phosphoric acid etching solution.
While etching to form a recess structure, GaA
The thickness of the active layer 1' of s is adjusted so that a predetermined pinch-off voltage can be obtained as a gate electrode ((9)d). Photoresist 14'? After removing, use A4 as gate metal.
Then Ad/Tik is deposited (Figure e). The dimensions of this gate electrode are calculated by 5 depending on the shape and dimensions of the upper layer of the Si 3N4 film in the spacer shown in FIG. Next, the ohmic electrode formation plan will be explained using diagrams f. The ohmic area is covered with a photoresist 24 except for the pole forming area, and the Al''!, or A e / T i 2 that adheres to the ohmic forming area is
After removing by etching, AuG is used as ohmic metal 6.
e/Niv? ! (Fig. f) At this time, the dimensions of the ohmic electrode are also affected by the shape and dimensions of the Si3N4 film of the spacer. After removing 24 layers of photoresist (Fig. g),
A photoresist 34 is processed so as to cover only the gate and ohmic electrode that have already been formed. If the 8i0a film 2 of the spacer is sufficiently thick, there will be a sufficient distance between the 8ialq4 film 5 and the electrodes, so the photoresist 34 will fit in between and completely protect each electrode. Next, the photoresist 34r is used as a mask and unnecessary gate metal 5r is removed by etching.
ＣＦ４ ドライエツチングによりスペーサの５ｒ３Ｎ
４膜３ｒ除去し、３ｉ０ｓ＋膜２ケ途中までエッチする
（図ｈ）。さらに弗酸−弗ｒヒアンモニウム混合液で残
りの５ｉ（ｌ膜ｒオーバーエツチング気味に除去？つづ
けるとサイドエッチによりホトレジスト３４の下の部分
にあった５ｉＱ２膜も完全に除去されるとともに同時に
残りの５ｉａＮ４膜及び５ｉａＮ４膜上のＡｕＧｅ／Ｎ
ｉ も除去することができる。このようにしてスペー
サ七すべて除去した後ホトレジスト３４奮除去しく図”
Ｌ合金操作によりＧａＡ、ｓとＡ ｕ Ｇ ｅ ／ Ｎ
ｉ との間にオーミックコンタクｌ−ｋとる。最後
に５ｉａＮ４１３２保護膜として成長させておおう（図
ｊ）。5r3N spacer by CF4 dry etching
4 film 3r is removed, and 3i0s+ film 2 is etched halfway (Figure h). Furthermore, the remaining 5i(l film r) was removed with a mixed solution of hydrofluoric acid and fluorhyammonium, with a slight overetching.Continuing, the 5iQ2 film under the photoresist 34 was completely removed by side etching, and at the same time, the remaining 5i(l film) was removed. 5iaN4 film and AuGe/N on 5iaN4 film
i can also be removed. After removing all seven spacers in this way, the photoresist was then removed.
GaA, s and A u G e /N by L alloy operation
An ohmic contact l-k is established between i and i. Finally, a 5iaN4132 protective film is grown (Figure j).
上記の説明かられかるように、本発明による製造方法で
けＧ ａＡｓ Ｆ’ Ｅ Ｔのゲート・オーミック間隔
は一度図すの段階のホトレジスト４の間隔葡キめればそ
れ以後の工程で行なうホトレジスト加工１４．２４．３
４の目合せ精度に影響されることがない。また電極形成
６ Ｓ ｉ ３Ｎ４−８ ｉ（ｌのスペーサのみによっ
てきまりホトレジスタ？用いない。As can be seen from the above description, in the manufacturing method according to the present invention, the gate ohmic spacing of the GaAs F' ET can be adjusted once the spacing of the photoresist 4 at the step of drawing is determined. Processing 14.24.3
It is not affected by the alignment accuracy in step 4. In addition, the electrode formation is determined only by the spacer 6S i 3N4-8i (1) and no photoresistor is used.
特にゲート電極形成の場合には全くホトレジスタがＧ
ａ Ａ ｓ基板上にない（図ｅ）から極めて信頼性の高
いショットキ電極が形成される。Especially in the case of gate electrode formation, the photoresistor is completely
An extremely reliable Schottky electrode is formed from the a As not on the substrate (Figure e).
これによって超高周波で特性の揃い１ しかも高信頼性
のＧａＡｓ ＦＥＴ ｆ得ることができる。This makes it possible to obtain a GaAs FET f with uniform characteristics and high reliability at ultra-high frequencies.
図は本発明の一実施例ケ、具体例で示した工稈順欠示し
たものである。
３、ｌ’−＝−ＧａＡｓ基板、２・・・・・・５ＩＯ２
，３，１３・・・・・・８ｉａＮ４．４＋ １４１
２４．３４・・・・・・ホトレジスト、５・・・・・・
Ａ４またはＡｌｌ／Ｔ ｉ 、 ｆｉ・・・・・・Ａ
ｕＧｅ／Ｎｉ ０The figure shows one embodiment of the present invention, with the culm order shown in the specific example not shown. 3, l'-=-GaAs substrate, 2...5IO2
,3,13...8iaN4.4+ 141
24.34...Photoresist, 5...
A4 or All/T i, fi...A
uGe/Ni 0
Claims (1)
ミック電極であるリセス構造のＣ１ａ Ａ Ｓ電界効果
形トランジスタの製造において＊ Ｇ ａ Ａ ｓ基板
上に２種の薄膜ｒ成長させる工程と、ポトレジスト加工
でゲートおよびオーミック電極の形成部の窓あけ勿同時
に行なう工程と、前記二層のエラテンクレートの差ｒ利
用して上層が下層よりＶより出した構造の所定の電極位
置にある二層構造のスペーツーｒ形成する工程と勿含み
、以後の工程でゲート電極、オーミック電極形成ケ夫々
別個に行ない。 各電極の位置、相互間の距離が前記スペーサの上層によ
り完全に定まＶ、特にゲート電極形成のときにはホト・
レジスタが基板上に存在しないこと？特徴とする（）
ａ Ａ ８電界効果形トランジスタの製造方法。[Claims] In the production of a recessed C1a AS field effect transistor in which the gate is a Schottky electrode and the source and drain are ohmic electrodes, a step of growing two types of thin films on a G a As substrate; The two layers are placed at predetermined electrode positions in a structure in which the upper layer protrudes from the V than the lower layer by making use of the difference r between the two layers' Elaten crates. In addition to the step of forming the spacer structure, the gate electrode and ohmic electrode are formed separately in subsequent steps. The position of each electrode and the distance between them are completely determined by the upper layer of the spacer, especially when forming the gate electrode.
That there are no resistors on the board? Feature()
a Method for manufacturing an A8 field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15746482A JPS5947771A (en) | 1982-09-10 | 1982-09-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15746482A JPS5947771A (en) | 1982-09-10 | 1982-09-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5947771A true JPS5947771A (en) | 1984-03-17 |
Family
ID=15650234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15746482A Pending JPS5947771A (en) | 1982-09-10 | 1982-09-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947771A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104483A (en) * | 1986-10-22 | 1988-05-09 | Mitsubishi Electric Corp | Semiconductor device |
| GB2534519A (en) * | 2013-10-31 | 2016-07-27 | Kawasaki Heavy Ind Ltd | Hydraulic shovel drive system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162461A (en) * | 1978-06-13 | 1979-12-24 | Matsushita Electric Ind Co Ltd | Manufacture for semiconductor device |
| JPS5730376A (en) * | 1980-07-30 | 1982-02-18 | Fujitsu Ltd | Manufacture of schottky barrier fet |
-
1982
- 1982-09-10 JP JP15746482A patent/JPS5947771A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54162461A (en) * | 1978-06-13 | 1979-12-24 | Matsushita Electric Ind Co Ltd | Manufacture for semiconductor device |
| JPS5730376A (en) * | 1980-07-30 | 1982-02-18 | Fujitsu Ltd | Manufacture of schottky barrier fet |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63104483A (en) * | 1986-10-22 | 1988-05-09 | Mitsubishi Electric Corp | Semiconductor device |
| GB2534519A (en) * | 2013-10-31 | 2016-07-27 | Kawasaki Heavy Ind Ltd | Hydraulic shovel drive system |
| GB2534519B (en) * | 2013-10-31 | 2019-12-11 | Kawasaki Heavy Ind Ltd | Hydraulic excavator drive system |
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