JPH0319228A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH0319228A JPH0319228A JP15431589A JP15431589A JPH0319228A JP H0319228 A JPH0319228 A JP H0319228A JP 15431589 A JP15431589 A JP 15431589A JP 15431589 A JP15431589 A JP 15431589A JP H0319228 A JPH0319228 A JP H0319228A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- insulating film
- aluminum
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 10
- 238000000576 coating method Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract 3
- 238000000151 deposition Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 239000011229 interlayer Substances 0.000 abstract description 16
- 229910052681 coesite Inorganic materials 0.000 abstract description 9
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 9
- 229910052682 stishovite Inorganic materials 0.000 abstract description 9
- 229910052905 tridymite Inorganic materials 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 239000010408 film Substances 0.000 abstract 15
- 239000010409 thin film Substances 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 22
- 229910052782 aluminium Inorganic materials 0.000 description 22
- 239000010410 layer Substances 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に関し、特に配
線構造の平担化技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a technique for flattening a wiring structure.
従来、半導体集積回路装置の配線構造は第３図に示す製
造方法で形成される。第３図（ａ）に示すようにシリコ
ン基板ｌ上に第１の層間絶縁膜として、例えば酸化シリ
コン（ＳｉＯｚ）膜２等が形成される。この上に第３図
（ｂ）のように全面にアルミニウム３を被着し、フォト
リングラフィー技術およびエッチング技術を用いて、第
３図（Ｃ）のように所定の形状の配線パターンを形戒す
る。その上に第２の層間絶縁膜として、Ｓｉｎ．膜５を
第３図（ｄ）のように堆積させ、さらに上層の配線（図
示せず）を形成していた。Conventionally, the wiring structure of a semiconductor integrated circuit device is formed by a manufacturing method shown in FIG. As shown in FIG. 3(a), a silicon oxide (SiOz) film 2, for example, is formed as a first interlayer insulating film on a silicon substrate l. On top of this, aluminum 3 is deposited on the entire surface as shown in Fig. 3(b), and a wiring pattern of a predetermined shape is formed using photolithography and etching techniques as shown in Fig. 3(C). do. Thereon, a second interlayer insulating film of Sin. A film 5 was deposited as shown in FIG. 3(d), and upper layer wiring (not shown) was further formed.
上述した従来の配線の製造方法では、配線パターンの段
差がそのまま残るため、その上に堆積させる層間絶縁膜
の被覆性が問題となる。例えば第３図（ｄ）に示したＡ
の部分においては、平坦ｉに比べて明らかに層間絶縁膜
５の膜厚が薄くなっている。電気的絶縁性を確保するた
めにはＡ部の膜厚を厚くしなければならないが、そのた
めには層間絶縁膜全体を厚く堆積する必要があり、多層
の配線構造を考える場合には上層配線との接続、上層配
線の被覆性等の問題が生じるという欠点がある。In the above-described conventional wiring manufacturing method, the step difference in the wiring pattern remains, which poses a problem in the coverage of the interlayer insulating film deposited thereon. For example, A shown in FIG. 3(d)
In the portion , the thickness of the interlayer insulating film 5 is obviously thinner than in the flat i. In order to ensure electrical insulation, the thickness of part A must be increased, but to do so, the entire interlayer insulating film must be thickly deposited, and when considering a multilayer wiring structure, it is necessary to increase the thickness of the interlayer insulation film. However, there are disadvantages in that problems arise such as connection of wires, coverage of upper layer wiring, etc.
本発明の目的は、配線部における層間絶縁膜の平坦性を
向上させた半導体集積回路装置の製造方法を提供するも
のである。An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device in which the flatness of an interlayer insulating film in a wiring portion is improved.
本発明の配線構造の製造方法は、半導体基板上に絶縁膜
を堆積させる工程と、この絶縁膜に所定の深さ、平面形
状を有する開孔を形戒する工程と、開孔部内と絶縁膜上
面において、互いに電気的に分離するように配線材を被
着させる工程と、前記工程に続いて少なくとも前記開孔
を埋めるように塗布膜を塗布，加熱する工程と、前記開
孔部内に形成された配線材の上部が露出するまで全面エ
ッチングする工程とを含んで構戊される。The method for manufacturing a wiring structure of the present invention includes a step of depositing an insulating film on a semiconductor substrate, a step of forming an aperture having a predetermined depth and a planar shape in the insulating film, and a step of depositing an insulating film on a semiconductor substrate. a step of depositing a wiring material on the upper surface so as to be electrically isolated from each other, a step of applying and heating a coating film so as to fill at least the opening, and a step of applying and heating a coating film so as to fill at least the opening; The process includes a step of etching the entire surface of the wiring material until the upper part thereof is exposed.
このような製造方法により各配線層および各絶縁膜上面
は平坦化され、積層構造においても、著しい段差を生じ
ることはない。By such a manufacturing method, the upper surface of each wiring layer and each insulating film is flattened, and even in a laminated structure, no significant step difference occurs.
〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の工程断面図である。シ
リコン基板１上に第１図（ａ）に示すように層間絶縁膜
としてＳｉＣｈ膜２を形戒する。この層間膜は絶縁性を
確保するに必要な厚さと配線材の厚さを加えた厚さより
厚く堆積する必要があり、例えば１．５μｍ程度堆積す
る。次に第１図（ｂ）に示すようにフォトリングラフィ
技術を用いて配線形状にＳｉｎ２膜２を１．０μｍ程度
エッチングする。ここでＳｉ０２膜２の溝の底とシリコ
ン基板１との距離は、絶縁分離厚となるようにエッチン
グ量を決める。続いて、配線材のアルミニウムを第１図
（Ｃ）のように全面に被着させる。FIG. 1 is a process sectional view of a first embodiment of the present invention. A SiCh film 2 is formed as an interlayer insulating film on a silicon substrate 1 as shown in FIG. 1(a). This interlayer film needs to be deposited to be thicker than the sum of the thickness required to ensure insulation and the thickness of the wiring material, and is deposited to a thickness of about 1.5 μm, for example. Next, as shown in FIG. 1(b), the Sin2 film 2 is etched to a thickness of about 1.0 μm in the shape of a wiring using a photolithography technique. Here, the etching amount is determined so that the distance between the bottom of the groove of the Si02 film 2 and the silicon substrate 1 corresponds to the insulation isolation thickness. Subsequently, aluminum as a wiring material is deposited on the entire surface as shown in FIG. 1(C).
このとき、アルミニウムの厚さは、先に形成した溝の深
さの半分程度となるようにする。ここでは０．５μｍ程
度被着させる。このようにそれぞれの膜厚を定めること
により、被着したアルミニウムは溝の段部で分離し、溝
内部の部分とＳｉＯ２膜２上面の部分とに分かれる。こ
の状態で塗布Ｓｔｏｗ膜４を塗布すると、塗布膜は溝の
部分に溜まり、溝以外の領域では薄く、溝部では厚く形
成される．溶剤を蒸発させるため３００〜４００℃で加
熱すると第１図（ｄ）の構造となる。次に、上部に付着
した薄い塗布Ｓｉ０２膜をウェットエッチングにより除
去し、第１図（ｅ）に示すように上部のアルミニウムを
露出させる。第１図（ｆ）に示すようにアルミニウムを
ウェットエッチングにより除去し、Ｓｉｎ．膜２および
４を全面エッチングして溝の部分のアルミニウムを露虫
させる。このとき、塗布Ｓｉｆ２膜４と層間膜としての
Ｓｉｆｔ膜２のエッチング速度は同じであるため、アル
ミニウムが露出した時点で第１図（ｇ）のように配線領
域の構造は極めて平坦となる。この後、層間絶縁膜とし
てＳｉＯ２膜５を堆積させると第ｌ図（ｈ）の構造が得
られる。At this time, the thickness of the aluminum should be approximately half the depth of the previously formed groove. Here, the thickness is about 0.5 μm. By determining the respective film thicknesses in this manner, the deposited aluminum is separated at the step of the groove, and is divided into a portion inside the groove and a portion on the upper surface of the SiO2 film 2. When the coating Stow film 4 is applied in this state, the coating film accumulates in the grooves, and is formed thinly in areas other than the grooves and thickly in the grooves. When heated at 300 to 400° C. to evaporate the solvent, the structure shown in FIG. 1(d) is obtained. Next, the thin coated Si02 film attached to the top is removed by wet etching to expose the top aluminum as shown in FIG. 1(e). As shown in FIG. 1(f), aluminum was removed by wet etching and the Sin. The entire surface of the films 2 and 4 is etched to expose the aluminum in the grooves. At this time, since the etching rate of the applied Sif2 film 4 and the Sift film 2 as an interlayer film are the same, the structure of the wiring region becomes extremely flat as shown in FIG. 1(g) when aluminum is exposed. Thereafter, a SiO2 film 5 is deposited as an interlayer insulating film to obtain the structure shown in FIG. 1(h).
第２図は本発明の第２の実施例の工程断面図である。本
実施例では第１層配線と第２層配線の電気的接続に本発
明を応用した場合を示す。第１の実施例に示した如く、
シリコン基板１１上のＳｉｆｔ膜１２に第１層のアルミ
ニウム配線１３を形成し、平坦化した後、層間絶縁膜と
してＳｉＯｚ膜１４を全面に１．０μｍ程度堆積し、続
いてアルミニウム配線１３へのフンタクト孔を開孔し、
さらにアルミニウムを０．５μｍ程度の厚さに被着し、
第２図（ａ）の構造を得る。ここでコンタクト孔内部と
Ｓ ｓ Ｃｈ膜１ ４上面とにアルミニウムが分離スる
ようにする。また、コンタクト孔内部に被着したアルミ
ニウム１５は第ｌ層のアルミニウム配線１３と接続され
る。続いて塗布Ｓｉｎ２膜ｌ６の塗布した後、第２図（
ｂ）のように加熱処理、塗布膜の薄い部分のエッチング
によう除去、上部のアルミニウム１５の除去を行う。次
に、全面エッチングにより塗布膜１６およびＳｉｎ２膜
ｌ４をコンタクト孔内部のアルミニウム１５の上面が露
出するまで除去し、さらに第２図（ｃ）のように層間絶
縁膜としてＳｉＯｚ膜１７を１．０μｍ程度堆積させる
。続いてＳｉＯ２膜１７を配線形状にエッチングし、コ
ンタクト孔部分のアルミニウム１５上面が露出する深さ
に形成する。第２層のアルミニウム配線１８を０．５μ
ｍ程度の厚さに被着し、塗布ＳｉＯｚ膜１９を塗布・加
熱形成して第２図（ｄ）の構造を得る。ここで第２図（
ｄ）に示されているように第１層配線ｌ３と第２層配線
１８とが、コンタクト孔のアルミニウム１５を介して導
通している構造となっている。この後、Ｓｉ（ｈ膜１７
．１９および、ＳｉＯｚ膜１７上部のアルミニウム配線
の除去、全面エッチングと再度のＳｉｎ．膜２０の堆積
により第２図（ｅ）の構造を得る。以上から明らかなよ
うに、２層配線構造としても極めて平坦な形状が得られ
る。FIG. 2 is a process sectional view of a second embodiment of the present invention. This embodiment shows a case where the present invention is applied to electrical connection between first layer wiring and second layer wiring. As shown in the first embodiment,
After forming the first layer of aluminum wiring 13 on the Sift film 12 on the silicon substrate 11 and planarizing it, a SiOz film 14 of about 1.0 μm is deposited on the entire surface as an interlayer insulating film, and then a dry film is applied to the aluminum wiring 13. Drill a hole,
Furthermore, aluminum is coated to a thickness of about 0.5 μm,
The structure shown in FIG. 2(a) is obtained. Here, aluminum is separated into the inside of the contact hole and the upper surface of the S s Ch film 14. Furthermore, the aluminum 15 deposited inside the contact hole is connected to the l-th layer aluminum wiring 13. Subsequently, after coating the Sin2 film l6, as shown in FIG.
As in b), heat treatment is performed, the thin portion of the coating film is removed by etching, and the upper aluminum 15 is removed. Next, the coating film 16 and the Sin2 film 14 are removed by etching the entire surface until the upper surface of the aluminum 15 inside the contact hole is exposed, and then a 1.0 μm thick SiOz film 17 is added as an interlayer insulating film as shown in FIG. 2(c). Deposit to a certain extent. Subsequently, the SiO2 film 17 is etched into a wiring shape to a depth that exposes the upper surface of the aluminum 15 in the contact hole portion. The second layer aluminum wiring 18 is 0.5μ
A SiOz film 19 is coated and heated to form the SiOz film 19 to a thickness of about 100 m, thereby obtaining the structure shown in FIG. 2(d). Here, Figure 2 (
As shown in d), the first layer wiring 13 and the second layer wiring 18 are electrically connected through the aluminum 15 of the contact hole. After this, Si(h film 17
．． 19 and the aluminum wiring on the top of the SiOz film 17 is removed, the entire surface is etched, and the SiOz film 17 is etched again. Deposition of film 20 results in the structure shown in FIG. 2(e). As is clear from the above, an extremely flat shape can be obtained even with a two-layer wiring structure.
以上説明したように、本発明では、絶縁膜に溝を形成し
、その溝部に配線を埋め込むことによって極めて平坦な
配線構造を得ることができるという効果がある。As described above, the present invention has the advantage that an extremely flat wiring structure can be obtained by forming a groove in an insulating film and burying a wiring in the groove.
したがって配線を多層化しても配線の段差によるオープ
ン不良や上下層配線間の層間膜が薄くなることに起因す
るショート不良を大幅に低減することが可能で、多層配
線構造での歩留り向上が可能である。Therefore, even if the wiring is multilayered, it is possible to significantly reduce open defects due to differences in wiring levels and short defects caused by thinning of the interlayer film between upper and lower layer wiring, and it is possible to improve yields in multilayer wiring structures. be.
なお、層間絶縁膜はＳｉｎ２膜でなく、例えばシリコン
窒化膜でも良く、塗布ＳｉＣｈ膜は塗布ＰＳＧ膜等でも
何ら本発明の効果を損ねるものではない。また、配線材
はアルミニウムに限らず、利用できることも言うまでも
ない。Note that the interlayer insulating film may be, for example, a silicon nitride film instead of the Sin2 film, and the applied SiCh film may be a coated PSG film or the like without detracting from the effects of the present invention. Furthermore, it goes without saying that the wiring material is not limited to aluminum, and can be used as well.
第１図は本発明の第１の実施例の工程断面図、第２図は
本発明の第２の実施例の工程断面図、第３図は従来の配
線構造の工程断面図である。
１，１１・・・・・・シリコン基板、２，５，１２，１
４，１７．２０・・・・・・ＳｉＯ２膜、３，１３，１
５．１８・・・・・・アルミニウム、４，１６．１９・
・・・・・塗布Ｓｉｎ．膜。FIG. 1 is a process sectional view of a first embodiment of the invention, FIG. 2 is a process sectional view of a second embodiment of the invention, and FIG. 3 is a process sectional view of a conventional wiring structure. 1, 11... Silicon substrate, 2, 5, 12, 1
4,17.20...SiO2 film, 3,13,1
5.18... Aluminum, 4,16.19.
...Coating Sin. film.
Claims (1)
定の深さ、平面形状を有する開孔部を形成する工程と、
前記開孔部内および前記絶縁膜上面のそれぞれにそれら
の間で互いに電気的に分離するように導電材を被着させ
る工程と、少なくとも前記開孔を埋めるように塗布膜を
形成する工程と、前記開孔部内に形成された前記導電材
の上部が露出するまで、全面をエッチングする工程とを
含むことを特徴とする半導体集積回路装置の製造方法。a step of forming an insulating film on a semiconductor substrate; a step of forming an opening having a predetermined depth and planar shape in the insulating film;
a step of depositing a conductive material in each of the openings and on the upper surface of the insulating film so as to be electrically isolated therebetween; and a step of forming a coating film so as to fill at least the openings; A method for manufacturing a semiconductor integrated circuit device, comprising the step of etching the entire surface of the conductive material formed in the opening until the upper part thereof is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15431589A JPH0319228A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15431589A JPH0319228A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319228A true JPH0319228A (en) | 1991-01-28 |
Family
ID=15581435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15431589A Pending JPH0319228A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319228A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6395863B2 (en) | 2000-02-02 | 2002-05-28 | Microtouch Systems, Inc. | Touch screen with polarizer and method of making same |
-
1989
- 1989-06-15 JP JP15431589A patent/JPH0319228A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6395863B2 (en) | 2000-02-02 | 2002-05-28 | Microtouch Systems, Inc. | Touch screen with polarizer and method of making same |
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