JPH05235175A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPH05235175A
JPH05235175A JP3653792A JP3653792A JPH05235175A JP H05235175 A JPH05235175 A JP H05235175A JP 3653792 A JP3653792 A JP 3653792A JP 3653792 A JP3653792 A JP 3653792A JP H05235175 A JPH05235175 A JP H05235175A
Authority
JP
Japan
Prior art keywords
wiring layer
layer
insulating film
interlayer insulating
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3653792A
Other languages
Japanese (ja)
Other versions
JP2758765B2 (en
Inventor
Atsushi Shoji
敦 荘司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP3653792A priority Critical patent/JP2758765B2/en
Publication of JPH05235175A publication Critical patent/JPH05235175A/en
Application granted granted Critical
Publication of JP2758765B2 publication Critical patent/JP2758765B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form through holes in the same shape by a method wherein, before the formation of the through holes, the part of a polyimide layer on a gate electrode is masked and then the other parts of the polyimide layer is etched away by an amount corresponding to the thickness of the gate electrode. CONSTITUTION:After the formation of an aluminum wiring layer 1, a plasma nitride film 3 is thinly grown on the whole surface to be coated with a thick polyimide layer 4 on the film 3. Next, after finishing the polyimide curing step, the polyimide layer 4 above a gate electrode 2, i.e., a thinned part, is masked with a photoresist 7 so as to etch away the other parts including the part of polyimide layer 4 on the second part 12 of the lower aluminum wiring layer 1 from the surface thereof by an amount corresponding to the thickness of the gate electrode 2. Thus, the thickness of the polyimide layer 4 on the second part 12 of the lower aluminum wiring layer 1 is equalized with the thickness of the polyimide layer 4 on the first part 11. Accordingly, the through holes 18, 28 can be formed in the same shape.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係わり、特に金属多層配線を形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming metal multi-layer wiring.

【０００２】[0002]

【従来の技術】従来のアルミニウムの２層構造の製造方
法は図２に示す様に、下層のアルミニウム配線層１上に
プラズマ窒化膜３を成長しポリイミド層４を塗布するこ
とにより層間絶縁膜として素子全体の表面を平坦にす
る。その後、下層のアルミニウム配線層１と上層のアル
ミニウム配線層１０との導通をとる為のスルーホール８
を形成する。このスルーホール８は、始めに等方性エッ
チングによりテーパー９を作り、そのあとで異方性エッ
チングを行なって形成する。2. Description of the Related Art As shown in FIG. 2, a conventional method for manufacturing a two-layer structure of aluminum is used as an interlayer insulating film by growing a plasma nitride film 3 on a lower aluminum wiring layer 1 and applying a polyimide layer 4 thereon. The surface of the entire device is made flat. After that, through holes 8 for establishing electrical connection between the lower aluminum wiring layer 1 and the upper aluminum wiring layer 10 are formed.
To form. The through hole 8 is formed by first forming a taper 9 by isotropic etching and then performing anisotropic etching.

【０００３】ところが、下層のアルミニウム配線層１よ
りさらに下の層、たとえばゲート電極２が形成されてい
る場合、このゲート電極２が下に存在している箇所と存
在していない箇所とでは下層のアルミニウム配線層１上
でポリイミド層４の膜厚差が生じる。ゲート電極２が下
に存在していない箇所は存在している箇所よりもゲート
電極の膜厚分だけポリイミド層４の膜厚が厚くなってい
る。そこでスルーホールを形成する際に、ポリイミド層
が厚い部分に合せて等方性エッチングを行なう為に、下
にゲート電極が存在する箇所は、等方性エッチングだけ
で下層のアルミニウム配線層上でポリイミド層がなくな
り、下層のアルミニウム配線層上には薄いプラズマ窒化
膜だけが残る。However, when a layer further below the lower aluminum wiring layer 1, for example, the gate electrode 2 is formed, the portion below the aluminum electrode layer 1 and the portion not including the gate electrode 2 are lower layers. A difference in film thickness of the polyimide layer 4 occurs on the aluminum wiring layer 1. The polyimide layer 4 is thicker in the portion where the gate electrode 2 does not exist below than in the portion where the gate electrode 2 does not exist. Therefore, when forming a through hole, in order to perform isotropic etching in accordance with the thick portion of the polyimide layer, the portion where the gate electrode exists below is formed by the isotropic etching only on the lower aluminum wiring layer. The layers disappear, leaving only a thin plasma nitride film on the underlying aluminum wiring layer.

【０００４】[0004]

【発明が解決しようとする課題】この従来のスルーホー
ルの形成方法においては、下にゲート電極が存在する箇
所は、下層のアルミニウム配線層上の層間絶縁膜は薄く
なる為、図２（ｂ）に示す様に、上層のアルミニウム配
線層を形成する際に薄い層間絶縁膜に穴が開き、下層の
アルミニウム配線層がエッチングされそこに溝１４が形
成されてしまうという問題点があった。In this conventional method of forming a through hole, the interlayer insulating film on the lower aluminum wiring layer is thin at the portion where the gate electrode exists below, so that FIG. As shown in (1), there is a problem that a hole is formed in the thin interlayer insulating film when the upper aluminum wiring layer is formed, and the lower aluminum wiring layer is etched to form the groove 14 therein.

【０００５】[0005]

【課題を解決するための手段】本発明の特徴は、半導体
基板と、該半導体基板の主面上に設けられた、たとえば
ゲート電極を構成する第１層目の配線層と、該第１層目
の配線層を被覆する第１の層間絶縁膜と、該第１の層間
絶縁膜上に設けられた、たとえばアルミニウム配線層の
第２層目の配線層と、該第２層目の配線層を被覆する、
たとえばポリイミド層を含む第２の層間絶縁膜と、該第
２の層間絶縁膜に形成され、該第１層目の配線層上方の
該第２層目の配線層の部分を露出させる第１のスルーホ
ールと、該第２の層間絶縁膜に形成され、下に該第１層
目の配線層が存在しない該第２層目の配線層の部分を露
出させる第２のスルーホールと、該第１および第２のス
ルーホールを通して該第２層目の配線層のそれぞれの部
分に接続する第３層目の配線層とを有する半導体装置の
製造方法において、前記第１のスルーホールが形成され
る前記第１層目の配線層上方の前記第２の層間絶縁膜の
箇所をマスクして、前記第２のスルーホールが形成され
る箇所を含んだ前記第２の層間絶縁膜の他の箇所の表面
を前記第１層目の配線層の膜厚程度エッチング除去し、
しかる後、前記第１および第２のスルーホールを同時に
形成する半導体装置の製造方法にある。A feature of the present invention is that a semiconductor substrate, a first wiring layer which is provided on a main surface of the semiconductor substrate and constitutes, for example, a gate electrode, and the first layer are provided. A first interlayer insulating film for covering the second wiring layer, a second wiring layer of, for example, an aluminum wiring layer provided on the first interlayer insulating film, and a second wiring layer Coating,
For example, a second interlayer insulating film including a polyimide layer and a first interlayer insulating film which is formed on the second interlayer insulating film and exposes a portion of the second wiring layer above the first wiring layer. A through hole, a second through hole formed in the second interlayer insulating film and exposing a portion of the second wiring layer below which the first wiring layer does not exist; In the method of manufacturing a semiconductor device having a third wiring layer connected to respective portions of the second wiring layer through the first and second through holes, the first through hole is formed. A portion of the second interlayer insulating film including a portion where the second through hole is formed is masked at a portion of the second interlayer insulating film above the first wiring layer. The surface is removed by etching to the thickness of the first wiring layer,
Then, there is a method of manufacturing a semiconductor device in which the first and second through holes are simultaneously formed.

【０００６】これにより、ゲート電極が下に存在する箇
所と存在しない箇所とのポリイミド層の膜厚が同じにな
り、どちらも同じ形状のスルーホールを形成することが
できる。As a result, the film thickness of the polyimide layer becomes the same at the portion where the gate electrode exists below and the portion where the gate electrode does not exist, and through holes having the same shape can be formed in both.

【０００７】[0007]

【実施例】次に本発明について図面を参照して説明す
る。図１（ａ），（ｂ），（ｃ）は本発明の一実施例を
工程順に示した断面図である。The present invention will be described below with reference to the drawings. 1A, 1B, and 1C are cross-sectional views showing an embodiment of the present invention in the order of steps.

【０００８】シリコン基板１の主表面にゲート絶縁膜１
３を介してゲート電極２が形成され、このゲート電極を
含み全体的にシリコン酸化膜５によって被覆されてい
る。シリコン酸化膜５上に下層のアルミニウム配線層１
が形成されている。このアルミニウム配線層１の第１の
部分１１はゲート電極２の上方に位置し、一方、第２の
部分１２は下にゲート電極２が存在しない場所に位置し
ている。この下層のアルミニウム配線層１の形成後、全
体的にプラズマ窒化膜３を薄く成長させ、その上に厚い
ポリイミド層４を塗布法で形成する。これにより、図１
（ａ）に示す様に素子全体の上表面が平坦になり、下に
ゲート電極２が存在する下層のアルミニウム配線層１の
第１の部分１１上のポリイミド層の箇所は、下にゲート
電極２が存在しない下層のアルミニウム配線層１の第２
の部分１２上のポリイミド層の箇所より薄くなってい
る。The gate insulating film 1 is formed on the main surface of the silicon substrate 1.
A gate electrode 2 is formed via the gate electrode 3, and the gate electrode 2 is covered with the silicon oxide film 5 as a whole. The lower aluminum wiring layer 1 on the silicon oxide film 5
Are formed. The first portion 11 of the aluminum wiring layer 1 is located above the gate electrode 2, while the second portion 12 is located below where the gate electrode 2 does not exist. After the formation of the lower aluminum wiring layer 1, the plasma nitride film 3 is thinly grown as a whole, and a thick polyimide layer 4 is formed thereon by a coating method. As a result,
As shown in (a), the upper surface of the entire device is flattened, and the polyimide layer on the first portion 11 of the lower aluminum wiring layer 1 where the gate electrode 2 exists below the gate electrode 2 Second of the lower aluminum wiring layer 1 in which there is no
Is thinner than the portion of the polyimide layer on the portion 12.

【０００９】次にポリイミドキュアを行った後、フォト
レジスト７によってゲート電極２上方のポリイミド層の
箇所すなわち薄くなっている箇所をマスキングして、下
層のアルミニウム配線層１の第２の部分１２上のポリイ
ミド層の箇所を含めた他の箇所をその表面からゲート電
極２の厚さ分だけエッチング除去する。これにより下層
のアルミニウム配線層１の第２の部分１２上のポリイミ
ド層の膜厚と第１の部分１１上のポリイミド層の膜厚と
が同じになる（図１（ｂ））。After performing a polyimide cure, a portion of the polyimide layer above the gate electrode 2, that is, a thin portion is masked with a photoresist 7 and the second portion 12 of the lower aluminum wiring layer 1 is masked. Other parts including the part of the polyimide layer are removed by etching from the surface by the thickness of the gate electrode 2. As a result, the film thickness of the polyimide layer on the second portion 12 of the lower aluminum wiring layer 1 becomes the same as the film thickness of the polyimide layer on the first portion 11 (FIG. 1 (b)).

【００１０】続いて、等方性エッチングによりテーパー
９を作り、引続いて異方性エッチングにより下層のアル
ミニウム配線層１の第１の部分１１および第２の部分１
２にそれぞれ達する第１および第２のスルーホール１
８，２８を形成する（図１（ｃ））。その後、図２
（ｂ）と同様に、これらのスルーホールを通して下層の
アルミニウム配線層の第１の部分および第２の部分にそ
れぞれ接続する上層のアルミニウム配線層を形成する。Then, a taper 9 is formed by isotropic etching, and then anisotropic etching is performed to form the first portion 11 and the second portion 1 of the lower aluminum wiring layer 1.
First and second through holes 1 reaching 2 respectively
8 and 28 are formed (FIG. 1C). After that, Figure 2
Similar to (b), an upper aluminum wiring layer connected to the first portion and the second portion of the lower aluminum wiring layer through these through holes is formed.

【００１１】[0011]

【発明の効果】以上説明したように本発明は、スルーホ
ール形成前にゲート電極上方のポリイミド層の箇所をマ
スクしポリイミド層の他の箇所をゲート電極の膜厚分だ
けエッチングするので、ゲート電極が下に存在すること
の有無にかかわらず、スルーホールは同じ形状に形成す
ることができるという効果を有する。As described above, according to the present invention, the portion of the polyimide layer above the gate electrode is masked and the other portions of the polyimide layer are etched by the thickness of the gate electrode before forming the through hole. Has the effect that the through-holes can be formed in the same shape regardless of whether or not there is an underneath.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例の製造方法を工程順に示した
断面図。FIG. 1 is a sectional view showing a manufacturing method according to an embodiment of the present invention in the order of steps.

【図２】従来技術の製造方法を工程順に示した断面図。FIG. 2 is a cross-sectional view showing a manufacturing method of a conventional technique in the order of steps.

【符号の説明】[Explanation of symbols]

１ 下層のアルミニウム配線層 ２ ゲート電極 ３ プラズマ窒化膜 ４ ポリイミド層 ５ シリコン酸化膜 ６ シリコン基板 ７ フォトレジスト ８，１８，２８ スルーホール ９ テーパー １０ 上層のアルミニウム配線層 １１ 下層のアルミニウム配線層の第１の部分 １２ 下層のアルミニウム配線層の第２の部分 １３ ゲート絶縁膜 １４ 溝 1 Lower Aluminum Wiring Layer 2 Gate Electrode 3 Plasma Nitride Film 4 Polyimide Layer 5 Silicon Oxide Film 6 Silicon Substrate 7 Photoresist 8, 18, 28 Through Hole 9 Taper 10 Upper Aluminum Wiring Layer 11 Lower Aluminum Wiring Layer 1st Part 12 Second part of lower aluminum wiring layer 13 Gate insulating film 14 Groove

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板と、該半導体基板の主面上に
設けられた第１層目の配線層と、該第１層目の配線層を
被覆する第１の層間絶縁膜と、該第１の層間絶縁膜上に
設けられた第２層目の配線層と、該第２層目の配線層を
被覆する第２の層間絶縁膜と、該第２の層間絶縁膜に形
成され、該第１層目の配線層上方の該第２層目の配線層
の部分を露出させる第１のスルーホールと、該第２の層
間絶縁膜に形成され、下に該第１層目の配線層が存在し
ない該第２層目の配線層の部分を露出させる第２のスル
ーホールと、該第１および第２のスルーホールを通して
該第２層目の配線層のそれぞれの部分に接続する第３層
目の配線層とを有する半導体装置の製造方法において、
前記第１のスルーホールが形成される前記第１層目の配
線層上方の前記第２の層間絶縁膜の箇所をマスクして、
前記第２のスルーホールが形成される箇所を含んだ前記
第２の層間絶縁膜の他の箇所の表面を前記第１層目の配
線層の膜厚程度エッチング除去し、しかる後、前記第１
および第２のスルーホールを同時に形成する事を特徴と
する半導体装置の製造方法。1. A semiconductor substrate, a first wiring layer provided on a main surface of the semiconductor substrate, a first interlayer insulating film covering the first wiring layer, and A second wiring layer provided on the first interlayer insulating film, a second interlayer insulating film covering the second wiring layer, and a second interlayer insulating film formed on the second interlayer insulating film; A first through hole for exposing a portion of the second wiring layer above the first wiring layer and a second interlayer insulating film, and the first wiring layer below the first through hole are formed. A second through hole that exposes a portion of the second wiring layer where there are no holes and a third through hole that connects to the respective portions of the second wiring layer through the first and second through holes. In a method of manufacturing a semiconductor device having a wiring layer of a layer,
By masking a portion of the second interlayer insulating film above the first wiring layer where the first through hole is formed,
The surface of the other part of the second interlayer insulating film including the part where the second through hole is formed is removed by etching to the film thickness of the first wiring layer, and then the first part is formed.
And a method of manufacturing a semiconductor device, which comprises simultaneously forming a second through hole. 【請求項２】 前記第２の層間絶縁膜はポリイミド層を
具備し該ポリイミド層の表面に前記エッチングが行なわ
れる事を特徴とする請求項１に記載の半導体装置の製造
方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the second interlayer insulating film includes a polyimide layer, and the surface of the polyimide layer is subjected to the etching. 【請求項３】 前記第２層目の配線層はアルミニウム配
線層であり、前記第１層目の配線層はゲート電極を構成
している事を特徴とする請求項１もしくは請求項２に記
載の半導体装置の製造方法。3. The wiring layer as the second layer is an aluminum wiring layer, and the wiring layer as the first layer constitutes a gate electrode, according to claim 1 or 2. Of manufacturing a semiconductor device of.
JP3653792A 1992-02-24 1992-02-24 Method for manufacturing semiconductor device Expired - Lifetime JP2758765B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3653792A JP2758765B2 (en) 1992-02-24 1992-02-24 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3653792A JP2758765B2 (en) 1992-02-24 1992-02-24 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05235175A true JPH05235175A (en) 1993-09-10
JP2758765B2 JP2758765B2 (en) 1998-05-28

Family

ID=12472536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3653792A Expired - Lifetime JP2758765B2 (en) 1992-02-24 1992-02-24 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2758765B2 (en)

Also Published As

Publication number Publication date
JP2758765B2 (en) 1998-05-28

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