JPH03184356A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH03184356A JPH03184356A JP1324529A JP32452989A JPH03184356A JP H03184356 A JPH03184356 A JP H03184356A JP 1324529 A JP1324529 A JP 1324529A JP 32452989 A JP32452989 A JP 32452989A JP H03184356 A JPH03184356 A JP H03184356A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- lead
- adhesion surface
- pad
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 238000007789 sealing Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 12
- 238000012360 testing method Methods 0.000 abstract description 22
- 230000008878 coupling Effects 0.000 abstract 2
- 238000010168 coupling process Methods 0.000 abstract 2
- 238000005859 coupling reaction Methods 0.000 abstract 2
- 239000000523 sample Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 4
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、半導体装置を構成する金属リードフレーム
状態で半導体装置の電気的特性検査（以下、テストと称
す）を行うに当って、半導体チップとリードフレーム間
の耐電圧を向上するリードフレームに関するものである
。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for testing the electrical characteristics of a semiconductor device (hereinafter referred to as a test) using a metal lead frame that constitutes the semiconductor device. This invention relates to a lead frame that improves the withstand voltage between the lead frame and the lead frame.
［従来の技ｖ＃］
従来、半導体集積回路装置（以下、ＩＣと称す）は、金
属リードフレーム（以下、フレームと称す）を使用して
製造され、樹脂封止後に外部電極となる各リード及びＩ
Ｃ本体と切離し、しかる後テストを行う第１の方法と、
樹脂封止後に外部電極となる各リードだけを切離し、Ｉ
Ｃ本体はフレームにつながった状態でテストを行う第２
の方法が行なわれている。この発明は上記第２の方法に
関するもので、以下第６〜ｌＯ図に従って説明する。[Conventional Technique v#] Conventionally, semiconductor integrated circuit devices (hereinafter referred to as ICs) are manufactured using metal lead frames (hereinafter referred to as frames), and each lead that becomes an external electrode and I
A first method of separating it from the C main body and then testing it;
After resin sealing, each lead that will become an external electrode is cut off, and the I
The C body is connected to the frame in the second test.
method is being used. The present invention relates to the second method, and will be explained below with reference to FIGS. 6 to 10.
第６図は従来のフレームを示す平面図、第７図は従来の
フレームにＩＣチップを搭載し、フレームの各外部リー
ドと配線した状態を示す平面図、第８図は第７図の状態
のフレームに樹脂封止を施した状態を示す平面図、第９
図は第８図のフレームに各外部リードの切断及び曲げ加
工を施した状態を示す平面図、第１Ｏ図は第９図の状態
のフレームのＩＣをテストする状態を示すテスターの断
面図である。Fig. 6 is a plan view showing a conventional frame, Fig. 7 is a plan view showing a state in which an IC chip is mounted on a conventional frame and wired to each external lead of the frame, and Fig. 8 is a plan view of the state shown in Fig. 7. Plan view showing a state in which the frame is resin-sealed, No. 9
The figure is a plan view showing the frame shown in Fig. 8 after cutting and bending each external lead, and Fig. 1O is a sectional view of the tester showing the state in which the IC of the frame shown in Fig. 9 is tested. .
図において、（１）は金属のリードフレームで所定形状
に打ち抜き成形された板材であり（ｌａ）〜（ｌｈ）の
各部分から構成されている。（ｌａ）は第１フレーム枠
、（１ｂ）は第２フレーム枠、（ｌｃ）は第１フレーム
枠（ｌａ）に設けられたピッチ穴、（１ｄ）は第２フレ
ーム枠（Ｉｂ）に設けられたピッチ穴、（ＩＣ）は接着
剤を介しＩＣチップを乗せる為のパッド、（１ｆ）はパ
ッド（ｌｅ）と第１フレーム枠（１ａ）、′１ＰＪｚフ
レーム枠（ｌｂ）とをつなぐ連結リード、（Ｉｇ）はＩ
Ｃの外部電極となる外部リード（１ｈ）を第１フレーム
枠（１ａ）、第２フレーム枠（１ｂ）とつなぐ連結リー
ド、（ｌｈ）はＩＣの外部電極となる外部リードである
。（２）はパッド（１ｅ）にＩＣチップ（３）を接着す
るための接着剤、（４）はＩＣチップ（３）の各電極と
外部リード（ｌｂ）を結ぶワイヤ線、（５）は第７図の
状態のフレームを樹脂封止し、連結リード（Ｉｆ）と外
部リード（ｔｈ）を残して第１フレーム枠（ｌａ）、第
２フレーム枠（ｌｂ）から切断し、切離した外部リード
（ｌｈ）に曲げ加工を施したＩＣである。（５，１）〜
（５，１６）はＩ（：（５）の外部電極リード、（５，
１７）は封止樹脂である。（６）〜（１５）は第９図の
状態のフレームに並んだＩＧ（５）をテストする装置の
各構成部分で、うち（６）〜（９）は第９図の状態のフ
レームを搬送、位置決めするハンドリング装置部を構成
し、また（１１）〜（１５）はＩＣ（５）をテストする
電気計測に係るテスト装置部分を構成しており、（６）
はハンドリング装置部の基礎となるベース板、 （ａ、
ｔ）は第１搬送レール、（８，２）は第２搬送レール、
（７）はベース板（６）と第１搬送レール（ａ、ｔ）
、第２搬送レール（８，２）の間に設けられた中継板、
（８，３）、 （８，４）はカバーレールである。第１
搬送レール（８，１） 、第２搬送レール（８，２ン
カバーレール（８，３） （８，４）は第１フレー
ム枠（ｌａ）、第２フレーム枠（ｌｂ）を受けてガイド
を行う搬送部分である。（９）は位置決めされたＩＣ（
５）の外部電極リード（５，１）〜（５，１６）とコン
タクトプローブ（１２，１）〜（１２，１６）の導通な
得る鳥のＩＣ押上げ具、（１１）はコンタクトプローブ
（１２，１）〜（１２，１６）を保持する保持板、（１
３）はコンタクトプローブ（１２，１）〜（１２，１６
）に挿入された圧縮バネ、（１５）はテスト測定値の印
加、測定値の読取り、良否判定を行う【Ｃテスター （
１４）はコンタクトプローブ（１２，１）〜（１２，１
６）へＩＣテスター（１５）から電流、電圧の印加及び
測定値をテスト装置部分へ送る為のケーブル群である。In the figure, (1) is a plate material punched into a predetermined shape using a metal lead frame, and is composed of parts (la) to (lh). (la) is the first frame, (1b) is the second frame, (lc) is the pitch hole provided in the first frame (la), and (1d) is the pitch hole provided in the second frame (Ib). (IC) is a pad for mounting the IC chip via adhesive, (1f) is a connecting lead that connects the pad (le) with the first frame (1a) and '1PJz frame (lb), (Ig) is I
A connection lead (1h) connects an external lead (1h) that becomes an external electrode of C with a first frame (1a) and a second frame (1b), and (lh) is an external lead that becomes an external electrode of the IC. (2) is the adhesive for bonding the IC chip (3) to the pad (1e), (4) is the wire line connecting each electrode of the IC chip (3) and the external lead (lb), and (5) is the adhesive for bonding the IC chip (3) to the pad (1e). The frame in the state shown in Figure 7 is sealed with resin and cut from the first frame frame (la) and second frame frame (lb), leaving the connecting lead (If) and external lead (th). This is an IC that has been subjected to bending processing. (5,1)~
(5, 16) is I(: (5) external electrode lead, (5,
17) is a sealing resin. (6) to (15) are the component parts of the device that tests the IGs (5) lined up in the frame in the state shown in Figure 9, of which (6) to (9) transport the frame in the state shown in Figure 9. , constitutes a handling device section for positioning, and (11) to (15) constitute a test device section related to electrical measurement for testing the IC (5), and (6)
is the base plate that is the basis of the handling device section, (a,
t) is the first transport rail, (8, 2) is the second transport rail,
(7) is the base plate (6) and the first conveyor rail (a, t)
, a relay plate provided between the second conveyance rails (8, 2),
(8,3) and (8,4) are cover rails. 1st
Transport rail (8,1), second transport rail (8,2)
The cover rails (8, 3) (8, 4) are transport parts that receive and guide the first frame (la) and the second frame (lb). (9) is the positioned IC (
5) is a bird IC push-up tool to ensure continuity between external electrode leads (5,1) to (5,16) and contact probes (12,1) to (12,16); (11) is a contact probe (12); ,1) to (12,16), (1
3) is a contact probe (12,1) to (12,16
), the compression spring (15) is used to apply the test measurement value, read the measurement value, and make a pass/fail judgment [C tester (
14) is a contact probe (12,1) to (12,1
6) This is a group of cables for applying current and voltage and sending measured values from the IC tester (15) to the test equipment section.
次に動作について第１０図に従って説明するが、第６図
の状態のフレームから第９図の状態のフレームに至る図
示しない製造装置の動作については周知の技術である為
割愛する。Next, the operation will be explained according to FIG. 10, but the operation of the manufacturing apparatus (not shown) from the frame in the state of FIG. 6 to the frame in the state of FIG. 9 will be omitted because it is a well-known technique.
まず第９図のリードフレーム（１）がハンドリング装置
部の図示しないハンドリング機構により第１搬送レール
（８，１） 及び第２搬送レール（８，２）の上に乗
せられる。第１搬送レール（８，１）及び第２搬送レー
ル（８，２）はベース板（６）を基礎として中継板（７
）の上に組立てられておりベース板（６）と中継板（７
）と共に金属材料であるステンレス鋼材から出来ている
。そして電気的にはＧＮＤレベルとなっているのが一般
的で第１Ｏ図においてもその様になっている。第１搬送
レール（８，１）及び第２搬送レール（８，２）に乗せ
られたリードフレーム（１）はピッチ穴（ｌｃ）又は（
ｌｄ）に、図示しない定ピツチ搬送機構の送り爪が挿入
しカバーレール（８，３） （８，４）にガイドされ
ながら定ピツチ搬送される。定ピツチ搬送を終えるとＩ
（：（５）の下に設けられたＩＣ押上げ具（９）が図示
しない機構によりＩ（１：（５）の封止樹脂（５，１７
）を押上げる。押上げられたＩ Ｃ（５）はＩＣ押上げ
具（９）の真上に設けられた、保持板（ＩＩ）に配列さ
れたコンタクトプローブ（１２，１）〜（１２，１６）
にＩＣ（５）の外部電極リード（５，１）〜（５，１６
）が接触することになる。接触を完了するとハンドリン
グ装置部からテストスタート信号が発生し、図示しない
信号線でＩＣテスター（１５）へスタート命令が与えら
れる。First, the lead frame (1) shown in FIG. 9 is placed on the first transport rail (8, 1) and the second transport rail (8, 2) by a handling mechanism (not shown) of the handling device section. The first conveyance rail (8,1) and the second conveyance rail (8,2) are based on the base plate (6) and the relay plate (7).
) is assembled on top of the base plate (6) and relay plate (7).
) and is made of stainless steel, which is a metal material. Electrically, it is generally at the GND level, and this is also the case in Fig. 1O. The lead frame (1) placed on the first transport rail (8, 1) and the second transport rail (8, 2) has pitch holes (lc) or (
A feeding claw of a fixed pitch conveyance mechanism (not shown) is inserted into the fixed pitch transport mechanism (8, 4), and the paper is conveyed at a fixed pitch while being guided by the cover rails (8, 3) (8, 4). When the fixed pitch conveyance is finished, I
(: IC push-up tool (9) provided under (5)
) is pushed up. The pushed up IC (5) is connected to the contact probes (12, 1) to (12, 16) arranged on the holding plate (II) provided directly above the IC pushing tool (9).
External electrode leads (5,1) to (5,16) of IC (5)
) will come into contact. When the contact is completed, a test start signal is generated from the handling device section, and a start command is given to the IC tester (15) via a signal line (not shown).
スタート信号を受取ったＩＣテスター（１５）は、予め
入力されているテストプログラムに従い定電圧又は定電
流を発生し、ケーブル群（１４）、コンタクトプローブ
（１２，１）〜（１２，１６）を通じて［（５）の外部
電極リード（５，１）〜（５，１６）に印加し、テスト
測定値を読取り良否を判定する。判定を終えたＩＣテス
ター（１５）から良否信号とテストエンド信号が発生し
、図示しない信号線でハンドリング装置部へ送られる。Upon receiving the start signal, the IC tester (15) generates a constant voltage or constant current according to the pre-input test program, and generates a constant voltage or current through the cable group (14) and contact probes (12,1) to (12,16). The voltage is applied to the external electrode leads (5,1) to (5,16) in (5), and the test measurement values are read to determine the quality. After completing the judgment, the IC tester (15) generates a pass/fail signal and a test end signal, which are sent to the handling device section via a signal line (not shown).
テストエンド信号を受取るとハンドリング装置部はＩＣ
押上げ具（９）を下げ初期位置に戻す。又圧縮バネ（１
３）により圧縮されていたコンタクトプローブ（１２，
１）〜（１２，１６）は圧縮バネ（１３）が伸びること
で初期位置に戻る。そして良否信号データーを記憶して
データーを転送すると同時に次の定ピツチ搬送を行う。When the test end signal is received, the handling device section
Lower the push-up tool (9) and return it to the initial position. Also, compression spring (1
3) The contact probe (12,
1) to (12, 16) return to their initial positions by stretching the compression spring (13). Then, the pass/fail signal data is stored, and at the same time the data is transferred, the next constant pitch conveyance is carried out.
以上の動作を繰返しながらＩＣ（５）のテストが行われ
図示しない連結リード（Ｉｆ）を切離す加工装置へ送ら
れる。While repeating the above operations, the IC (5) is tested and sent to a processing device that disconnects the connecting lead (If) (not shown).
［発明が解決しようとする課題］
従来のリードフレームは以上のように構成されているの
で、リードフレームは金属の板材を使用したものであり
、従ってＩＣチップを搭載するパッドは導電性を有して
いる。又第１Ｏ図に示すようにＩＣのテストを行う際に
おいて第１フレーム枠及び第２フレーム枠はハンドリン
グ装置の第１搬送レール及び第２搬送レールに接触し電
気的にＧＮＤレベルとなっており、この第１フレーム枠
及び第２フレーム枠と連結されている部分も同じくＧＮ
Ｄレベルとなる。この状態でテストの定電圧、定電流の
印加を行うと図示しないＩＣチップの不純物分布（例え
ばＮ層、Ｐ層）の区別によってＩＣチップのパッドとの
接触面が動作機能上＋ｖＣＣレベル（例えば＋４．５ｖ
、＋５ｖすど）トナルＩＣ（例えばＣＭＯＳロジックＩ
Ｃなど）においてパッド、連結リード、及び第１フレー
ム枠及び第２フレーム枠を介してハンドリング装置のＧ
ＮＤと短絡する為、パッドから上記ＧＮＤへ過電流が流
れる不具合がある為、事実上第１Ｏ図に示す状態でのテ
ストは不可能であった。[Problem to be solved by the invention] Since the conventional lead frame is constructed as described above, the lead frame uses a metal plate material, and therefore the pad on which the IC chip is mounted has conductivity. ing. Furthermore, as shown in Figure 1O, when testing the IC, the first frame and the second frame contact the first and second transport rails of the handling device and are electrically at the GND level. The parts connected to the first frame and the second frame are also GN.
It will be D level. When a constant voltage and a constant current are applied for testing in this state, the contact surface with the pad of the IC chip is at +vCC level (for example, +4 .5v
, +5v) tonal IC (e.g. CMOS logic I
G of the handling device via the pad, connecting lead, and the first frame and second frame at
Due to the short circuit with ND, there was a problem in which an overcurrent flowed from the pad to the above-mentioned GND, so it was virtually impossible to test under the condition shown in FIG. 1O.
この対策としてＩＣチップとパッドの接着剤としてエポ
キシ系の絶縁樹脂を用い電気的に短絡を防止することが
試みられているが、接着剤の厚みのコントロールが困難
で上記の様な短絡不良となるＩＣが約ｌＯ〜２０％発生
するという問題点があった。As a countermeasure to this problem, attempts have been made to prevent electrical short circuits by using epoxy-based insulating resin as an adhesive between the IC chip and the pad, but it is difficult to control the thickness of the adhesive, resulting in short circuit failures as described above. There was a problem that IC was generated by about 10 to 20%.
この発明は、上記で延べた問題点を解消するためになさ
れたもので、リードフレームから切り離さない状態のＩ
Ｃテストに於ける短絡不具合をなくすることを目的とし
ている。This invention was made in order to solve the above-mentioned problems.
The purpose is to eliminate short circuit problems in C tests.
［課題を解決するための手段］
この発明に係るリードフレームは、ＩＣチップの搭載さ
れるパッド面とフレーム枠とを接続している連結リード
を改良し、テストをする状態で開放出来る様にしたもの
である。[Means for Solving the Problems] In the lead frame according to the present invention, the connecting lead connecting the pad surface on which an IC chip is mounted and the frame frame is improved so that it can be opened in a test state. It is something.
［作用］
ＩＣチップのパッドとの接着面が電圧レベル＋ ＶＣ（
：であっても、パッドとフレーム枠とを開放する事によ
り、ハンドリング装置のＧＮＤと短絡する事がなく、過
電流も発生することなく、フレームから切り離さない状
態でＩＣテストが可能となる。[Function] The adhesive surface of the IC chip with the pad has a voltage level + VC (
: By opening the pad and the frame frame, there will be no short circuit with the GND of the handling device, no overcurrent will occur, and it is possible to test the IC without separating it from the frame.
［実施例］ 以下、この発明の一実施例を図について説明する。[Example] An embodiment of the present invention will be described below with reference to the drawings.
第１図はリードフレームを示す平面図で、第６図の従来
例におけるフレームに対し第１フレーム枠５第２フレー
ム枠と連結し、パッドとは開放されている補助連結リー
ドを有している。FIG. 1 is a plan view showing a lead frame, which is connected to a first frame frame 5 and a second frame frame in contrast to the conventional frame shown in FIG. 6, and has auxiliary connecting leads that are open from the pad. .
尚、第１図はパッドと第１フレーム枠、第２フレーム枠
と連結する連結リードを従来例に対し各２本ずつとして
いる。第２図は第１図のフレームにＩＣチップを搭載し
、ＩＣチップの各電極とフレームの外部リードをワイヤ
線で配線した状態を示す平面図、第３図は第２図の状態
のフレームに樹脂封止を施した状態を示す平面図、第４
図は第３図の状態のフレームの各リードの切断及び曲げ
加工を施した状態を示す平面図で、第９図の従来例に対
して２本ずつの連結リードが切断され、補助リードで樹
脂封止されたＩＣが第１フレーム枠及び第２フレーム粋
に固定されている。第５図は第４図の状態のフレームの
ｔＣをテストする状態を示すテスターの断面図である。In addition, in FIG. 1, the number of connecting leads connecting the pad, the first frame frame, and the second frame frame are two each compared to the conventional example. Figure 2 is a plan view showing a state in which an IC chip is mounted on the frame shown in Figure 1, and each electrode of the IC chip and the external lead of the frame are wired with wires, and Figure 3 shows the frame in the state shown in Figure 2. A plan view showing a state in which resin sealing is applied, No. 4
The figure is a plan view showing the state in which each lead of the frame in the state shown in Fig. 3 has been cut and bent.In contrast to the conventional example shown in Fig. 9, two connecting leads each have been cut, and the auxiliary leads are made of resin. The sealed IC is fixed to the first frame and the second frame. FIG. 5 is a sectional view of the tester showing a state in which the tC of the frame in the state shown in FIG. 4 is tested.
図において（２）〜（４） 、 （６） 、 （７）
、 （８，１）〜（８，３）。In the figure (2) to (4), (6), (7)
, (8,1) to (8,3).
（９） 、（１１）、（１２，１）〜（１２，１６）
、（１３）〜（１５）は第８図ないし第１Ｏ図の従来例
に示したものと同等であるので説明を省略する。(9), (11), (12,1) to (12,16)
, (13) to (15) are the same as those shown in the conventional example shown in FIGS. 8 to 10, and therefore their explanation will be omitted.
（１０）はリードフレーム、（ｌｏｇ）は第１フレーム
枠、（１０ｂ）は第２フレーム枠、（１０ｃ） 、 （
１０ｄ）はピッチ穴、（１０ｅ）はパッド、（１０ｆ）
、 （１０ｇ）は連結リード、（１０ｈ）は外部リー
ド、（１０ｉ）は補助連結リードである。連結リード（
１０ｆ）は第６図の従来例における連結リード（Ｉｆ）
と同等のものであるが、連結リード（１ｆ）が１本ずつ
であるのに対し連結リード（１０ｆ）は各２本ずつとな
っている。(10) is the lead frame, (log) is the first frame, (10b) is the second frame, (10c), (
10d) is a pitch hole, (10e) is a pad, (10f)
, (10g) is a connecting lead, (10h) is an external lead, and (10i) is an auxiliary connecting lead. Connected lead (
10f) is the connecting lead (If) in the conventional example in Fig. 6.
However, while there is one connecting lead (1f), there are two connecting leads (10f) each.
補助連結リード（１０ｉ）はＩＣチップ（３）の接着面
となるパッド（ｆｏｅ）とは開放されており、第１フレ
ーム枠（１０ａ）、第２フレーム枠（１０ｂ）と連結さ
れている。（５０）はリードフレーム（１０）を使用し
たＩＣで（５０，１）〜（５０，１６）は外部電極リー
ド、（５０，１７）は封止樹脂である。The auxiliary connection lead (10i) is open to the pad (foe) which is the adhesive surface of the IC chip (3), and is connected to the first frame (10a) and the second frame (10b). (50) is an IC using a lead frame (10), (50,1) to (50,16) are external electrode leads, and (50,17) is a sealing resin.
次に動作について説明する。Next, the operation will be explained.
第１図から第４図に至る過程は、第６図から第９図に至
る従来例と同じく周知の技術、製造装置（図示せず）に
よるもので説明の重複を避ける。しかし連結リード（］
Ｏｆ）は第４図の段階において切断するので、第９図の
従来例において第１フレーム枠（１ａ）と第２フレーム
枠（２ａ）はそれぞれ連結リード（Ｉｆ）を経てパッド
（ｌｅ）と導通しているのに対し、第４図においては第
１フレーム枠（１０ａ）と第２フレーム枠（１０ｂ）は
それぞれ補助連結リード（１０ｉ）によって封止樹脂（
５０，１７）に嵌入しているがパッド（１ｅ）とは導通
していない。The process from FIG. 1 to FIG. 4 is performed using well-known technology and manufacturing equipment (not shown), as in the conventional example shown from FIG. 6 to FIG. 9, so that the explanation will not be repeated. However, the connected lead (]
Of) is cut at the stage shown in FIG. 4, so in the conventional example shown in FIG. 9, the first frame (1a) and the second frame (2a) are electrically connected to the pad (le) through the connection lead (If). On the other hand, in FIG. 4, the first frame (10a) and the second frame (10b) are each sealed with a sealing resin (10i) by an auxiliary connection lead (10i).
50, 17), but is not electrically connected to the pad (1e).
［発明の効果］
以上説明したように、ＩＣチップの接着面のパッドと、
第１フレーム枠及び第２フレーム枠とを接続している従
来の連結リードが切断されても補助連結リードによりＩ
Ｃチップをフレームに固定でき、かつ、フレームとパッ
ドとは導通がなく開放されているのでＩＣチップを搭載
するパッド（接着面）が＋ｖＣＣレベルであっても、ハ
ンドリング装置のＧＮＤと短絡することなく、フレーム
から切り離さない状態でのＩＣのテストが可能となる効
果がある。[Effect of the invention] As explained above, the pad on the adhesive surface of the IC chip,
Even if the conventional connecting lead connecting the first frame and the second frame is cut, the auxiliary connecting lead
The C chip can be fixed to the frame, and since there is no conduction between the frame and the pads and they are open, even if the pad (adhesive surface) on which the IC chip is mounted is at +vCC level, there will be no short circuit with the GND of the handling device. This has the effect of making it possible to test the IC without separating it from the frame.
第１図はこの発明の一実施例によるリードフレームを示
す平面図、第２図は第１図のフレームにＩＣチップを搭
載し、ＩＣチップ各電極とフレームの外部リードをワイ
ヤ線で配線した状態を示す平面図、第３図は第２図の状
態のフレームに樹脂封止を施した状態を示す平面図、第
４図は第３図の状態のフレームに各リードの切断及び曲
げ加工を施した状態を示す平面図、第５図は第４図の状
態のフレームのＩＣをテストする状態を示すテスター断
面図、第６図は従来のリードフレームを示す平面図、第
７図は第６図のフレームにＩＣチップを搭載し、ＩＣチ
ップの各電極とフレームの外部リードと配線した状態を
示す平面図、第８図は第７図の状態のフレームに樹脂封
止を施した状態を示す平面図、第９図は第８図の状態の
フレームに各リードの切断及び曲げ加工を施した状態を
示す平面図、第１Ｏ図は第９図の状態のフレームのＩＣ
をテストする状態を示すテスターの断面図である。図に
おいて（２）は接着剤、（３）はＩＣチップ、（４）は
ワイヤ線、（６）はベース板、（７）は中継板、（８，
１）は第１搬送レール、（８，２）は第２搬送レール、
（８，３） 、 （８，４）はカバーレール、（９）は
ＩＣ押上げ具、（１０）はリードフレーム、（１０ａ）
は第１フレーム枠、（１０ｂ）は第２フレーム枠、（１
０ｃ） 、 （１０ｄ）はピッチ穴、（１０ｅ）はパッ
ド、（ｌｏｆ） 、 （１０ｇ）は連結リード、（１０
ｈ）は外部リード、（１０ｉ）は補助連結リード、（１
１）は保持板、（１２，１〜１２．１６）はコンタクト
プローブ、（１３）は圧縮バネ、（１４）はケーブル群
、（１５）はＩＣテスター （５０）はＩＣ１（５０，
１）〜（５０，１６）は外部電極リードである。
なお、図中、同一符号は同一、又は相当部分を示す。Fig. 1 is a plan view showing a lead frame according to an embodiment of the present invention, and Fig. 2 shows a state in which an IC chip is mounted on the frame shown in Fig. 1, and each electrode of the IC chip and the external lead of the frame are wired with wires. 3 is a plan view showing the frame in the state shown in FIG. 2 with resin sealing, and FIG. 4 is a plan view showing the frame in the state shown in FIG. 3 after cutting and bending each lead. FIG. 5 is a sectional view of the tester showing the tester testing the IC of the frame in the state shown in FIG. 4, FIG. 6 is a plan view showing the conventional lead frame, and FIG. Fig. 8 is a plan view showing a state in which an IC chip is mounted on the frame and wired to each electrode of the IC chip and the external leads of the frame, and Fig. 8 is a plan view showing a state in which the frame shown in Fig. 7 is sealed with resin. Figure 9 is a plan view showing the frame shown in Figure 8 after cutting and bending each lead, and Figure 1O is the IC of the frame shown in Figure 9.
FIG. 3 is a cross-sectional view of the tester showing a state in which it is tested. In the figure, (2) is the adhesive, (3) is the IC chip, (4) is the wire line, (6) is the base plate, (7) is the relay plate, (8,
1) is the first transport rail, (8, 2) is the second transport rail,
(8,3), (8,4) is the cover rail, (9) is the IC pusher, (10) is the lead frame, (10a)
is the first frame, (10b) is the second frame, (1
0c), (10d) are pitch holes, (10e) are pads, (lof), (10g) are connecting leads, (10
h) is the external lead, (10i) is the auxiliary connection lead, (1
1) is a holding plate, (12,1 to 12.16) is a contact probe, (13) is a compression spring, (14) is a cable group, (15) is an IC tester, (50) is an IC1 (50,
1) to (50, 16) are external electrode leads. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
半導体チップの接着面と該接着面とほぼ水平で平行な上
下にフレーム枠を有したリードフレームであり、該接着
面と上記フレーム枠とは接続されたフレームであって、
上記フレーム枠から該接着面に水平に伸び該接着面とは
接触せず樹脂封止後該樹脂に埋まる突起状のリードを有
したことを特徴とするリードフレーム。In metal rad frames on which semiconductor chips are mounted,
A lead frame has a bonding surface of a semiconductor chip and a frame frame above and below which is substantially horizontal and parallel to the bonding surface, and the bonding surface and the frame frame are connected frames,
A lead frame characterized in that it has a protruding lead that extends horizontally from the frame frame to the adhesive surface and does not come into contact with the adhesive surface but is buried in the resin after resin sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1324529A JPH03184356A (en) | 1989-12-13 | 1989-12-13 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1324529A JPH03184356A (en) | 1989-12-13 | 1989-12-13 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03184356A true JPH03184356A (en) | 1991-08-12 |
Family
ID=18166822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1324529A Pending JPH03184356A (en) | 1989-12-13 | 1989-12-13 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03184356A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0550013A2 (en) * | 1991-12-27 | 1993-07-07 | Fujitsu Limited | Semiconductor device and method of producing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6119157A (en) * | 1984-07-06 | 1986-01-28 | Nec Corp | Lead frame and semiconductor device using same |
-
1989
- 1989-12-13 JP JP1324529A patent/JPH03184356A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6119157A (en) * | 1984-07-06 | 1986-01-28 | Nec Corp | Lead frame and semiconductor device using same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0550013A2 (en) * | 1991-12-27 | 1993-07-07 | Fujitsu Limited | Semiconductor device and method of producing the same |
| EP0550013B1 (en) * | 1991-12-27 | 2000-07-26 | Fujitsu Limited | Semiconductor device and method of producing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6247629B1 (en) | Wire bond monitoring system for layered packages | |
| KR100681772B1 (en) | Method and apparatus for testing semiconductor devices | |
| US6429675B2 (en) | Structure and method for probing wiring bond pads | |
| EP0622733B1 (en) | Method and device for testing integrated power devices | |
| US5656941A (en) | Tab tape-based bare chip test and burn-in carrier | |
| US5585281A (en) | Process and apparatus for forming and testing semiconductor package leads | |
| JPH03184356A (en) | Lead frame | |
| US5940680A (en) | Method for manufacturing known good die array having solder bumps | |
| JP2634286B2 (en) | Handler device for testing electrical characteristics of semiconductor devices | |
| JP3958078B2 (en) | Tape-like IC module and IC module manufacturing method | |
| JPH0353536A (en) | Bonding method of conductor | |
| KR0141453B1 (en) | Manufacturing method of known-good die | |
| EP0632493A1 (en) | Semiconductor device with twice-bonded wire and method for manufacturing | |
| JP2007115282A (en) | Ic module for ic card used as both contact/non-contact types | |
| JPH0789126B2 (en) | Method for testing electrical characteristics of hybrid integrated circuit board | |
| JPH03116962A (en) | Lead frame | |
| JP3208095B2 (en) | Inspection equipment for semiconductor devices | |
| JPH0980116A (en) | Socket for semiconductor chip | |
| US6720574B2 (en) | Method of testing a semiconductor chip | |
| JP3042408B2 (en) | Semiconductor device measuring method and measuring jig | |
| JPH05206233A (en) | Aging equipment for semiconductor | |
| JP2795267B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP2900572B2 (en) | Film carrier type semiconductor device and its sorting method | |
| JP3163903B2 (en) | Inspection parts for multi-chip module substrates | |
| JP2000241446A (en) | Wire probe device for substrate and ic tester |