JPH03173166A - Heat-dissipating substrate for semiconductor - Google Patents
Heat-dissipating substrate for semiconductorInfo
- Publication number
- JPH03173166A JPH03173166A JP1311948A JP31194889A JPH03173166A JP H03173166 A JPH03173166 A JP H03173166A JP 1311948 A JP1311948 A JP 1311948A JP 31194889 A JP31194889 A JP 31194889A JP H03173166 A JPH03173166 A JP H03173166A
- Authority
- JP
- Japan
- Prior art keywords
- powder sintered
- substrate
- heat
- heat dissipation
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000843 powder Substances 0.000 claims abstract description 33
- 239000010949 copper Substances 0.000 claims abstract description 29
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims abstract description 11
- 229910052802 copper Inorganic materials 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 3
- 230000017525 heat dissipation Effects 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 6
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 5
- 229910052742 iron Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高い熱伝導率と、高い接合信頼性を有する半
導体用放熱基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heat dissipating substrate for semiconductors having high thermal conductivity and high bonding reliability.
従来１例えば第３図に示すごとく、半導体装置９は、制
御″ｎ回路部９５と、そのボンディングパント９５２に
ボンディングワイヤー９７を介して接続した半導体チッ
プ９３と、該半導体チップ９３を搭載した放熱基板９１
とよりなる。Conventional 1 For example, as shown in FIG. 3, a semiconductor device 9 includes a control "n circuit section 95, a semiconductor chip 93 connected to its bonding punt 952 via a bonding wire 97, and a heat dissipation board on which the semiconductor chip 93 is mounted. 91
It becomes more.
該放熱基板９１は、アルミナ基板（アルミナセラミック
ス基板）９０上に搭載し、該アルミナ基板９０と放熱基
板９１とシリコン半導体チップ９３とは互いに半田等に
より接合する。The heat dissipation substrate 91 is mounted on an alumina substrate (alumina ceramics substrate) 90, and the alumina substrate 90, heat dissipation substrate 91, and silicon semiconductor chip 93 are bonded to each other by soldering or the like.
また、制御回路部９５は制御回路付アルミナ基板９５１
と、その上に配設したボンディングパラと９５２及び電
子回路部９５３とよりなる。該電子回路部９５３は、コ
ンデンサー、抵抗体等よりなる。In addition, the control circuit section 95 includes an alumina substrate 951 with a control circuit.
, a bonding plate 952 disposed thereon, and an electronic circuit section 953. The electronic circuit section 953 includes a capacitor, a resistor, and the like.
また、上記アルミナ基板９０及び制御回路付アルミナ基
板９５１は、アルミニウム（Ａｆｆｉ）、１ｌｉｉｌ（
Ｃｕ）、鉄（Ｆｅ）等の放熱ケース９９に接合する。そ
して、上記半導体チップ９３等は同図に示すごとく、放
熱ケース９９内に収納し、封止樹脂９日により封止する
。The alumina substrate 90 and the alumina substrate with control circuit 951 are made of aluminum (Affi), 1liil (
It is bonded to a heat dissipation case 99 made of Cu), iron (Fe), or the like. Then, as shown in the figure, the semiconductor chip 93 and the like are housed in a heat dissipation case 99 and sealed with a sealing resin.
上記放熱基板９】は、半導体チップ９３が電気的作動を
行う際に発生する熱を、アルミナ基板９０、放熱ケース
９９を介して外部へ放散させるために設けである。The heat dissipation board 9] is provided to dissipate heat generated when the semiconductor chip 93 performs electrical operation to the outside via the alumina substrate 90 and the heat dissipation case 99.
そして、従来上記放熱基板９１としては３ シリコン半
導体チップ９３の発熱量が大きいため、下地との接合の
信頼性を高めるために、モリブデン（Ｍｏ）が用いられ
ている。即ち、ＭｏＯ熱膨張係数は、半導体チップのシ
リコンとアルミナＭＵｉとの中間に位置し、熱膨張係数
が小さく、接合上の信頼性が高い、特に、近年のハイパ
ワー化の動きより、Ｍｏを使用する場合が多い。１亥Ｍ
Ｏ放熱基板は、まず湿式法によりＭｏ粉末を作製する。Conventionally, molybdenum (Mo) has been used as the heat dissipation substrate 91 in order to improve the reliability of bonding with the base because the amount of heat generated by the 3 silicon semiconductor chip 93 is large. In other words, MoO has a thermal expansion coefficient that is between that of silicon and alumina MUi in semiconductor chips, and has a small thermal expansion coefficient and high reliability in bonding. Often. 1 yen M
For the O heat dissipation substrate, first, Mo powder is produced by a wet method.
そして、これを成形、高温焼成、圧延した後、板状に打
抜くことにより製造する。This is then molded, fired at a high temperature, rolled, and then punched into a plate shape.
また、Ｍｏ製の放熱基板は、その製造費用が高く、コス
ト高である。その理由としては、Ｍｏ自体が高価である
こと、Ｍｏ粉末の製造がコスト高であることなどによる
。Moreover, the heat dissipation board made of Mo is expensive to manufacture. This is because Mo itself is expensive, and the production of Mo powder is expensive.
一方、Ｆｅ又はＣｕの放熱基板を用いることが考えられ
るが、半導体チップのシリコンとアルミナ基板との熱膨
張係数に大きな差異がある。そのため、使用中にＦｅ又
はＣｕの放熱基板と半導体チップ又はアルミナ基板との
間が剥離するおそれがある。そのため、かかる放熱基板
は、パワーが小さく発熱量の小さい半導体チップに、そ
の使用が限られる。On the other hand, it is conceivable to use a heat dissipation substrate made of Fe or Cu, but there is a large difference in the coefficient of thermal expansion between the silicon of the semiconductor chip and the alumina substrate. Therefore, there is a risk that the Fe or Cu heat dissipation substrate and the semiconductor chip or alumina substrate may peel off during use. Therefore, the use of such a heat dissipation board is limited to semiconductor chips with low power and low heat generation.
Ｃ解決しようとする課題〕
上記のごと＜、Ｍｏは、放熱基板としてその接合信頼性
に優れているが、そのもの自体が非常に高価な金属であ
り、コスト的にはＦｅやＣｕとは比較できない程高くな
る。C Problems to be Solved] As mentioned above, Mo has excellent bonding reliability as a heat dissipation substrate, but it is itself a very expensive metal and cannot be compared with Fe or Cu in terms of cost. moderately high.
本発明はかかる問題点に鑑み、熱伝導率に優れかつ半導
体チンプとアルミナ基板との間の接合信頼性に優れ、か
つ安価な半導体用放熱基板を提供しようとするものであ
る。In view of these problems, the present invention aims to provide a heat dissipating substrate for semiconductors that has excellent thermal conductivity, excellent bonding reliability between a semiconductor chip and an alumina substrate, and is inexpensive.
〔課題の解決手段］
本発明は、半導体チップと、該半導体チップを搭載する
アルミナ基板と１両者の間に介設した放熱基板とよりな
る半導体装置において、上記放熱基板は、鉄・ニッケル
合金の粉末焼結体と、該粉末焼結体の空隙内に含浸させ
た銅とよりなることを特徴とする半導体用放熱基板にあ
る。[Means for Solving the Problems] The present invention provides a semiconductor device comprising a semiconductor chip, an alumina substrate on which the semiconductor chip is mounted, and a heat dissipation substrate interposed between the two, wherein the heat dissipation substrate is made of an iron-nickel alloy. A heat dissipating substrate for a semiconductor, comprising a powder sintered body and copper impregnated into the voids of the powder sintered body.
本発明において粉末焼結体は、鉄（Ｆｅ）とニッケル（
Ｎｉ）との合金粉末を高温で焼結したもので、その内部
には多数の空隙を有する０本発明の放熱基板は、この鉄
・ニッケル合金の粉末焼結体内にＣｕを含浸させてなる
ものである。In the present invention, the powder sintered body contains iron (Fe) and nickel (
The heat dissipating substrate of the present invention is made by impregnating Cu into the powder sintered body of this iron-nickel alloy. It is.
上記鉄・ニッケル合金としては、特にＦｅ−３６Ｎｉ
（アンバー）を用いることが好ましい。As the above-mentioned iron-nickel alloy, especially Fe-36Ni
(Amber) is preferably used.
また、上記粉末焼結体と含ｐＪｃｕとの割合は重量比で
は２両者の合計量中にＣｕが１２〜３６ｗｔ％存在して
いることが好ましい、１２％未満では、熱膨張係数がシ
リコン（Ｓｉ）のそれよりも小さくなる。一方、３６％
を越えるとアルミナ基板の熱膨張係数を超え、初期の目
的を達成し難い（第２図参照）。In addition, the ratio of the powder sintered body to the pJcu-containing pJcu is preferably such that 12 to 36 wt% of Cu is present in the total amount of both.If the ratio is less than 12%, the thermal expansion coefficient of silicon (Si) ) is smaller than that of On the other hand, 36%
If it exceeds the thermal expansion coefficient of the alumina substrate, it will be difficult to achieve the initial objective (see Figure 2).
また、粉末焼結体内へのＣｕの含浸方法としては１例え
ば上記粉末焼結体を溶融Ｃｕ浴中へ、減圧下に浸漬する
方法がある。また、粉末焼結体上にＣｕを載置して、こ
れらをＣｕの融点以上に加熱して、溶融鋼を粉末焼結体
内に吸収させる方法など１通常の冶金法で行われる方法
で製造が可能である。Further, as a method for impregnating Cu into the powder sintered body, there is, for example, a method of immersing the powdered sintered body in a molten Cu bath under reduced pressure. In addition, manufacturing can be carried out by a method that is carried out in a normal metallurgical method, such as placing Cu on a powder sintered body, heating it above the melting point of Cu, and absorbing molten steel into the powder sintered body. It is possible.
また、上記放熱基板への半導体チップの搭載は。Also, mounting a semiconductor chip on the heat dissipation board mentioned above.
はんだ、金属ろうなどによる接合が一般的である。Bonding using solder, metal brazing, etc. is common.
本発明においては、放熱基板のマトリクスとして鉄・ニ
ッケル合金の粉末焼結体を用いている。In the present invention, an iron-nickel alloy powder sintered body is used as the matrix of the heat dissipation substrate.
そして、該鉄・ニッケル合金にＣｕを含浸させた放熱基
板は、熱膨張係数が半導体チップのシリコンとアルミナ
基板との中間を値を示し、また上記Ｃｕは高い熱伝導率
を有する。The heat dissipating substrate made of the iron-nickel alloy impregnated with Cu exhibits a thermal expansion coefficient intermediate between that of the silicon of the semiconductor chip and the alumina substrate, and the Cu has high thermal conductivity.
そのため、前記従来のごとく、上記熱膨張係数の差に基
づく、半導体チップ、放熱基板、アルミナ基板の各両者
間に剥離を生ずることがない。それ故、半導体チップと
アルミナ基板との間の接合信頼性が高い。Therefore, as in the prior art, separation between the semiconductor chip, the heat dissipation substrate, and the alumina substrate due to the difference in the thermal expansion coefficients does not occur. Therefore, the reliability of the bond between the semiconductor chip and the alumina substrate is high.
また、上記放熱基板は優れた放熱性を発揮する。Moreover, the heat dissipation substrate described above exhibits excellent heat dissipation.
また、鉄・ニッケル合金の粉末焼結体及び含浸ＣＵは共
に安価な材料であり、Ｍｏのごとき高価な放熱基板に代
わって、安価な放熱基板を提供する。Further, both the iron-nickel alloy powder sintered body and the impregnated CU are inexpensive materials, and provide an inexpensive heat dissipation substrate in place of an expensive heat dissipation substrate such as Mo.
したがって９本発明によれば、熱伝導率に優れかつ半導
体チップとアルミナ基板との間の接合信軸性に優れ、か
つ安価な半導体用放熱基板を提供することができる。Therefore, according to the present invention, it is possible to provide a heat dissipation substrate for a semiconductor that has excellent thermal conductivity, excellent joint axial stability between a semiconductor chip and an alumina substrate, and is inexpensive.
［実施例］
第１実施例
本発明の実施例にかかる放熱基板につき、第１図により
説明する。[Embodiments] First Embodiment A heat dissipation board according to an embodiment of the present invention will be explained with reference to FIG.
該放熱基板は、粉末焼結体１の空隙ｌｌ内にＣｕ２を含
浸させてなる。該粉末焼結体ｌは、鉄・ニッケル合金の
粉末１０を混合し、高温に加熱し粉末同志を互いに焼結
させることにより得たものである。The heat dissipation substrate is made by impregnating Cu2 into the voids 11 of the powder sintered body 1. The powder sintered body 1 is obtained by mixing iron-nickel alloy powder 10 and heating the mixture to a high temperature to sinter the powders together.
上記放熱基板は５上記粉末焼結体１の上にＣｕ塊を載置
し、これらを減圧下においてＣｕの融点以上に加熱し、
溶融Ｃｕを粉末焼結体ｌの空隙１１内に吸収させること
により得た。The heat dissipation substrate 5 places Cu lumps on the powder sintered body 1 and heats them under reduced pressure to a temperature higher than the melting point of Cu,
It was obtained by absorbing molten Cu into the voids 11 of the powder sintered body 1.
上記放熱基板には、はんだ付けによりシリコン半導体チ
ップを搭載する（図示略）。A silicon semiconductor chip is mounted on the heat dissipation board by soldering (not shown).
第２実施例
鉄・ニッケル合金としてのアンバー合金（Ｆｅ３６％Ｎ
ｉ合金）の粉末を用い３ これを水及び有機糊料と混合
し、板状に成形し、これらを１１００°Ｃに加熱して粉
末焼結体とした。上記粉末は。Second Example Amber alloy as iron-nickel alloy (Fe36%N
Powder of Alloy i) was mixed with water and organic glue, formed into a plate shape, and heated to 1100°C to form a powder sintered body. The above powder is.
平均粒径５０μｍのものを用いた。また、得られた粉末
焼結体は、空隙率約２５％であった。The particles with an average particle size of 50 μm were used. Further, the obtained powder sintered body had a porosity of about 25%.
次に、上記粉末焼結体の上に、Ｃｕ板を載置し。Next, a Cu plate was placed on the powder sintered body.
これらを減圧下に約１１２０°Ｃに加熱した。これによ
り、Ｃｕを含浸してなる粉末焼結体を製造した。These were heated to about 1120°C under reduced pressure. In this way, a powder sintered body impregnated with Cu was manufactured.
このようにして得た放熱基板は、熱伝導率が１０８ｗ／
ｍ−に、熱膨張係数が５．７Ｘ１０−６／°Ｃであった
。The heat dissipation board thus obtained has a thermal conductivity of 108w/
m-, the coefficient of thermal expansion was 5.7X10-6/°C.
第３実施例
上記第２実施例に準じて、粉末焼結体と含浸ＣＵとの割
合が異なる種々の放熱基板を製造した。Third Example According to the second example above, various heat dissipating substrates having different ratios of powder sintered body and impregnated CU were manufactured.
そして、これら放熱基板について、熱伝導率と熱膨張係
数を測定した。Then, the thermal conductivity and thermal expansion coefficient of these heat dissipating substrates were measured.
その結果を、第２図にＣｕの重量比に関して示した。The results are shown in FIG. 2 in terms of the weight ratio of Cu.
同図より、熱伝導率（実線）及び熱膨張係数（点線）は
、共にＣｕ含浸量が多くなるに従って大きくなることが
分かる。From the figure, it can be seen that both the thermal conductivity (solid line) and the thermal expansion coefficient (dotted line) increase as the amount of Cu impregnated increases.
一方、半導体チップのシリコンは、熱膨張係数が約３．
５ Ｘ １０−’／’Ｃである。また、アルミナ基板
の熱膨張係数は約７． ３ Ｘ １０−’／’Ｃである
。On the other hand, silicon in semiconductor chips has a coefficient of thermal expansion of approximately 3.
5 x 10-'/'C. Also, the thermal expansion coefficient of the alumina substrate is approximately 7. 3 x 10-'/'C.
それ故１両者の中間の熱膨張係数を得るにはＣｕ星は１
重量比で１２〜３６％とすることが好ましいことが分か
る。また、Ｃｕ含浸量がこの範囲内にあるときには、Ｍ
ｏとほぼ同等の熱伝導率を達成することもできる。Therefore, to obtain a thermal expansion coefficient intermediate between the two, the Cu star must be 1
It can be seen that the weight ratio is preferably 12 to 36%. Furthermore, when the Cu impregnation amount is within this range, M
It is also possible to achieve a thermal conductivity approximately equal to o.
第１図は第１実施例の放熱基板の断面説明図。
第２図は第３実施例におけるＣｕ含浸量と熱伝導率及び
熱膨張係数との関係線回、第３図は従来の半導体装置の
説明図である。
９１、、、放熱基板
９３、、、半導体チップ。
出 願 人
愛知製鋼株式会社FIG. 1 is an explanatory cross-sectional view of a heat dissipation board of the first embodiment. FIG. 2 is a diagram showing the relationship between the amount of Cu impregnated and the thermal conductivity and coefficient of thermal expansion in the third embodiment, and FIG. 3 is an explanatory diagram of a conventional semiconductor device. 91, . . . Heat dissipation board 93, . . . Semiconductor chip. Applicant: Aichi Steel Co., Ltd.
Claims (1)
板と、両者の間に介設した放熱基板とよりなる半導体装
置において、 上記放熱基板は、鉄・ニッケル合金の粉末焼結体と、該
粉末焼結体の空隙内に含浸させた銅とよりなることを特
徴とする半導体用放熱基板。[Claims] A semiconductor device comprising a semiconductor chip, an alumina substrate on which the semiconductor chip is mounted, and a heat dissipation substrate interposed between the two, wherein the heat dissipation substrate is a powder sintered body of an iron-nickel alloy. and copper impregnated into the voids of the powder sintered body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1311948A JPH03173166A (en) | 1989-11-30 | 1989-11-30 | Heat-dissipating substrate for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1311948A JPH03173166A (en) | 1989-11-30 | 1989-11-30 | Heat-dissipating substrate for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03173166A true JPH03173166A (en) | 1991-07-26 |
Family
ID=18023365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1311948A Pending JPH03173166A (en) | 1989-11-30 | 1989-11-30 | Heat-dissipating substrate for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03173166A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100319786B1 (en) * | 1997-05-13 | 2002-02-19 | 셈보쿠야 아키오 | Thin plate member for semiconductor package and manufacturing method therefor |
| EP1296372A2 (en) * | 2001-09-21 | 2003-03-26 | Kabushiki Kaisha Toyota Jidoshokki | Heat dissipating material and manufacturing method thereof |
-
1989
- 1989-11-30 JP JP1311948A patent/JPH03173166A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100319786B1 (en) * | 1997-05-13 | 2002-02-19 | 셈보쿠야 아키오 | Thin plate member for semiconductor package and manufacturing method therefor |
| EP1296372A2 (en) * | 2001-09-21 | 2003-03-26 | Kabushiki Kaisha Toyota Jidoshokki | Heat dissipating material and manufacturing method thereof |
| EP1296372A3 (en) * | 2001-09-21 | 2006-07-26 | Kabushiki Kaisha Toyota Jidoshokki | Heat dissipating material and manufacturing method thereof |
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