JPH03218030A - Semiconductor integrated circuit device and preform bonding material used in the same - Google Patents
Semiconductor integrated circuit device and preform bonding material used in the sameInfo
- Publication number
- JPH03218030A JPH03218030A JP1331690A JP1331690A JPH03218030A JP H03218030 A JPH03218030 A JP H03218030A JP 1331690 A JP1331690 A JP 1331690A JP 1331690 A JP1331690 A JP 1331690A JP H03218030 A JPH03218030 A JP H03218030A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- integrated circuit
- semiconductor integrated
- circuit device
- thermally conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 239000000463 material Substances 0.000 title claims abstract description 63
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- 238000009418 renovation Methods 0.000 claims 1
- 238000005219 brazing Methods 0.000 abstract description 29
- 238000000034 method Methods 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 28
- 230000017525 heat dissipation Effects 0.000 description 17
- 239000000945 filler Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 230000005496 eutectics Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910015365 Au—Si Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000001308 synthesis method Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体集積回路装置の製造技術に関し、特に
半導体集積回路装置のダイボンディング技術において、
ダイボンディング部の高熱伝導化および高精度化構造が
可能とされ、放熱効率の向上を図ることができる半導体
集積回路装置およびそれに用いられるプリフォーム接合
材に適用して有効な技術に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and particularly to a die bonding technology for semiconductor integrated circuit devices.
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device and a preform bonding material used therein, which enables a die bonding part to have a high thermal conductivity and a highly precise structure, and which can improve heat dissipation efficiency.
口従来の技術］
近年、半導体集積回路装置の高密度化および高集積化に
伴い、消費電力密度の急上昇がもたらされ、電子計算機
などの熱問題は厳しい一面を持つようになってきている
。このような状況の中で、半導体チップ背面からの冷却
技術が重要となりつつあり、ダイボンディング技術にお
ける熱経路での熱抵抗低減が重要課題となっている。[Background Art] In recent years, as semiconductor integrated circuit devices have become denser and more highly integrated, the density of power consumption has increased rapidly, and heat problems in electronic computers and the like have become more severe. Under these circumstances, cooling technology from the back side of semiconductor chips is becoming important, and reducing thermal resistance in the thermal path in die bonding technology has become an important issue.
また、従来のダイボンディング技術としては、たとえば
株式会社電気書院、１９８７年発行「Ｌｓｒ設計製作技
術ＪＰ１１８〜Ｐ１１９、または社団法人電子通信学会
、昭和５９年１１月３０日発行「ＬＳＩハンドブック．
Ｐ４０６〜Ｐ４０８などの文献に記載されるように、半
導体チップをダイボンディング基板に接着する接着方法
としては、共晶合合法、はんだ接着法および樹脂接着法
が用いられている。Conventional die bonding techniques include, for example, "Lsr Design and Manufacturing Technology JP118-P119, published by Denki Shoin Co., Ltd., 1987," or "LSI Handbook," published by the Institute of Electronics and Communication Engineers, November 30, 1987.
As described in documents such as P406 to P408, the eutectic synthesis method, the solder bonding method, and the resin bonding method are used as bonding methods for bonding a semiconductor chip to a die bonding substrate.
たとえば、共晶合合法は、Ａｕ−Ｓｉ共晶合金の融点が
３７０℃と比較的低いことから広く用いられている。こ
の共晶合金法は、ダイボンディング時の酸化を防止する
ため、Ｎ２またはＮ２＋Ｈ雰囲気中において４００℃前
後に加熱しながら、Ａｕメッキされたグイパッドに半導
体チップ背面を押し付け、Ａｕ−Ｓｉ共晶反応を行わせ
て接合するものである。この時、共晶反応を起こし易く
するために、接合部分に振動を与える方法がとられてい
る。また、この合金層をさらに良好なものにするため、
半導体チップの背面にＡｕを蒸着したり、またはＡｕ箔
を挟む方法がとられている。For example, the eutectic synthesis method is widely used because the melting point of Au-Si eutectic alloy is relatively low at 370°C. In this eutectic alloy method, in order to prevent oxidation during die bonding, the back surface of a semiconductor chip is pressed against an Au-plated Goo pad while heating to around 400°C in an N2 or N2+H atmosphere to initiate an Au-Si eutectic reaction. This is done to join. At this time, in order to facilitate the eutectic reaction, a method of applying vibration to the bonded portion is used. In addition, in order to make this alloy layer even better,
Methods of depositing Au on the back surface of the semiconductor chip or sandwiching Au foil have been used.
［発明が解決しようとする課題］
ところが、前記のような従来技術においては、半導体チ
ップ背面とダイボンディング基板とを固着するろう材層
厚、およびろう材層の高熱伝導化の点について配慮がさ
れておらず、半導体集積回路装置の放熱性の均一化が図
れないという欠点がある。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, consideration is not given to the thickness of the brazing material layer for fixing the back surface of the semiconductor chip and the die bonding substrate, and to the high thermal conductivity of the brazing material layer. Therefore, there is a drawback that the heat dissipation of the semiconductor integrated circuit device cannot be made uniform.
従って、従来のダイボンディング技術においては、放熱
性の不均一および高集積化に起因する近年の半導体集積
回路装置における消費電力密度の増大に対応できなくな
るという問題がある。Therefore, the conventional die bonding technology has the problem that it cannot cope with the increase in power consumption density in recent semiconductor integrated circuit devices due to non-uniform heat dissipation and high integration.
そこで、本発明の目的は、ダイボンディング部の接合材
厚が均一化され、かつ高熱伝導接合材層の形成によって
放熱効率の向上が可能とされる半導体集積回路装置およ
びそれに用いられるプリフォーム接合材を提供すること
にある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device and a preform bonding material used therein, in which the thickness of the bonding material in the die bonding part is made uniform and heat dissipation efficiency can be improved by forming a highly thermally conductive bonding material layer. Our goal is to provide the following.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［課題を解決するための手段］
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.
すなわち、本発明の半導体集積回路装置は、半導体チッ
プが接合材を介してダイボンディング基板に実装される
半導体集積回路装置であって、前記接合材中に高熱伝導
材料から形成される複数の熱伝導材が含有されるもので
ある。That is, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which a semiconductor chip is mounted on a die bonding substrate via a bonding material, and the bonding material includes a plurality of thermally conductive layers made of a highly thermally conductive material. It contains wood.
また、前記熱伝導材を、直径が均一な球形状または同心
円リング状、あるいは高さが均一な多面体形状または多
角形リング状に形成したり、金属、ダイヤモンド、セラ
ミックまたはこれらの複合体から形成したものである。The thermally conductive material may be formed into a spherical or concentric ring shape with a uniform diameter, a polyhedral shape or a polygonal ring shape with a uniform height, or formed from metal, diamond, ceramic, or a composite thereof. It is something.
さらに、前記熱伝導材の直径または高さを、ダイボンデ
ィング後の接合材厚にほぼ等しくなるように形成したも
のである。Furthermore, the diameter or height of the thermally conductive material is formed to be approximately equal to the thickness of the bonding material after die bonding.
また、本発明の半導体集積回路装置に用いられるプリフ
ォーム接合材は、前記熱伝導材が、前記半導体チップと
前記ダイボンディング基板との接合面に均一に含有され
て形成されるものである。Further, the preform bonding material used in the semiconductor integrated circuit device of the present invention is formed such that the thermally conductive material is uniformly contained in the bonding surface of the semiconductor chip and the die bonding substrate.
［作用］
前記した半導体集積回路装置によれば、半導体チップが
グイポンディング基板に接合される接合材中に高熱伝導
材料から形成される複数の熱伝導材が含有されることに
より、高熱伝導化が可能とされる接合材層が形成され、
半導体集積回路装置の放熱効率の向上を図ることができ
る。[Function] According to the semiconductor integrated circuit device described above, high thermal conductivity is achieved by containing a plurality of thermally conductive materials made of highly thermally conductive materials in the bonding material used to bond the semiconductor chip to the bonding substrate. A bonding material layer is formed that enables
It is possible to improve the heat dissipation efficiency of the semiconductor integrated circuit device.
また、前記熱伝導材の形状を、直径が均一な球形状また
は同心円リング状、あるいは高さが均一な多面体形状ま
たは多角形リング状に形成したり、また素材を金属、ダ
イヤモンド、セラミックまたはこれらの複合体から形成
し、熱伝導材の直径または高さを、ダイボンディング後
の接合材厚にほぼ等しくなるように形成することにより
、ダイボンディング部の接合材厚が均一化され、半導体
集積回路装置の放熱性の均一化を図ることができる。Further, the shape of the heat conductive material may be formed into a spherical shape or concentric ring shape with a uniform diameter, a polyhedral shape or a polygonal ring shape with a uniform height, or the material may be metal, diamond, ceramic, or any of these materials. By forming the thermally conductive material from a composite so that its diameter or height is approximately equal to the thickness of the bonding material after die bonding, the thickness of the bonding material at the die bonding part is made uniform, and the semiconductor integrated circuit device It is possible to achieve uniform heat dissipation.
さらに、前記した半導体集積回路装置に用いられるプリ
フォーム接合材は、熱伝導材が、半導体チップとダイボ
ンディング基板との接合面に均一に含有されて形成され
ることにより、ダイボンディング工程が容易とされ、完
成された半導体集積回路装置における放熱性の均一化が
可能である。Furthermore, the preform bonding material used in the semiconductor integrated circuit device described above is formed so that the heat conductive material is uniformly contained in the bonding surface between the semiconductor chip and the die bonding substrate, thereby facilitating the die bonding process. It is possible to make the heat dissipation uniform in the completed semiconductor integrated circuit device.
［実施例１］
第１図は本発明の一実施例である半導体集積回路装置の
要部を示す断面図、第２図（ａ）および（ｂ）は本実施
例の半導体集積回路装置に用いられる熱伝導材を示す断
面図、第３図は本実施例の半導体集積回路装胃に最適な
プリフォーム接合材を示す断面図である。[Example 1] Fig. 1 is a sectional view showing the main parts of a semiconductor integrated circuit device according to an embodiment of the present invention, and Fig. 2 (a) and (b) are cross-sectional views showing main parts of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 3 is a sectional view showing a preform bonding material most suitable for the semiconductor integrated circuit package of this embodiment.
まず、第１図により本実施例の半導体集積回路装置の構
成を説明する。First, the configuration of the semiconductor integrated circuit device of this embodiment will be explained with reference to FIG.
本実施例の半導体集積回路装置は、たとえば半導体チッ
プ１がダイボンディング基板２に実装される半導体集積
回路装置とされ、半導体チップ１の背面が複数の高熱伝
導ボール（熱伝導材）３を含有するろう材（接合材）４
によってダイボンディング基板２の主面上に溶融固着さ
れている。The semiconductor integrated circuit device of this embodiment is, for example, a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a die bonding substrate 2, and the back surface of the semiconductor chip 1 contains a plurality of highly thermally conductive balls (thermal conductive material) 3. Brazing material (bonding material) 4
is melted and fixed onto the main surface of the die bonding substrate 2.
半導体チップ１は、ろう材４と接合可能となるようにそ
の背面にメタライズ層５が形成されている。また、メタ
ライズ層５は、たとえば下層よりＣｒ，Ｔｉ，Ｗなどの
接着層、Ｎｉ，Ｐｔ，Ｐｄ，Ｃ ｕ ， Ｍ ｏなどの
バリア層、Ａｕなどの酸化防止層が組み合わされ、三層
構造の複合膜から形成されている。A metallized layer 5 is formed on the back surface of the semiconductor chip 1 so that it can be bonded to a brazing material 4. In addition, the metallized layer 5 has a three-layer structure in which, from the bottom, an adhesive layer such as Cr, Ti, and W, a barrier layer such as Ni, Pt, Pd, Cu, Mo, and an oxidation prevention layer such as Au are combined. It is formed from a composite membrane.
ダイボンディング基板２は、半導体チップ１と同様に、
三層構造のメタライズ層６がその主面に形成されている
。The die bonding substrate 2, like the semiconductor chip 1,
A metallized layer 6 having a three-layer structure is formed on its main surface.
高熱伝導ボール３は、たとえばＭｏ，Ｗ，Ｆｅなどのろ
う材４と反応しない金属、またはＮ１，Ｃｒ，Ｃｏなど
のろう材４と反応し難い金属などの高熱伝導材料３ａか
ら形成され、第２図（ａ）に示すように球形の単体構造
とされている。The high thermal conductivity ball 3 is made of a high thermal conductivity material 3a such as a metal that does not react with the brazing filler metal 4 such as Mo, W, or Fe, or a metal that does not easily react with the brazing filler metal 4 such as N1, Cr, or Co. As shown in Figure (a), it has a spherical unitary structure.
一方、高熱伝導材料３ａが、ダイヤモンド．Ａｊｉ！Ｎ
，ＳｉＣ，Ｃ−ＢＮなどの絶縁材料、またはＡｇ，Ｃｕ
，Ａｕ，Ａｆなどのろう材４と反応し易い金属などから
形成される場合には、第２図０））のようにＴ ｉ／Ｎ
ｉ． Ｃ ｒ／Ｎ ｉ、またはＮｉなどによってメッ
キコートしたバリアメタル層３ｂが形成された被覆構造
のものが用いられる。On the other hand, the high thermal conductivity material 3a is diamond. Aji! N
, SiC, C-BN or other insulating materials, or Ag, Cu
, Au, Af, or other metals that easily react with the brazing filler metal 4, as shown in Fig. 2 0)).
i. A coating structure in which a barrier metal layer 3b plated with Cr/Ni, Ni, or the like is formed is used.
ろう材４は、たとえばＰｂ−Ｓｎ，Ａｕ−Ｓｎ，Ｐｂ−
Ａｇ系はんだが用いられ、第３図に示すようなろう材４
に高熱伝導ボール３が含有されたプリフォームろう材７
とされ、直径の等しい高熱伝導ボール３が均一に配合さ
れている。The brazing filler metal 4 is, for example, Pb-Sn, Au-Sn, Pb-
Ag-based solder is used, and the brazing material 4 as shown in Fig. 3 is used.
Preform brazing material 7 containing high thermal conductivity balls 3
High heat conductive balls 3 having the same diameter are uniformly mixed.
次に、本実施例の作用について説明する。Next, the operation of this embodiment will be explained.
以上のように構成される本実施例の半導体集積回路装置
においては、半導体チップ１のダイボンディング時に、
プリフォームろう材７に熱伝導材である複数の高熱伝導
ボール３が接合面上に均一に配置されることにより、ろ
う材４による接合層８を所望の厚さ、すなわち高熱伝導
ボール３の直径に均一化することができる。In the semiconductor integrated circuit device of this embodiment configured as described above, during die bonding of the semiconductor chip 1,
By uniformly disposing a plurality of high heat conductive balls 3, which are heat conductive materials, on the bonding surface of the preform brazing filler metal 7, the bonding layer 8 made of the brazing filler metal 4 can be formed to a desired thickness, that is, the diameter of the high heat conductive balls 3. can be homogenized.
また、この場合に高熱伝導ボール３の直径を変えること
により、接合層８を所望の厚さに形成することができる
。Further, in this case, by changing the diameter of the high thermal conductivity balls 3, the bonding layer 8 can be formed to have a desired thickness.
さらに、プリフォームろう材７に高熱伝導材料３ａによ
って形成された高熱伝導ボール３が含有されることによ
り、ろう材４による接合層８の高熱伝導化を図ることが
できる。Further, since the preform brazing material 7 contains the high thermal conductivity balls 3 made of the high thermal conductive material 3a, the bonding layer 8 made of the brazing material 4 can have high thermal conductivity.
従って、本実施例の半導体集積回路装萱によれば、半導
体チップ１の放熱性が接合面において均一化され、放熱
性の向上が可能とされる半導体集積回路装置を得ること
ができる。Therefore, according to the semiconductor integrated circuit device of this embodiment, the heat dissipation of the semiconductor chip 1 is made uniform at the bonding surface, and a semiconductor integrated circuit device can be obtained in which the heat dissipation can be improved.
［実施例２］
第４図は本発明の他の実施例である半導体集積回路装置
の要部を示す断面図、第５図（ａ）および（ｂ）は本実
施例の半導体集積回路装置に用いられる熱伝導材を示す
斜視図、第６図は本実施例の半導体集積回路装匿に最適
なプリフォーム接合材を示す断面図である。[Embodiment 2] FIG. 4 is a sectional view showing the main parts of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS. FIG. 6 is a perspective view showing the thermally conductive material used, and a sectional view showing the preform bonding material most suitable for packaging the semiconductor integrated circuit of this embodiment.
本実施例の半導体集積回路装置は、第４図に示すように
半導体チップ１がダイボンディング基板２に実装される
半導体集積回路装置とされ、実施例１との相違点は半導
体チップ１の背面が複数の高熱伝導リング（熱伝導材）
９を含有するろう材（接合材）４によってダイボンディ
ング基板２の主面上に溶融固着されている点である。The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a die bonding substrate 2 as shown in FIG. Multiple high thermal conductivity rings (thermal conductive material)
It is melted and fixed onto the main surface of the die bonding substrate 2 by a brazing material (bonding material) 4 containing 9.
すなわち、高熱伝導リング９は、実施例１と同様にろう
材と反応しない金属、またはろう材と反応し難い金属な
どの高熱伝導材料３ａから形成される場合には単体構造
とされ、一方絶縁材料またはろう材と反応し易い高熱伝
導材料３ａから形成される場合には、メッキコートした
被覆構造のものが用いられる。That is, when the high thermal conductivity ring 9 is formed from the high thermal conductive material 3a such as a metal that does not react with the brazing filler metal or a metal that does not easily react with the brazing filler metal as in Example 1, it has a unitary structure, whereas it has a single structure when it is formed from an insulating material. Alternatively, if it is made of a highly thermally conductive material 3a that easily reacts with the brazing material, a coated structure coated with plating is used.
そして、たとえば第５図（ａ）に示すような多角形、ま
たは第５図（ｂ）のように円形のリング状に形成され、
断面が多角形に形成されている。また、高熱伝導リング
９の高さは、ダイボンディング後のろう材４による接合
層８の厚さに合わせた所望の高さに形成されている。For example, it is formed into a polygonal shape as shown in FIG. 5(a) or a circular ring shape as shown in FIG. 5(b),
The cross section is polygonal. Further, the height of the high thermal conductivity ring 9 is formed to a desired height that matches the thickness of the bonding layer 8 made of the brazing material 4 after die bonding.
従って、本実施例の半導体集積回路装置によれば、実施
例１と同様にろう材４による接合層８を所望の厚さ、す
なわち熱伝導材である高熱伝導リング９の高さに均一化
することができ、接合層８の高熱伝導化を図ることがで
きる。これにより、半導体チップ１の放熱性が接合面に
おいて均一化され、放熱性の向上が可能とされる半導体
集積回路装置を得ることができる。Therefore, according to the semiconductor integrated circuit device of this embodiment, as in the first embodiment, the bonding layer 8 made of the brazing filler metal 4 is made uniform to the desired thickness, that is, the height of the high thermal conductivity ring 9 which is the thermal conductive material. Therefore, high thermal conductivity of the bonding layer 8 can be achieved. Thereby, the heat dissipation of the semiconductor chip 1 is made uniform at the bonding surface, and a semiconductor integrated circuit device can be obtained in which the heat dissipation can be improved.
［実施例３］
第７図は本発明のさらに他の実施例である半導体集積回
路装置の要部を示す断面図である。[Embodiment 3] FIG. 7 is a sectional view showing a main part of a semiconductor integrated circuit device which is still another embodiment of the present invention.
本実施例の半導体集積回路装置は、第７図に示すように
半導体チップ１がダイボンディング基板２に実装される
半導体集積回路装置とされ、実施例１および２との相違
点はろう材（接合材）４に高熱伝導材料３ａを含有する
ことなく、ダイボンディング基板２の表面に突起部２ａ
が形成されて半導体チップ１の背面が溶融固着されてい
る点である。The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a die bonding substrate 2 as shown in FIG. material) 4 does not contain the high thermal conductive material 3a, and the protrusions 2a are formed on the surface of the die bonding substrate 2.
is formed and the back surface of the semiconductor chip 1 is fused and fixed.
すなわち、ダイボンディング基板２は、その表面に第７
図に示すように複数の突起部２ａが形成され、この突起
部２ａがダイボンディング後のろう材４による接合層８
の厚さに合わせた所望の高さに形成されている。That is, the die bonding substrate 2 has the seventh layer on its surface.
As shown in the figure, a plurality of protrusions 2a are formed, and these protrusions 2a form a bonding layer 8 formed by the brazing material 4 after die bonding.
It is formed to a desired height according to the thickness of the plate.
従って、本実施例の半導体集積回路装置によれば、実施
例１および２と同様にろう材４による接合層８を所望の
厚さ、すなわちダイボンディング基板２の突起部２ａの
高さに均一化することができ、接合層８の高熱伝導化を
図ることができる。Therefore, according to the semiconductor integrated circuit device of this embodiment, the bonding layer 8 made of the brazing material 4 is made uniform to the desired thickness, that is, the height of the protrusion 2a of the die bonding substrate 2, as in the first and second embodiments. Therefore, high thermal conductivity of the bonding layer 8 can be achieved.
これにより、半導体チップ１の放熱性が接合面において
均一化され、放熱性の向上が可能とされる半導体集積回
路装置を得ることができる。Thereby, the heat dissipation of the semiconductor chip 1 is made uniform at the bonding surface, and a semiconductor integrated circuit device can be obtained in which the heat dissipation can be improved.
以上、本発明者によってなされた発明を実施例１〜３に
基づき具体的に説明したが、本発明は前記各実施例に限
定されるものではな《、その要旨を逸脱しない範囲で種
々変更可能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples 1 to 3. However, the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Needless to say, it is.
たとえば、実施例１の半導体集積回路装置については、
ろう材４に含有される高熱伝導ボール３が球形である場
合について説明したが、本発胡は前記実施例１に限定さ
れるものではなく、たとえば八面体などの多面体に形成
された高熱伝導ボール３についても広く適用可能とされ
、その大きさはダイボンディング後の接合層８の厚さに
合わせた所望の高さに形成されればよい。For example, regarding the semiconductor integrated circuit device of Example 1,
Although the case has been described in which the high heat conductive balls 3 contained in the brazing filler metal 4 are spherical, the present invention is not limited to the above-mentioned Example 1, and may be a high heat conductive ball formed into a polyhedron such as an octahedron. 3 is also widely applicable, and its size may be formed to a desired height that matches the thickness of the bonding layer 8 after die bonding.
また、実施例２における高熱伝導リング９についても、
断面が多角形である場合に限定されず、たとえば円形で
もよく、またリング形状にスリット加工したものでもよ
い。Also, regarding the high thermal conductivity ring 9 in Example 2,
The cross section is not limited to a polygon, but may be circular, or may be slit into a ring shape.
さらに、実施例３のダイボンディング基板２の突起部２
ａについても、第７図に示すような半楕球に限定されず
、たとえば半球または多面体でもよい。Furthermore, the protrusion 2 of the die bonding substrate 2 of Example 3
Also, a is not limited to a semi-ellipse as shown in FIG. 7, but may be a hemisphere or a polyhedron, for example.
［発明の効果］
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.
（１）．半導体チップが接合材を介してダイボンディン
グ基板に実装される半導体集積回路装置において、接合
材中に高熱伝導材料から形成される複数の熱伝導材が含
有されることにより、ダイボンディング部の高熱伝導化
が可能とされるので、半導体集積回路装置の放熱効率の
向上を図ることができる。(1). In a semiconductor integrated circuit device in which a semiconductor chip is mounted on a die bonding substrate via a bonding material, the bonding material contains a plurality of thermally conductive materials made of high thermally conductive materials, thereby achieving high thermal conductivity at the die bonding part. Therefore, it is possible to improve the heat dissipation efficiency of the semiconductor integrated circuit device.
（２），熱伝導材の形状を、直径が均一な球形状または
同心円リング状、あるいは高さが均一な多面体形状また
は多角形リング状に形成したり、また素材を金属、ダイ
ヤモンド、セラミックまたはこれらの複合体から形成し
、熱伝導材の直径または高さを、ダイボンディング後の
接合材厚にほぼ等しくなるように形成することにより、
ダイボンディング部の接合材厚が均一化され、高精度化
構造を得ることができるので、半導体集積回路装置の放
熱性の均一化を図ることができる。(2) The shape of the thermally conductive material may be formed into a spherical or concentric ring shape with a uniform diameter, or a polyhedral shape or polygonal ring shape with a uniform height, or the material may be metal, diamond, ceramic, or any of these materials. The diameter or height of the thermally conductive material is approximately equal to the thickness of the bonding material after die bonding.
Since the thickness of the bonding material at the die bonding portion is made uniform and a highly precise structure can be obtained, the heat dissipation of the semiconductor integrated circuit device can be made uniform.
（３）．半導体集積回路装置に用いられるプリフォーム
接合材において、熱伝導材が、単導体チップとダイボン
ディング基板との接合面に均一に含有されて形成される
ことにより、ダイボンディングエ程が容易とされると同
時に、完成された半導体集積回路装置における放熱性の
均一化が可能である。(3). In the preform bonding material used for semiconductor integrated circuit devices, the die bonding process is facilitated by uniformly containing a thermally conductive material on the bonding surface between the single conductor chip and the die bonding substrate. At the same time, it is possible to make the heat dissipation uniform in the completed semiconductor integrated circuit device.
（４）．前記（１）〜（３）により、放熱性の均一化お
よび高集積化が可能とされ、これらに起因する消費電力
密度の増大に対応できる半導体集積回路装置およびそれ
に用いられるプリフォーム接合材を得ることができる。(4). According to (1) to (3) above, a semiconductor integrated circuit device and a preform bonding material used therein are obtained, which enable uniform heat dissipation and high integration, and which can cope with the increase in power consumption density caused by these. be able to.
第１図は本発明の実施例１である半導体集積回路装置の
要部を示す断面図、
第２図（ａ）およびら）は実施例１の半導体集積回路装
置に用いられる熱伝導材を示す断面図、第３図は実施例
１の半導体集積回路装冒に最適なプリフォーム接合材を
示す断面図、
第４図は本発明の実施例２である半導体集積回路装置の
要部を示す断面図、
第５図（ａ）およびら）は実施例２の半導体集積回路装
置に用いられる熱伝導材を示す斜視図、第６図は実施例
２の半導体集積回路装置に最適なプリフォーム接合材を
示す断面図、
第７図は本発明の実施例３である半導体集積回路装置の
要部を示す断面図である。
１・・・半導体チップ、２・・・ダイボンディング基板
、２ａ・・・突起部、３・・・高熱伝導ボール（熱伝導
材）、３ａ・・・高熱伝導材料、３ｂ・・・バリアメタ
ル層、４・・・ろう材（接合材）、５．６・・・メタラ
イズ層、７・・・プリフォームろう材
（プリフォーム接合材）
８
・接合層、
９
・高熱伝導リング
（熱伝導材
）FIG. 1 is a sectional view showing the main parts of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view showing the preform bonding material most suitable for mounting a semiconductor integrated circuit according to the first embodiment, and FIG. 4 is a cross-sectional view showing the main parts of the semiconductor integrated circuit device according to the second embodiment of the present invention. 5(a) and 5(a) are perspective views showing a thermally conductive material used in the semiconductor integrated circuit device of Example 2, and FIG. 6 is a preform bonding material optimal for the semiconductor integrated circuit device of Example 2. FIG. 7 is a cross-sectional view showing essential parts of a semiconductor integrated circuit device according to a third embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor chip, 2...Die bonding board, 2a...Protrusion, 3...High heat conductive ball (thermal conductive material), 3a...High heat conductive material, 3b...Barrier metal layer , 4... Brazing material (bonding material), 5.6... Metallized layer, 7... Preform brazing material (preform bonding material) 8 - Bonding layer, 9 - High thermal conductive ring (thermal conductive material)
Claims (1)
板に実装される半導体集積回路装置であって、前記接合
材中に高熱伝導材料から形成される複数の熱伝導材が含
有されることを特徴とする半導体集積回路装置。 ２、前記熱伝導材が、直径が均一な球形状または同心円
リング状、あるいは高さが均一な多面体形状または多角
形リング状に形成されることを特徴とする請求項１記載
の半導体集積回路装置。 ３、前記熱伝導材が、金属、ダイヤモンド、セラミック
またはこれらの複合体から形成されることを特徴とする
請求項１記載の半導体集積回路装置。 ４、前記熱伝導材の直径または高さが、ダイボンディン
グ後の接合材厚にほぼ等しく形成されることを特徴とす
る請求項１記載の半導体集積回路装置。 ５、前記熱伝導材が、前記半導体チップと前記ダイボン
ディング基板との接合面に均一に含有されることを特徴
とする請求項１、２、３または４記載の半導体集積回路
装置に用いられるプリフォーム接合材。[Claims] 1. A semiconductor integrated circuit device in which a semiconductor chip is mounted on a die bonding substrate via a bonding material, wherein the bonding material contains a plurality of thermally conductive materials made of a highly thermally conductive material. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein the thermally conductive material is formed into a spherical shape or a concentric ring shape with a uniform diameter, or a polyhedral shape or a polygonal ring shape with a uniform height. . 3. The semiconductor integrated circuit device according to claim 1, wherein the thermally conductive material is made of metal, diamond, ceramic, or a composite thereof. 4. The semiconductor integrated circuit device according to claim 1, wherein the diameter or height of the thermally conductive material is formed to be approximately equal to the thickness of the bonding material after die bonding. 5. The substrate for use in a semiconductor integrated circuit device according to claim 1, 2, 3 or 4, wherein the thermally conductive material is uniformly contained in a bonding surface between the semiconductor chip and the die bonding substrate. Renovation bonding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1331690A JPH03218030A (en) | 1990-01-23 | 1990-01-23 | Semiconductor integrated circuit device and preform bonding material used in the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1331690A JPH03218030A (en) | 1990-01-23 | 1990-01-23 | Semiconductor integrated circuit device and preform bonding material used in the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03218030A true JPH03218030A (en) | 1991-09-25 |
Family
ID=11829771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1331690A Pending JPH03218030A (en) | 1990-01-23 | 1990-01-23 | Semiconductor integrated circuit device and preform bonding material used in the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03218030A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147870A (en) * | 1996-01-05 | 2000-11-14 | Honeywell International Inc. | Printed circuit assembly having locally enhanced wiring density |
| US6246014B1 (en) | 1996-01-05 | 2001-06-12 | Honeywell International Inc. | Printed circuit assembly and method of manufacture therefor |
| DE10030697A1 (en) * | 2000-06-23 | 2002-01-10 | Infineon Technologies Ag | Method for securing semiconductor chip on substrate compensates for mechanical stresses in substrate using tape/adhesive layer applied to substrate |
| WO2002009194A1 (en) * | 2000-07-26 | 2002-01-31 | The Research Foundation Of State University Of New York | Method and system for bonding a semiconductor chip onto a carrier using micro-pins |
| JP2011228604A (en) * | 2010-04-23 | 2011-11-10 | Honda Motor Co Ltd | Manufacturing method of circuit board and circuit board |
-
1990
- 1990-01-23 JP JP1331690A patent/JPH03218030A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147870A (en) * | 1996-01-05 | 2000-11-14 | Honeywell International Inc. | Printed circuit assembly having locally enhanced wiring density |
| US6246014B1 (en) | 1996-01-05 | 2001-06-12 | Honeywell International Inc. | Printed circuit assembly and method of manufacture therefor |
| DE10030697A1 (en) * | 2000-06-23 | 2002-01-10 | Infineon Technologies Ag | Method for securing semiconductor chip on substrate compensates for mechanical stresses in substrate using tape/adhesive layer applied to substrate |
| DE10030697C2 (en) * | 2000-06-23 | 2002-06-27 | Infineon Technologies Ag | Method for mounting a semiconductor chip on a substrate |
| WO2002009194A1 (en) * | 2000-07-26 | 2002-01-31 | The Research Foundation Of State University Of New York | Method and system for bonding a semiconductor chip onto a carrier using micro-pins |
| US7064432B2 (en) | 2000-07-26 | 2006-06-20 | The Research Foundation Of State University Of New York | Method and system for bonding a semiconductor chip onto a carrier using micro-pins |
| US7326637B2 (en) | 2000-07-26 | 2008-02-05 | Research Foundation Of State University Of New York | Method and system for bonding a semiconductor chip onto a carrier using micro-pins |
| JP2011228604A (en) * | 2010-04-23 | 2011-11-10 | Honda Motor Co Ltd | Manufacturing method of circuit board and circuit board |
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