JPH03152958A - Processing of polyimide film - Google Patents

Processing of polyimide film

Info

Publication number
JPH03152958A
JPH03152958A JP29274589A JP29274589A JPH03152958A JP H03152958 A JPH03152958 A JP H03152958A JP 29274589 A JP29274589 A JP 29274589A JP 29274589 A JP29274589 A JP 29274589A JP H03152958 A JPH03152958 A JP H03152958A
Authority
JP
Japan
Prior art keywords
polyimide film
cured part
semi
etched
polyimide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29274589A
Other languages
Japanese (ja)
Inventor
Shinichi Tonari
真一 隣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29274589A priority Critical patent/JPH03152958A/en
Publication of JPH03152958A publication Critical patent/JPH03152958A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain an opening high in dimensional accuracy by a method wherein a lower polyimide film fully-cured part is formed on the surface of semiconductor substrate, an upper polyimide film is applied to form a semi-cured part, the semi-cured part is etched, and then the fully-cured part is etched. CONSTITUTION:A lower aluminum wiring 2 is formed on the surface of a semiconductor substrate 1, and a lower polyimide film 3 is applied thereon, which is thermally treated to finish the polymerization of imide to form a fully cured part. Then, an upper polyimide film 4 is applied thereon, which is subjected to an incomplete heat treatment to form a semi-cured part, and a negative resist 5a is formed. In succession, the semiconductor substrate 1 is etched with an amine solution such as hydrazine, and then the fully-cured part is etched through an RIE method mainly using oxygen gas. Then, the negative resist 5a is separated off with alkylbenzen sulfonic acid, and the polymerization of imide of the semi-cured part is finished through a final heat treatment.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の多層配線の形成方法に関し、
特に眉間絶縁膜としてポリイミド膜を用いた加工方法に
関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming multilayer wiring of a semiconductor integrated circuit,
In particular, the present invention relates to a processing method using a polyimide film as an insulating film between the eyebrows.

〔従来の技術〕[Conventional technology]

従来ポリイミド膜にスルーホール加工する方法としては
、ウニ・ソI−エツチング法とドライエツチング法とが
あり、前者は使用するフォトレジストの種類によって、
ネガレジスト法とポジレジスト法とに分類されるので、
順を追って説明する。
Conventional methods for forming through holes in polyimide films include the Uni-Solution I-etching method and the dry etching method.
It is classified into negative resist method and positive resist method.
I will explain step by step.

ネガレジスI・法においては、イミド重合が始まる20
0〜250℃の温度でキュアしたポリイミド膜を、ネガ
レジストをマスクとして90〜110℃のしドラジンな
どのアミン溶液で選択エツチングしたのち、通常のアル
キルベンゼンスルフォン酸を用いてネガレジストを剥離
する。
In the NegaRegis I method, imide polymerization begins20
A polyimide film cured at a temperature of 0 to 250°C is selectively etched with an amine solution such as hydrodrazine at 90 to 110°C using a negative resist as a mask, and then the negative resist is peeled off using a common alkylbenzenesulfonic acid.

ポジレジスト法においては、ポリイミド膜をイミド重合
が起らない100〜200℃で乾燥したのち、テトラメ
チルアンモニウムハイドロオキサイド水溶液などのアル
カリ溶液を用いて、連続してポジレジストの溶解現像と
ポリイミド膜の選択エツチングを行なってから、ブチル
アセテ−1へなどでポジレジストを剥離する。
In the positive resist method, after drying the polyimide film at 100 to 200°C, where imide polymerization does not occur, an alkaline solution such as an aqueous solution of tetramethylammonium hydroxide is used to continuously dissolve and develop the positive resist and form the polyimide film. After selective etching, the positive resist is removed using butyl acetate 1 or the like.

ドライエツチング法としては、ポリイミド膜をイミド重
合が完了する300〜400℃でキュアしてから、ポジ
レジストまたはネガレジス1−をマスクとして、酸素ガ
スを主体としたRIE法でポリイミド膜を選択エツチン
グしたのち、通常通りアルキルベンゼンスルフォン酸を
用いてフォトレジストを剥離する。
The dry etching method involves curing the polyimide film at 300 to 400°C to complete imide polymerization, then selectively etching the polyimide film using a RIE method mainly using oxygen gas using a positive resist or negative resist 1- as a mask. , strip the photoresist using alkylbenzene sulfonic acid as usual.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の加工法では、多層配線のスルーホール口径や配線
幅の微細化に対処することができない。
Conventional processing methods cannot cope with miniaturization of the through-hole diameter and wiring width of multilayer wiring.

ウェットエツチング法においては第3図に示すように、
ポリイミド膜6の加工後の形状が、フォトレジスト5の
開口寸法に比較して大きく開いなすりばち状になる。
In the wet etching method, as shown in Figure 3,
The shape of the polyimide film 6 after processing becomes a dovetail shape with a larger opening compared to the opening size of the photoresist 5.

これはエツチング時のフォトレジスト5の膨潤や部分剥
離により、フォl〜レジストーポリイミド界面にエツチ
ング液が侵食した結果によるものである。
This is due to the etching solution corroding the photoresist polyimide interface due to swelling and partial peeling of the photoresist 5 during etching.

このためエツチングの寸法ばらつきを考慮すると、開口
寸法が膜厚の2〜3倍の3〜5μmが限度になっている
Therefore, taking into consideration the dimensional variations in etching, the opening size is limited to 3 to 5 .mu.m, which is 2 to 3 times the film thickness.

一方RIE法ではフォトレジストの開口寸法そのままに
、異方性エツチングが達成できるが、余りにも加工形状
が急峻であるために、第4図に示すように上層アルミニ
ウム配線7がスルーホールにおいて段切れするという問
題がある。
On the other hand, with the RIE method, anisotropic etching can be achieved with the opening dimensions of the photoresist unchanged, but because the processed shape is too steep, the upper layer aluminum wiring 7 is broken at the through hole as shown in FIG. There is a problem.

通常のスバ・ツタ法によるアルミニウム膜形成方法では
、スルーホールの口径はポリイミドの膜厚の2倍が最小
限度とされている。
In the ordinary method of forming an aluminum film using the Suba-Ivy method, the minimum diameter of the through-hole is twice the thickness of the polyimide film.

いずれにしても、層間絶縁膜として厚さ1.5μmのポ
リイミド膜を用いる場合は、開口寸法3μmが限界にな
っていた。
In any case, when a polyimide film with a thickness of 1.5 μm is used as an interlayer insulating film, the opening size is limited to 3 μm.

〔゛課題を解決するための手段〕[Means to solve problems]

本発明のポリイミドの加工法は、半導体基板表面に下層
ポリイミド膜を塗布し、熱処理してイミド重合を完了さ
せたのち、上層のポリイミド膜を塗布して不完全な熱処
理を行なってから、フォトリソグラフィにて上層の半硬
化部分をヒドラジンなとのアミン溶液でエツチングした
のち、酸素ガスを主体としたRIE法で下層の全硬化部
分をエツチングしてから、アルキルベンゼンスルフォン
酸などを用いてフォー・レジストを剥離したのち、最終
熱処理によって上層の半硬化部分のイミド重合を完了さ
せるものである。
In the polyimide processing method of the present invention, a lower polyimide film is applied to the surface of a semiconductor substrate, heat treatment is performed to complete imide polymerization, an upper polyimide film is applied, incomplete heat treatment is performed, and then photolithography is performed. After etching the semi-hardened part of the upper layer with an amine solution such as hydrazine, the fully hardened part of the lower layer is etched by RIE method mainly using oxygen gas, and then a four-resist is applied using alkylbenzene sulfonic acid. After peeling, a final heat treatment completes the imide polymerization of the semi-cured portion of the upper layer.

本発明の目的は、層間絶縁膜としてポリイミドを用いて
、正確な開口寸法を確保しながら、上層のアルミニウム
配線の被覆性を実現することにある。
An object of the present invention is to use polyimide as an interlayer insulating film to achieve coverage of upper layer aluminum wiring while ensuring accurate opening dimensions.

〔実施例〕〔Example〕

本発明の第1の実施例について、第1図(a>〜(d)
を参照して説明する9 半導体基板表面1に下層アルミニウム配線2を形成した
のち、下層ポリイミド膜3を回転塗布する そのあと窒素オーブンに入れて、100℃で1時間、2
50℃で1時間、4oo℃で1時間引き続いて熱処理を
行ない、厚さ5000人の下層ポリイミドlll3を形
成する。
Regarding the first embodiment of the present invention, FIG. 1 (a>-(d)
9 After forming the lower layer aluminum wiring 2 on the semiconductor substrate surface 1, the lower layer polyimide film 3 is spin-coated.Then, it is placed in a nitrogen oven and heated at 100°C for 1 hour for 2 hours.
Subsequent heat treatments are performed at 50° C. for 1 hour and at 400° C. for 1 hour to form a lower polyimide layer 113 with a thickness of 5000.

つぎに上層ポリイミド膜4を回転塗布し、窒素オーブン
に入れて、100℃で1時間、250℃で30分熱処理
を行なう。
Next, the upper polyimide film 4 is spin-coated, placed in a nitrogen oven, and heat treated at 100° C. for 1 hour and 250° C. for 30 minutes.

続いてネガレジスト5aを形成する。ネガレジスト5が
後続のRIE法によるドライエツチングに耐えるために
は、1.5μm以上の膜厚が必要である(第1図(a)
)。
Subsequently, a negative resist 5a is formed. In order for the negative resist 5 to withstand dry etching by the subsequent RIE method, a film thickness of 1.5 μm or more is required (Fig. 1(a)).
).

つぎに第1図(b)に示すように、ヒドラジンなどのア
ミン溶液を用いて上層のポリイミド4のエツチングを行
なう。
Next, as shown in FIG. 1(b), the upper layer of polyimide 4 is etched using an amine solution such as hydrazine.

このとき下層のポリイミドはイミド結合が完全に終了し
ているため、はとんどエツチングされない つぎに第1図(c)に示すように、酸素ガスを主体とし
たガスを用いたRIEにより、ネガレジスト5aの開口
直下の下層ポリイミド4を異方性エツチングする。
At this time, the polyimide in the lower layer is not etched because the imide bonds are completely completed.Next, as shown in FIG. 1(c), the negative layer is etched by RIE using a gas mainly composed of oxygen The lower polyimide layer 4 directly under the opening of the resist 5a is anisotropically etched.

つぎにアルキルベンスルフォン酸を用いてネガレジスト
5aを剥離するく第1図(d))。
Next, the negative resist 5a is removed using alkylbensulfonic acid (FIG. 1(d)).

そのあと400℃で1時間の加熱により、上層 − ポリイミド4の重合を完了させる。Then, by heating at 400℃ for 1 hour, the upper layer - Polymerization of polyimide 4 is completed.

つぎに本発明の第2の実施例を第2図(a)。Next, a second embodiment of the present invention is shown in FIG. 2(a).

(b)を参照して説明する。This will be explained with reference to (b).

上層ポリイミド膜4を回転塗布するところまでは、第1
の実施例と同様である。
Until the upper layer polyimide film 4 is spin-coated, the first
This is similar to the embodiment.

そのあと窒素オーブンに入れて、I 50 ℃で1時間
熱処理を行なう。
Thereafter, it is placed in a nitrogen oven and heat treated at I 50° C. for 1 hour.

つぎにポジレジスト5bを形成する。Next, a positive resist 5b is formed.

この場合は通常のアルカリ溶液による現像工程で、上層
ポリイミド4も同時にエツチングされるのは、従来技術
と同様である。
In this case, the upper polyimide layer 4 is also etched at the same time in the normal alkaline solution development step, as in the prior art.

つぎにRI E法で下層ポリイミド3を選択工・ソチン
グしてから、ブチルアセテートでボジレジス)5bを剥
離する。
Next, the lower polyimide layer 3 is selectively etched and soothed using the RIE method, and then the polyimide layer 5b is peeled off using butyl acetate.

最後に窒素オーブンに入れて、250℃で1時間、40
0℃で1時間加熱して、1層ポリイミド4のイミド重合
を完了する。
Finally, put it in a nitrogen oven for 1 hour at 250℃ for 40 minutes.
The imide polymerization of the one-layer polyimide 4 is completed by heating at 0° C. for 1 hour.

〔発明の効果〕〔Effect of the invention〕

本発明によりポリイミドを層間絶縁膜とした多層配線構
造において、スルーポールの口径を縮小することが可能
となり、かつスルーホールの形状を上層ポリイミドはテ
ーパー状に保ちながら、下層ポリイミドはR,I E法
により寸法通りに方向性上・ソチングするという、理想
的なパターン形成が実現された。
According to the present invention, in a multilayer wiring structure using polyimide as an interlayer insulating film, it is possible to reduce the diameter of the through hole, and while keeping the shape of the through hole tapered in the upper layer polyimide, the lower layer polyimide can be formed using the R, IE method. The ideal pattern formation was achieved by directional soching according to the dimensions.

」二層ポリイミドがテーパー状に形成されることにより
、」二層アルミニウム配線の被覆性も改善されて、段切
れを解消することができた。
``By forming the two-layer polyimide into a tapered shape,'' the coverage of the two-layer aluminum wiring was improved, and step breakage could be eliminated.

このため半導体集積回路の微細化、高速化、高集積化が
可能となった。
This has made it possible to make semiconductor integrated circuits smaller, faster, and more highly integrated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は本発明の第1の実施例を工程順
に示す断面図、第2図(a>、(b)は本発明の第2の
実施例を工程順に示す断面図、第3図はウェットエツチ
ング法による従来技術の問題点を示す断面図、第4図は
RIE法による従来技術の問題点を示す断面図。 1・・・半導体基板、2・・・下層アルミニウム配線、
3・・・下層ポリイミド膜、4・・・上層ポリイミド膜
、5・・・フォトレジスト、5a・・ネガレジスト、5
1)・・・ポジレジスト、6・・・ポリイミド膜、7・
・・上層アルミニウム配線。
FIGS. 1(a) to (d) are cross-sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (b) are cross-sectional views showing the second embodiment of the present invention in the order of steps. Figure 3 is a sectional view showing the problems of the conventional technique using the wet etching method, and Fig. 4 is a sectional view showing the problems of the conventional technique using the RIE method. 1... Semiconductor substrate, 2... Lower layer aluminum wiring,
3... Lower layer polyimide film, 4... Upper layer polyimide film, 5... Photoresist, 5a... Negative resist, 5
1)...Positive resist, 6...Polyimide film, 7.
...Top layer aluminum wiring.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板表面に下層ポリイミド膜を塗布し、熱処理
してイミド重合を完了させて全硬化部分を形成したのち
、上層ポリイミド膜を塗布して不完全な熱処理を行なっ
て半硬化部分を形成してから、フォトリソグラフィにて
半硬化部分をヒドラジンなどのアミン溶液でエッチング
して、酸素ガスを主体としたRIE法で全硬化部分をエ
ッチングしてから、アルキルベンゼンスルフォン酸など
を用いてフォトレジストを剥離したのち、最終熱処理に
よつて半硬化部分のイミド重合を完了させることを特徴
とするポリイミド膜の加工方法。
A lower polyimide film is applied to the surface of the semiconductor substrate, heat-treated to complete imide polymerization to form a fully cured part, and then an upper polyimide film is applied and an incomplete heat treatment is performed to form a semi-hardened part. , After etching the semi-cured part using photolithography with an amine solution such as hydrazine, etching the fully cured part using RIE method mainly using oxygen gas, and then peeling off the photoresist using alkylbenzene sulfonic acid etc. A method for processing a polyimide film, characterized by completing imide polymerization of a semi-cured portion by final heat treatment.
JP29274589A 1989-11-09 1989-11-09 Processing of polyimide film Pending JPH03152958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29274589A JPH03152958A (en) 1989-11-09 1989-11-09 Processing of polyimide film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29274589A JPH03152958A (en) 1989-11-09 1989-11-09 Processing of polyimide film

Publications (1)

Publication Number Publication Date
JPH03152958A true JPH03152958A (en) 1991-06-28

Family

ID=17785784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29274589A Pending JPH03152958A (en) 1989-11-09 1989-11-09 Processing of polyimide film

Country Status (1)

Country Link
JP (1) JPH03152958A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103851173A (en) * 2012-12-06 2014-06-11 现代自动车株式会社 Shifting apparatus for vehicle with DCT and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103851173A (en) * 2012-12-06 2014-06-11 现代自动车株式会社 Shifting apparatus for vehicle with DCT and control method thereof

Similar Documents

Publication Publication Date Title
JPH03177021A (en) Manufacture of semiconductor device
US6759317B2 (en) Method of manufacturing semiconductor device having passivation film and buffer coating film
JPH11145278A (en) Manufacture of semiconductor device
JPH03152958A (en) Processing of polyimide film
JPH09306901A (en) Manufacture of semiconductor device
JPH0770538B2 (en) Method for forming patterned thin film on substrate
JPS63202939A (en) Manufacture of multilayer interconnection
JP2594572B2 (en) Lift-off flattening method
KR100365756B1 (en) A method for forming contact hole of semiconductor device
JPH0239433A (en) Manufacture of semiconductor device
JP2950059B2 (en) Method for manufacturing semiconductor device
JPH0237707A (en) Manufacture of semiconductor device
JPH09199473A (en) Pattern formation of polyimide resin film
JPH05243217A (en) Manufacture of semiconductor device
JP2912002B2 (en) Method for manufacturing semiconductor device
JPH02178950A (en) Manufacture of semiconductor device
JPH04179124A (en) Manufacture of semiconductor device
JPH02284425A (en) Manufacture of semiconductor device
JPH10144674A (en) Polyimide film for electronic device
JPH04257238A (en) Manufacture of semiconductor device
JPS6273739A (en) Forming method for multilayer interconnection
JPH02132830A (en) Selective oxidation
JPS63119549A (en) Manufacture of semiconductor element
JPH079939B2 (en) Multilayer wiring formation method
JP2004103625A (en) Lift-off process using cryogenic liquid