JPH04257238A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04257238A JPH04257238A JP1864391A JP1864391A JPH04257238A JP H04257238 A JPH04257238 A JP H04257238A JP 1864391 A JP1864391 A JP 1864391A JP 1864391 A JP1864391 A JP 1864391A JP H04257238 A JPH04257238 A JP H04257238A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polyimide
- polyimide film
- semiconductor device
- carbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229920001721 polyimide Polymers 0.000 claims abstract description 58
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 23
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000004642 Polyimide Substances 0.000 claims abstract description 21
- 238000004380 ashing Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 16
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 7
- 239000003960 organic solvent Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- 230000007850 degeneration Effects 0.000 abstract 1
- 239000007788 liquid Substances 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012778 molding material Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 150000001721 carbon Chemical class 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、高信頼性の半導体装置
を得るための半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for obtaining a highly reliable semiconductor device.
【０００２】0002
【従来の技術】近年、素子の微細化，高密度化に伴って
、半導体素子の応力の影響を受け易くなっている。特に
、拡散工程後の実装工程で、半導体素子にかかる応力が
大きいため、この工程での応力を低減する目的でポリイ
ミド膜が応力緩和材として一般的に用いられている。2. Description of the Related Art In recent years, with the miniaturization and higher density of semiconductor devices, semiconductor devices have become more susceptible to stress. In particular, since the stress applied to semiconductor elements is large in the mounting process after the diffusion process, a polyimide film is generally used as a stress relaxation material for the purpose of reducing the stress in this process.
【０００３】ここでは例として、拡散工程完了後、実装
工程の直前でポリイミド膜を形成する場合について説明
する。[0003] As an example, a case will be described in which a polyimide film is formed after the completion of the diffusion process and immediately before the mounting process.
【０００４】図２は、ボンディングパッド用のＡＩ（ア
ルミニウム）部分での断面図である。図２において、１
は単結晶シリコン、２はＳｉＯ２膜、３はＳｉ，Ｃｕを
含有したＡｌ膜、４はｐ−ＳｉＮ膜、５はポリイミド膜
、６はポリイミド変質層である。ここで、ボンディング
パッド用Ａｌ膜３の上に、保護膜としてｐ−ＳｉＮ膜４
が形成されており、さらにその上に応力緩和材としての
ポリイミド膜５が形成されている。ボンディングパッド
用Ａｌ膜３の上部のｐ−ＳｉＮ膜４とポリイミド膜５は
、その後のボンディングのため除去されている。ここで
、ポリイミド膜５は、Ａｌ膜３上を開孔した後、４００
℃で硬化して最終状態のポリイミド膜にするため、その
硬化の際の炭素系堆積物が先にポリイミド膜を開孔した
領域に堆積する。Ａｌ膜３上にこの炭素系堆積物が存在
すると、ボンディング材とＡｌ膜３の密着強度が劣化し
てしまうため、Ａｌ膜３上の炭素系堆積物を除去する目
的で、オゾンによるアッシングを行ない、先に開孔した
領域の炭素系堆積物を除去していた。FIG. 2 is a cross-sectional view of an AI (aluminum) portion for a bonding pad. In Figure 2, 1
2 is a single crystal silicon, 2 is an SiO2 film, 3 is an Al film containing Si and Cu, 4 is a p-SiN film, 5 is a polyimide film, and 6 is a polyimide altered layer. Here, a p-SiN film 4 is placed as a protective film on the bonding pad Al film 3.
is formed thereon, and a polyimide film 5 as a stress relaxation material is further formed thereon. The p-SiN film 4 and polyimide film 5 above the bonding pad Al film 3 are removed for subsequent bonding. Here, after opening the polyimide film 5 on the Al film 3,
Since the polyimide film is cured at a temperature of 0.degree. C. to form the final state of the polyimide film, carbon-based deposits during the curing are deposited in the areas where the polyimide film was previously opened. If this carbon-based deposit exists on the Al film 3, the adhesion strength between the bonding material and the Al film 3 will deteriorate, so in order to remove the carbon-based deposit on the Al film 3, ashing with ozone is performed. , the carbon-based deposits in the area where the holes were drilled earlier were removed.
【０００５】なお、炭素系堆積物の膜厚でボンディング
材の密着強度の間には、図３のような相関が存在するた
め、炭素系堆積物の膜厚は２０Å以下であることが好ま
しい。[0005] Since there is a correlation between the thickness of the carbon-based deposit and the adhesion strength of the bonding material as shown in FIG. 3, the thickness of the carbon-based deposit is preferably 20 Å or less.
【０００６】以上の構造のＡｌボンディングパッドにお
いては、Ａｌパッド上の炭素系堆積物は除去できるが、
オゾンアッシング時にポリイミド膜５自体もオゾンアッ
シングされるため、ポリイミド膜５の表面の０．３μｍ
以下の領域にポリイミド変質層６ができてしまっていた
。[0006] In the Al bonding pad having the above structure, carbon deposits on the Al pad can be removed, but
Since the polyimide film 5 itself is also subjected to ozone ashing during ozone ashing, 0.3 μm of the surface of the polyimide film 5
A polyimide degraded layer 6 was formed in the following areas.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、ポリイミド膜の硬化時に付着する炭素系堆
積物を除去する際に、ポリイミド膜の表面に変質層がで
きるため、その後のモールド材との密着性が劣化し、半
導体装置の信頼性上で課題があった。[Problems to be Solved by the Invention] However, in the above-mentioned conventional structure, when removing the carbon-based deposits that adhere to the polyimide film when it is cured, a degraded layer is formed on the surface of the polyimide film, which makes it difficult to bond with the subsequent molding material. Adhesion deteriorated, causing problems in the reliability of semiconductor devices.
【０００８】本発明は、このような課題を解決するもの
で、Ａｌパッドとボンディング材との密着強度を劣化さ
せることなく、ポリイミド膜とモールド材との密着性を
向上した半導体装置を提供することを目的とする。The present invention is intended to solve these problems, and provides a semiconductor device in which the adhesion between the polyimide film and the molding material is improved without deteriorating the adhesion strength between the Al pad and the bonding material. With the goal.
【０００９】[0009]
【課題を解決するための手段】この目的を達成するため
に本発明の半導体装置の製造方法は、ポリイミド膜の硬
化時にできた炭素系堆積物をオゾンアッシング法により
除去する工程と、そのオゾンアッシング時にできたポリ
イミド膜の表面のポリイミド変質層をボンディングパッ
ド用アルミニウム上にフォトレジストパターンを形成し
て保護しポリイミド剥離液によって除去する工程と、前
述のフォトレジストパターンを有機溶剤で除去する工程
とを少なくとも有する構成による。[Means for Solving the Problems] In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes a step of removing carbon-based deposits formed during curing of a polyimide film by an ozone ashing method, and The polyimide deterioration layer formed on the surface of the polyimide film is protected by forming a photoresist pattern on the bonding pad aluminum, and the process is removed with a polyimide stripping solution, and the process of removing the photoresist pattern with an organic solvent. At least according to the configuration.
【００１０】0010
【作用】この構成によって、ポリイミド変質層をポリイ
ミド剥離液によって除去する際、ボンディングパッド用
アルミニウム上はフォトレジストで保護され、その後フ
ォトレジストを有機溶剤で除去すると、ポリイミド膜の
表面は損傷を受けない。[Operation] With this structure, when the polyimide degraded layer is removed using a polyimide stripping solution, the bonding pad aluminum surface is protected by the photoresist, and when the photoresist is then removed using an organic solvent, the surface of the polyimide film is not damaged. .
【００１１】[0011]
【実施例】本発明の半導体装置の製造方法の一実施例を
図１を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
【００１２】まず、図１（ａ）において単結晶シリコン
１上に、ＳｉＯ２２を９００〜１０００℃で５０００〜
１００００Å形成する。その後、ＳｉとＣｕを含有した
Ａｌをスパッタリング法でＳｉＯ２膜２上に堆積し、Ａ
ｌ膜３とする。この時のスパッタリングの条件は、圧力
５〜１０ｍＴｏｒｒ、パワー５〜１０ＫＷとし、Ａｌ膜
３の膜厚は０．５〜１．０μｍとする。その後、フォト
リソ法によって、所定の場所のみレジストを残し（図示
せず）、そのレジストをマスクにしてＡｌ膜３をエッチ
ングする。エッチング後、レジストをアッシングによっ
て除去する。その後、３８０〜４５０℃でＡｌ膜３のシ
ンタリングをＨ２雰囲気で行なう。その後、ｐ−ＳｉＮ
を全面に０．５〜１．５μｍ堆積してｐ−ＳｉＮ膜４を
形成する。ｐ−ＳｉＮ膜４堆積後、フォトリソ法によっ
て、ボンディングパッド用Ａｌ膜上以外の領域にレジス
トを残し、ドライエッチによってＡｌ膜３上のｐ−Ｓｉ
Ｎ膜４を除去する。その後、アッシングでレジストを除
去する。次に、３８０〜４５０℃のＨ２雰囲気で熱処理
を行ない、拡散工程を完了する。次に全面にワニス状の
ポリイミド前駆体（図示せず）をスピンコート法で５〜
１０μｍ塗布する。ここではネガ型感光性ポリイミドに
ついて説明する。その後、１００℃で数分溶剤を揮発さ
せて、ステッパーまたはプロジェクションアライナーで
露光を行なう。露光時間はステッパーで５００〜１００
０ＭＳＥＣとする。その後、露光された領域以外の領域
のポリイミド前駆体をＮＭＰ（Ｎ−メチル−２−ピロリ
ドン）を含む溶剤によって除去（現像）する。この時、
ボンディングパッド用Ａｌ膜３上のポリイミド前駆体は
除去しておく。現像後、Ｎ２雰囲気で３００〜４００℃
で前記ポリイミド前駆体を硬化させ、ポリイミド膜５に
する。この時、最終状態でのポリイミド膜５の膜厚は初
期のワニス状態での膜厚の半分程度になる。この硬化の
時に、ワニス状態で含まれていた溶剤および感光基が揮
発し、その一部がウエハ上に炭素系堆積物７となって付
着する。この時の膜厚は５０〜１００Å程度である。First, in FIG. 1(a), SiO22 is heated at 900 to 1000° C. to 5000° C. on a single crystal silicon 1.
A thickness of 10,000 Å is formed. After that, Al containing Si and Cu is deposited on the SiO2 film 2 by sputtering method, and Al containing Si and Cu is deposited on the SiO2 film 2.
1 film 3. The sputtering conditions at this time are a pressure of 5 to 10 mTorr, a power of 5 to 10 KW, and a thickness of the Al film 3 of 0.5 to 1.0 μm. Thereafter, by photolithography, a resist is left only at predetermined locations (not shown), and the Al film 3 is etched using the resist as a mask. After etching, the resist is removed by ashing. Thereafter, the Al film 3 is sintered at 380 to 450° C. in an H2 atmosphere. After that, p-SiN
A p-SiN film 4 is formed by depositing 0.5 to 1.5 μm over the entire surface. After depositing the p-SiN film 4, a resist is left on the area other than on the bonding pad Al film by photolithography, and the p-SiN film 4 on the Al film 3 is removed by dry etching.
The N film 4 is removed. After that, the resist is removed by ashing. Next, heat treatment is performed in an H2 atmosphere at 380 to 450°C to complete the diffusion process. Next, a varnish-like polyimide precursor (not shown) is applied over the entire surface by spin coating.
Apply 10 μm. Here, negative photosensitive polyimide will be explained. Thereafter, the solvent is evaporated at 100° C. for several minutes, and exposure is performed using a stepper or projection aligner. Exposure time is 500 to 100 with a stepper.
Set to 0MSEC. Thereafter, the polyimide precursor in areas other than the exposed area is removed (developed) using a solvent containing NMP (N-methyl-2-pyrrolidone). At this time,
The polyimide precursor on the bonding pad Al film 3 is removed. After development, 300-400℃ in N2 atmosphere
The polyimide precursor is cured to form a polyimide film 5. At this time, the film thickness of the polyimide film 5 in the final state is about half of the film thickness in the initial varnish state. At the time of this curing, the solvent and photosensitive group contained in the varnish state are volatilized, and some of them adhere as carbon-based deposits 7 on the wafer. The film thickness at this time is about 50 to 100 Å.
【００１３】次に図１（ｂ）に示すように、オゾンアッ
シングによって炭素系堆積物７を除去する。この時のオ
ゾンアッシング条件は、基板温度１８０〜２５０℃、ア
ッシング時間１０〜６０秒程度とする。この時、ポリイ
ミド膜５もオゾンアッシングされるため、表面に０．３
μｍ程度のポリイミド変質層６ができる。次に全面にレ
ジスト８を０．５〜１．０μｍスピンコート法で塗布す
る。その後、露光，現像によって所定の場所のみレジス
ト８を残すようにする。この時、Ａｌ膜３上にはレジス
ト８を残すようにする。Next, as shown in FIG. 1(b), the carbonaceous deposit 7 is removed by ozone ashing. The ozone ashing conditions at this time are a substrate temperature of 180 to 250° C. and an ashing time of about 10 to 60 seconds. At this time, since the polyimide film 5 is also subjected to ozone ashing, 0.3
A polyimide degraded layer 6 of about μm size is formed. Next, a resist 8 with a thickness of 0.5 to 1.0 μm is applied over the entire surface by spin coating. Thereafter, the resist 8 is left only in predetermined areas by exposure and development. At this time, the resist 8 is left on the Al film 3.
【００１４】次に図１（ｃ）に示すように、ポリイミド
剥離液でポリイミド膜５の表面の変質層６とポリイミド
膜５の一部を除去し、清浄なポリイミド膜５の表面を露
出させる。その後、レジスト８を１５〜２５℃のアセト
ンで除去する。アセトンでは、レジスト８以外の膜は変
質しないため、レジスト以外の膜に損傷を与えることな
く、レジスト８を除去できる。Next, as shown in FIG. 1C, the degraded layer 6 on the surface of the polyimide film 5 and a part of the polyimide film 5 are removed using a polyimide stripper to expose the clean surface of the polyimide film 5. Thereafter, the resist 8 is removed with acetone at 15 to 25°C. Since acetone does not change the quality of the films other than the resist 8, the resist 8 can be removed without damaging the films other than the resist.
【００１５】以上の構造のボンディングパッドにおいて
は、炭素系堆積物７除去のためのオゾンアッシングによ
ってできた変質層６を、ポリイミド剥離液によって除去
し、清浄なポリイミド膜５の表面を露出させることがで
きる。In the bonding pad having the above structure, the altered layer 6 formed by ozone ashing to remove the carbon-based deposits 7 can be removed using a polyimide stripping solution to expose the clean surface of the polyimide film 5. can.
【００１６】なお、ポリイミド膜５の硬化時にできた炭
素系堆積物７をオゾンアッシング法により除去する際、
炭素系堆積物７を完全に除去する必要は必ずしもなく、
図３に示すように炭素系堆積物の膜厚が２０Å以下であ
ればよい。[0016] When removing the carbon-based deposit 7 formed during curing of the polyimide film 5 by the ozone ashing method,
It is not necessarily necessary to completely remove the carbon-based deposits 7;
As shown in FIG. 3, it is sufficient if the thickness of the carbon-based deposit is 20 Å or less.
【００１７】[0017]
【発明の効果】以上のように本発明の半導体装置の製造
方法は、ポリイミド膜の硬化時にできた炭素系堆積物を
オゾンアッシング法により除去する工程と、そのオゾン
アッシング時にできたポリイミド膜の表面のポリイミド
変質層をボンディングパッド用アルミニウム上にフォト
レジストパターンを形成して保護しポリイミド剥離液に
よって除去する工程と、前述のフォトレジストパターン
を有機溶剤で除去する工程とを少なくとも有する構成に
よるので、清浄なポリイミド膜の表面を露出させ、かつ
炭素系堆積物を除去できるため、Ａｌ膜とボンディング
材との密着強度を劣化させることなく、その後のポリイ
ミド膜とモールド材との密着性が向上し、高信頼性の半
導体装置を提供できる。Effects of the Invention As described above, the method for manufacturing a semiconductor device of the present invention includes a step of removing carbon-based deposits formed during curing of a polyimide film by an ozone ashing method, and a step of removing carbon-based deposits formed during curing of a polyimide film, This structure includes at least the steps of forming a photoresist pattern on the bonding pad aluminum to protect the degraded polyimide layer and removing it with a polyimide stripping solution, and removing the photoresist pattern with an organic solvent. Since the surface of the polyimide film can be exposed and carbon-based deposits can be removed, the adhesion between the polyimide film and the molding material is improved without degrading the adhesion strength between the Al film and the bonding material, resulting in a high A reliable semiconductor device can be provided.
【図１】本発明の一実施例の半導体装置の製造方法を示
す工程断面図FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体装置の断面図[Figure 2] Cross-sectional view of a conventional semiconductor device
【図３】炭素系堆積物の膜厚に対するＡｌパッドとボン
ディング材の密着強度の相関図[Figure 3] Correlation diagram of adhesion strength between Al pad and bonding material with respect to film thickness of carbon-based deposit
１ 単結晶シリコン
２ ＳｉＯ２膜
３ アルミニウム膜（Ｓｉ，Ｃｕ含有）４ ｐ−Ｓ
ｉＮ膜
５ ポリイミド膜
６ ポリイミド変質層
７ 炭素系堆積物
８ レジスト（フォトレジスト）1 Single crystal silicon 2 SiO2 film 3 Aluminum film (containing Si and Cu) 4 p-S
iN film 5 Polyimide film 6 Polyimide altered layer 7 Carbon-based deposit 8 Resist (photoresist)
Claims (2)
きた炭素系堆積物をオゾンアッシング法により除去する
工程と、そのオゾンアッシング時にできたポリイミド膜
の表面のポリイミド変質層をボンディングパッド用アル
ミニウム上にフォトレジストパターンを形成して保護し
ポリイミド剥離液によって除去する工程と、前記フォト
レジストパターンを有機溶剤で除去する工程とを少なく
とも有することを特徴とする半導体装置の製造方法。1. A step of removing carbon-based deposits formed during curing of a polyimide film as an insulating film by ozone ashing, and removing a polyimide altered layer on the surface of the polyimide film formed during the ozone ashing onto an aluminum bonding pad. 1. A method for manufacturing a semiconductor device, comprising at least the steps of forming and protecting a photoresist pattern on the substrate and removing it with a polyimide stripping solution, and removing the photoresist pattern with an organic solvent.
きた炭素系堆積物をオゾンアッシング法により除去する
工程が、ポリイミド膜の硬化時にできた炭素系堆積物の
膜厚が２０Å以下になるようにオゾンアッシング法によ
り除去する工程であることを特徴とする請求項１記載の
半導体装置の製造方法。2. The step of removing carbon-based deposits formed during curing of the polyimide film as an insulating film by ozone ashing is performed so that the film thickness of the carbon-based deposits formed during curing of the polyimide film is 20 Å or less. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of removing by an ozone ashing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1864391A JPH04257238A (en) | 1991-02-12 | 1991-02-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1864391A JPH04257238A (en) | 1991-02-12 | 1991-02-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04257238A true JPH04257238A (en) | 1992-09-11 |
Family
ID=11977290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1864391A Pending JPH04257238A (en) | 1991-02-12 | 1991-02-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04257238A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100508748B1 (en) * | 1998-02-05 | 2005-11-11 | 삼성전자주식회사 | Polyimide Film Discombing Method and Rework Method of Semiconductor Device |
| WO2008026328A1 (en) | 2006-08-30 | 2008-03-06 | Alps Electric Co., Ltd. | Magnetism detector and its manufacturing method |
-
1991
- 1991-02-12 JP JP1864391A patent/JPH04257238A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100508748B1 (en) * | 1998-02-05 | 2005-11-11 | 삼성전자주식회사 | Polyimide Film Discombing Method and Rework Method of Semiconductor Device |
| WO2008026328A1 (en) | 2006-08-30 | 2008-03-06 | Alps Electric Co., Ltd. | Magnetism detector and its manufacturing method |
| US7564238B2 (en) | 2006-08-30 | 2009-07-21 | Alps Electric Co., Ltd. | Magnetic detection device connecting element and detection circuit and method of manufacturing the same |
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