JPH03149829A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03149829A JPH03149829A JP28947189A JP28947189A JPH03149829A JP H03149829 A JPH03149829 A JP H03149829A JP 28947189 A JP28947189 A JP 28947189A JP 28947189 A JP28947189 A JP 28947189A JP H03149829 A JPH03149829 A JP H03149829A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- slit
- corners
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract 3
- 229910052782 aluminium Inorganic materials 0.000 claims abstract 3
- 230000005012 migration Effects 0.000 abstract description 8
- 238000013508 migration Methods 0.000 abstract description 8
- 102100027340 Slit homolog 2 protein Human genes 0.000 abstract description 2
- 101710133576 Slit homolog 2 protein Proteins 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＡＬ多層配線構造の半導体装置におけるスト
レスマイグレーションに対して強靭な構造を有する構造
を提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention provides a structure that is strong against stress migration in a semiconductor device having an AL multilayer wiring structure.
［従来の技術］
半導体装置の高密度集積化にともないＡＬ配線Ｊの多層
化が標準的に行なわれるようになってきた。ところが、
配線の多層化によりストレスマイグレーションという新
しい問題が発生してきた。[Prior Art] With the increase in the density of integration of semiconductor devices, multi-layering of AL wiring J has become standard practice. However,
A new problem called stress migration has arisen due to multilayer wiring.
ストレスマイグレーションは、主にモールドパッケージ
を行なう製品に顕著にみられるが、実際には製造の過程
で起きている。第２図［ＡＬＺ層配線を例に説明する。Stress migration is mainly seen in products that undergo mold packaging, but it actually occurs during the manufacturing process. FIG. 2 [Explanation will be given by taking ALZ layer wiring as an example.
下層ＡＬ配線層２仕に、層間絶縁膜２２が形成されＶ工
Ａホールを介して下層ＡＬ配線層２１と接続された上層
ＡＬ配線層２５があり、保護膜としてパシベーション涙
２４で覆われた構造の半導体装置では、これらの製造工
程特に上層ＡＬ配線層の形成以降の工程ＫＭける熱処理
で、第２図の矢印で示したような圧縮応力や引っ張り応
力などによるストレスが上層ＡＬ配置８２５．下ＭＡＬ
配線２１に加わる。この場合特に下層配線２３には大き
なストレスが加わるため通常ストレスマイグレーション
は、この下層配線２１に生じることが多い。第５図にそ
の°例を示す。下層配線層２１の進行方向に垂直に発生
しているノツチ２５が、ストレスマイグレーシーａｙが
起きているところである。An interlayer insulating film 22 is formed on the lower AL wiring layer 2, and there is an upper AL wiring layer 25 connected to the lower AL wiring layer 21 via the V-hole A hole, and the structure is covered with a passivation tear 24 as a protective film. In this semiconductor device, stress due to compressive stress, tensile stress, etc., as shown by the arrows in FIG. Lower MAL
It is added to the wiring 21. In this case, since a large stress is particularly applied to the lower layer wiring 23, stress migration usually occurs in the lower layer wiring 21 in many cases. An example is shown in Figure 5. The notch 25, which is generated perpendicularly to the direction of movement of the lower wiring layer 21, is where stress migration racy ay occurs.
［発明が解決しようとする課題］
そこで本発明では第Ｓ図の様なストレスにより起きるス
トレスマイグレージレが顕著に起きる半導体装置の四隅
のコーナー部のストレスを緩和する配線構造を提供する
ものである。[Problems to be Solved by the Invention] Therefore, the present invention provides a wiring structure that alleviates stress at the four corners of a semiconductor device where stress migration lag caused by stress as shown in FIG. .
［課題を解決するための手段］
下層配線層が受けるストレｉを緩和する方法として下層
配線層の一部にスリットを設ける。[Means for Solving the Problems] A slit is provided in a part of the lower wiring layer as a method of alleviating the strain i that the lower wiring layer receives.
［実施例］
第１図に、本発明の実施例を示す。これは半導体装
置の四隅の部分を現わしている。１は下層ＡＬ配線層で
あり、通常この下層ＡＬ配線層上に上層ＡＬ配線層が平
行に形成されていることが多い。そのため下層ＡＬ配線
層に多くのノツチが発生し易く信頼性上問題があった。[Example] FIG. 1 shows an example of the present invention. This shows the four corners of the semiconductor device. 1 is a lower AL wiring layer, and an upper AL wiring layer is usually formed in parallel on this lower AL wiring layer. Therefore, many notches are likely to occur in the lower AL wiring layer, resulting in reliability problems.
また、半導体装置の四隅には特にモールドパッケージ実
施時に応力が集中するため工夫が必要である。そこで本
発明ではこれらのストレスを緩和する方法として下層ム
Ｌ配線にスリット２を形成している。この場合上ＭｉＡ
Ｌ配線からのストレスとモールドパッケージからのスト
レス両方からのストレスに効果があるようＫこのスリッ
ト２は半導体装置の中心方向に向いた方向に形成した。Furthermore, since stress is concentrated particularly at the four corners of the semiconductor device when mold packaging is performed, special measures are required. Therefore, in the present invention, as a method of alleviating these stresses, slits 2 are formed in the lower layer wiring. In this case upper MiA
The slit 2 was formed in the direction toward the center of the semiconductor device so as to be effective against stress from both the L wiring and the mold package.
、スリット幅としては１．５〜５ミクロン、スリット長
は下層ＡＬ配線幅の５分の１〜２分の１が良好であった
。The slit width was preferably 1.5 to 5 microns, and the slit length was preferably 1/5 to 1/2 of the lower layer AL wiring width.
［発明の効果］
このようＫろリットを下層ムＬ配線内に設けることによ
り下層＾Ｌ配線が受ける色々な応力、歪をスリット内に
逃がすことができる。そのため従来多く発生したノツチ
、更にモールドパッケージに起きる半導体装置４隅４へ
のストレスに対してもＡＬ配線が変形、縦線することも
な（たいへん良好な多層配線構造の半導体装置を形成す
ることができた。[Effects of the Invention] By providing the K slit in the lower layer wiring, various stresses and strains that the lower layer L wiring receives can be released into the slit. Therefore, the AL wiring does not deform or form vertical lines even when there are notches that occur in the past, and stress on the four corners 4 of the semiconductor device that occurs in mold packages (this makes it possible to form semiconductor devices with very good multilayer wiring structures). did it.
第１図が本発明の実施例を示す図であり、１が下層ＡＬ
配線で２がその中に形成したスリットである。
第２図がＡＬＺ層配−構迫の断面図である。第５図がス
トレスマイグレーションの一例を示ス図である。
、以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三部（他１名）／３．朴ｋがち
ド ・吃、半港休裟１箇１ａFIG. 1 is a diagram showing an embodiment of the present invention, in which 1 is a lower layer AL.
2 is the slit formed in the wiring. FIG. 2 is a sectional view of the ALZ layer arrangement. FIG. 5 is a diagram showing an example of stress migration. , Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) / 3. Park k chido ・吃、half port holiday 1 article 1a
Claims (1)
て、その半導体装置の四つのコーナー部の下層配線が、
該半導体装置の中心方向にスリット構造を有することを
特徴とする半導体装置。In a semiconductor device having two or more layers of aluminum multilayer wiring, the lower layer wiring at the four corners of the semiconductor device is
A semiconductor device characterized by having a slit structure toward the center of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28947189A JPH03149829A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28947189A JPH03149829A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03149829A true JPH03149829A (en) | 1991-06-26 |
Family
ID=17743708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28947189A Pending JPH03149829A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03149829A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763936A (en) * | 1995-04-27 | 1998-06-09 | Yamaha Corporation | Semiconductor chip capable of supressing cracks in insulating layer |
-
1989
- 1989-11-07 JP JP28947189A patent/JPH03149829A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763936A (en) * | 1995-04-27 | 1998-06-09 | Yamaha Corporation | Semiconductor chip capable of supressing cracks in insulating layer |
| US5885857A (en) * | 1995-04-27 | 1999-03-23 | Yamaha Corporation | Semiconductor chip capable of suppressing cracks in the insulating layer |
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