JPH0314261A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0314261A JPH0314261A JP1151271A JP15127189A JPH0314261A JP H0314261 A JPH0314261 A JP H0314261A JP 1151271 A JP1151271 A JP 1151271A JP 15127189 A JP15127189 A JP 15127189A JP H0314261 A JPH0314261 A JP H0314261A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrate
- chip
- metal cap
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000001681 protective effect Effects 0.000 claims description 10
- 238000007789 sealing Methods 0.000 abstract description 5
- 230000017525 heat dissipation Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、ＩＣチップを搭載し、［も・１脂封止された
［Ｃパソリーシにより＋１４成された１′ 導体装置に
関し、
耐湿性と放熱性とを合わせ持ったＩＣのパンケージを提
供することを目的とし、
ピン８を設けた基板１と、
該基板ｌの面上であって、該リートピン８を設けた面上
ル：１、反対の面上に設ｉ）たチップ２と、該チップ２
の表面に設りた保護Ｉり３と、該基板Ｉの該チップ２側
の面トてあって、該チップ２の周りに設りられた壁１１
と、
第１の面か該保護膜３と接し、第２の面が該壁１１と接
しているように設りられた第１の金属ギ中ノブ４と、
該第１の金属−１−トップ４に接し、該４％ｌ）反１を
包めこむ第２の金属キャップ５とを有し、該金属＝１−
千ップ４と壁１１との間を樹脂４：・１止した第１の樹
脂封止領域と、該Ｗ１反２と該ダム４１との間を樹脂封
止した第２の樹脂目止領域とをイするように構成する。[Detailed Description of the Invention] [Summary] The present invention relates to a 1' conductor device mounted with an IC chip and sealed with 1' resin, which has moisture resistance and heat dissipation properties. For the purpose of providing a pan-cage for ICs, a board 1 is provided with pins 8, and a board 1 is provided on the surface of the board 1 with pins 8 provided, and a board 1 is provided on the opposite surface. i) chip 2 and chip 2
A protective wall 3 provided on the surface of the substrate I and a wall 11 provided around the chip 2 on the side of the chip 2 of the substrate I.
and a first metal inner knob 4 provided such that a first surface is in contact with the protective film 3 and a second surface is in contact with the wall 11, and the first metal -1- a second metal cap 5 in contact with the top 4 and enclosing the 4% l) anti-corrosion 1;
A first resin-sealed area where the space between the tip 4 and the wall 11 is sealed with resin 4:1, and a second resin-sealed area where the space between the W1 and the dam 41 is sealed with resin. Configure it to match.
本発明は、ＩＣチップを搭載し、樹脂封止されたＩＣパ
ッケージにより構成された半導体装置に関する。The present invention relates to a semiconductor device including an IC package mounted with an IC chip and sealed with resin.
第２図は、従来のプラスチックピングリフｌアレイ （
ＰＣＡ）型パッケージの構成を示す断面図である。Figure 2 shows a conventional plastic pin glyph l array (
FIG. 2 is a cross-sectional view showing the configuration of a PCA type package.
図のように、ピン２５か下向きに形成されたカラスエポ
キシ基板２１上に、チップ２２を搭載して樹脂２４によ
って封止し、金属キャップ２３を被せたものである。Ｉ
ＭＩ Ｉｌｒ ２ ／ｌ Ｌ；ｌ、予めチップ２２０）
周りに形成されたダｉ−２Ｅｉの内側に流し込んで固め
て形成する。As shown in the figure, a chip 22 is mounted on a glass epoxy substrate 21 with pins 25 facing downward, sealed with resin 24, and covered with a metal cap 23. I
MI Ilr 2 /l L;l, tip 220 in advance)
It is poured into the inside of the die i-2Ei formed around it and hardened to form it.
ところが、第２図のような＋７４成のパンケージでは、
図示したように金属キャップ２３と基板２１との隙間へ
から外界の水分が浸入し、樹脂２４を伝って千ノブ２２
に到達し７、Ｉｃの篩１湿性を、７ｔｊ化させてしまう
。これは、樹脂用＋１−領域か金属キャップ２３内たＬ
Ｊで、チップ２２と外界との距離か短いため、比較的容
易に千ノブ２２まで水分が到達してし月；うたぬである
。However, in the +74 composition pan cage as shown in Figure 2,
As shown in the figure, moisture from the outside enters into the gap between the metal cap 23 and the substrate 21, passes through the resin 24, and enters the 1000-knob 22.
7, the sieve 1 wetness of Ic becomes 7tj. This is the +1- area for the resin or the L inside the metal cap 23.
In J, the distance between the chip 22 and the outside world is short, so moisture can reach the Sennobu 22 relatively easily.
また、チップ２２と金１１１；キャップ２３との間にあ
るのは樹脂２４なので、チップ２２で発生した熱が金属
−１−中ノブ２３まで伝導しにくく、放熱性が悪かった
。Further, since the resin 24 is between the chip 22 and the gold 111 and the cap 23, it is difficult for the heat generated in the chip 22 to be conducted to the metal 1-middle knob 23, resulting in poor heat dissipation.
そごで、耐湿性を向干させたパンケージとして、第Ｎ３
図に示されるようなパッケージがある。As a pan cage with improved moisture resistance, No.
There is a package as shown in the figure.
これ心：１、第２図′ζホしたパッケージの周りを、さ
らにもう−１ｌｒＣ４ろ・ｊ脂２７て覆って、金属−１
−ヤング２８を被−１たものである。樹脂をニー屯にす
ることにより、樹脂封止領域が広くなって、水分の浸入
経路が第２図に示したパンケージに比べて長くなり、ま
た２重に封止され′ζいるので、耐湿性が向上する。This is what I thought: 1. In Figure 2, cover the package with another layer of -1lrC4 filter 27, and add metal -1.
-Young 28. By making the resin knee-tight, the resin sealing area becomes wider and the moisture infiltration path is longer than that of the pan cage shown in Figure 2. Also, since it is double sealed, moisture resistance is improved. will improve.
また、放熱性を向トさせたパッケージとしで、第４図に
示されるようなパッケージがある。There is also a package with improved heat dissipation, as shown in FIG. 4.
これは、ピン２５か形成されている側の基板２１の下側
に千ツブ２２を形成し、基板２１に埋めこまれた金属キ
ャップ２９を介して放熱フィン３０に熱を逃がすもので
ある。This is to form a protrusion 22 on the lower side of the substrate 21 on the side where the pins 25 are formed, and to release heat to the radiation fins 30 via a metal cap 29 embedded in the substrate 21.
このように、チップ２２を基板２１の下側に形成するの
ば、ヂンブ２２の表面に直接金属ギャップ２９が接触す
ると、チップ２２が金属ギャップ２９から直接機械的シ
ョック等を受け、チップ２２の表面に形成された素子が
破損してしまうからである。In this way, when the chip 22 is formed on the lower side of the substrate 21, when the metal gap 29 comes into direct contact with the surface of the die 22, the chip 22 receives a direct mechanical shock from the metal gap 29, and the surface of the chip 22 is damaged. This is because the elements formed in this way will be damaged.
（発明が解決しようとする課題〕
ところか、第３図のような構成では、２重の樹脂の中に
チップ２２か埋込まれた形になるので、第２し１に示し
たバノノノーシに比べ、放熱性が悪くス（っでしまう問
題かあ、、た。(Problem to be Solved by the Invention) However, in the configuration shown in Figure 3, the chip 22 is embedded in a double layer of resin, so compared to the Banononoshi shown in Part 2 and 1. Is there a problem with the heat dissipation being poor?
また、第４図の、Ｊ、うな１１１４成では、チップ２１
がピン２５と同し基板２１の下側に形成されているため
、ピン２５か邪＋ｒｔになって、樹脂」′・１止領域を
第３図で示したパ、ノノ−−ジのように広く形成するこ
とか−（さｌ（かった。（ｊｆｇ 、っ′（、耐湿性に
おいて第２図で示した４’ｆ７ｉ成のパッケージとほと
んど変わらないものとなってし、まう問題かあ、った。In addition, in the case of J, eel 1114 formation in Fig. 4, the chip 21
Since the pin 25 and the pin 25 are formed on the lower side of the substrate 21, the pin 25 becomes the wrong +rt, and the resin '' 1 stop area is as shown in Fig. 3. I wonder if I should make it wider.(jfg, っ'(,) In terms of moisture resistance, it would be almost the same as the 4'F7I package shown in Figure 2, which is a problem. It was.
この３１、うに、第３し１のような構成のパンゲージに
して、耐湿性を向−にさ・ｌようとすると放熱性が悪く
なり、第４図のような構成のパッケージにし−（、放熱
性を向−にさ−ｌようとすると耐湿性が悪くなるといっ
た、お互い相いれない問題があった。If you try to make a pan gauge with the structure shown in Figure 3 and 1 and try to improve moisture resistance, the heat dissipation will be poor, so you should use a package with the structure shown in Figure 4. Attempts to improve the moisture resistance of the material have problems that are mutually exclusive, such as poor moisture resistance.
従って本発明は、耐湿性と放熱性とを合わせ持ったＩＣ
のパッケージを提供することを目的とする。Therefore, the present invention provides an IC that has both moisture resistance and heat dissipation.
The purpose is to provide a package of
〔詞！題を解決するための手段］
（ｊ
上記「１的を達成するために本発明シ；１、ピン８を設
ｉｔ ；７．：、！吉１反１と、該基板１の面上であっ
て、該リートピン８を設りた面とは反対の面−ｌ−に設
りたチップ２と、該チップ２の表面に設ＬＪた保護１１
り３と、該基板１の該チップ２側の面上であって、該千
ノブ２の周りに設けられた壁１１と、
第１の面が該保護膜３と接し、第２の面か該壁１１と接
しているように設りられた第１の金属−１−ヤソブ４と
、
該第１の金属キャップ４に接し、該基板１を包みこむ第
２の金属キャップ５とを有し、該金属キャップ４と壁１
１との間を樹脂封止した第１の樹脂封止領域と、該基板
２と該ダム１■との間を樹脂封止した第２の樹脂：ｌ）
Ｊ正領域とを有ずろように半導体装置のパッケージを構
成する。[Lyrics! Means for Solving the Problem] The chip 2 provided on the surface -l- opposite to the surface provided with the leet pin 8, and the protection 11 provided on the surface of the chip 2.
3, a wall 11 provided on the surface of the substrate 1 on the chip 2 side and around the knob 2, a first surface of which is in contact with the protective film 3, and a second surface of It has a first metal cap 4 provided so as to be in contact with the wall 11, and a second metal cap 5 that is in contact with the first metal cap 4 and wraps around the substrate 1. , the metal cap 4 and the wall 1
A first resin-sealed region that resin-seals between the substrate 2 and the dam 1; and a second resin that resin-seals the space between the substrate 2 and the dam 1: l)
A semiconductor device package is configured to have a J positive region.
本発明では第１図に示すように、放熱フィン９に接続さ
れた金属キャップ５を保護膜３を介して基板１０）−１
−側のチップ２と接ずろようにし”（いるので、放熱性
を向にさ一口ることができる。金属キャップ５υ、ｌ、
保；（（膜３を介してチップ２と接しているので、千ノ
ブ２の表面の素子に加わる（；（械的ソＥｌンクＩ３１
和らげられ、素子が破損することはない
また、’ｆ−ツブ２が、ピン８か形成されたのとは反対
側の千ツブ２の−１−側に形成されているので、第３図
に示した＋１へ成のパッケージと同様に、樹脂↑、ｊ市
領域を広くとることができ、耐湿性を向」二さ−Ｕるこ
とかできろ。In the present invention, as shown in FIG.
The metal cap 5υ, l,
((Since it is in contact with the chip 2 through the membrane 3, it is applied to the elements on the surface of the knob 2.
In addition, since the 'f-tube 2 is formed on the -1- side of the 100-tube 2, which is opposite to where the pin 8 is formed, as shown in Fig. 3. Similar to the +1 package shown above, the resin area can be expanded and moisture resistance can be improved.
従って、第１図のような構成のＩＣパ、ケージは、放熱
性と耐湿性とが両方とも優れている。Therefore, the IC package having the structure as shown in FIG. 1 has excellent heat dissipation and moisture resistance.
（実施例〕
第１図（ａ）、（ｂ）に、本発明の一実施例のＩＣパッ
ケージの断面図を示す。（ａ）は、ＩＣパッケージの断
面図を示し、（）））は、ＩＣパッケージの」二面図を
示す。(Example) Figures 1 (a) and (b) show cross-sectional views of an IC package according to an example of the present invention. (a) shows a cross-sectional view of the IC package, and ())) 2 shows a two-sided view of the IC package.
同に示したように本発明では、カラスエポキシ基板１の
下側にピン８を設ＤＪ、その反対側の基板１の」−例に
チップ２を搭載する。千ツブ２の表面には、厚さ５μｍ
のポリイミドの保護膜３か形成され、ごの保護膜３に接
して企１ｉ１キートンプ４がチップ２」二に設けられて
いる。As shown in the figure, in the present invention, pins 8 are provided on the lower side of the glass epoxy substrate 1, and the chip 2 is mounted on the opposite side of the substrate 1. The surface of Sentsubu 2 has a thickness of 5 μm.
A polyimide protective film 3 is formed, and a keypad 4 is provided on the chip 2 in contact with the protective film 3.
金属キャップ４の下面は、ワイヤ１０かチップ２に接続
された領域以外で、なるべく広い■１１積てチップ２と
接するようする。また、その−１−面は、チップ２の周
囲を囲むように基板１に接着されたガラスエポキシ製の
ダム１１に接するようにずろ。The lower surface of the metal cap 4 should be in contact with the stacked chips 2 as wide as possible except in the area where the wires 10 or the chips 2 are connected. Further, the -1- plane is shifted so as to be in contact with a dam 11 made of glass epoxy that is bonded to the substrate 1 so as to surround the periphery of the chip 2.
そして、ダム１１と金属キャップ４との間に形成された
樹脂６て、第１の樹脂封止１ｉＪ（域を形成する。Then, the resin 6 formed between the dam 11 and the metal cap 4 forms a first resin sealing area 1iJ.
ダム１１が金属キャップ４を支える形になるので、チッ
プ２の表面に過大な応力が加わることかなく、水分の浸
入も防くことができる。なお、ダム１１の形状は、千ツ
ブ２の周囲を囲む環状の他に、支柱状にしてもよい。Since the dam 11 supports the metal cap 4, excessive stress is not applied to the surface of the chip 2, and moisture can be prevented from entering. In addition, the shape of the dam 11 may be in the form of a pillar instead of a ring surrounding the periphery of the tube 2.
さらに、この第１の樹脂封止領域の外側で、金属キャッ
プ４に接する金属キャップ５．ダＪ、１１及び基板１の
間に樹脂７を形成し、第２の樹脂］：・１１Ｆ領域を形
成ずろ。Furthermore, a metal cap 5. which is in contact with the metal cap 4 outside this first resin sealing area. Form the resin 7 between the resin 11 and the substrate 1, and form the second resin]:-11F region.
ごのように、２重の楯・１脂月十領域によって、外Ｗか
らの水分の浸入を防いでいる。As shown in the figure, a double shield and one fat moon area prevent moisture from entering from outside.
また、金属キャップ５の七には放熱フィンが設ＧＪられ
、チップ２で発生した熱を２つの金属キャップを介して
伝導さ１！放熱し７ていイ）。チップ２と金属キャップ
４との間に＆Ｊ：、 ＩＩｓ！厚５１ｔｍのポリイミド
のイ呆護１１％％ ３かあるか、月當Ｑこン）すいもの
なので熱伝導にはほとんど影口し７ない。しかし、金属
キャップ４からの機械的ショックを和らげるのにば１−
分な厚さである。な、幻、圓示しなかったが、放熱フィ
ンにＧ、１送風手段等により風を送り、効率良く放熱フ
ィンの熱を逃がし２やる。In addition, a heat dissipation fin is provided at 7 of the metal cap 5, and the heat generated in the chip 2 is conducted through the two metal caps 1! It dissipates heat (7). Between tip 2 and metal cap 4 &J:, IIs! The thickness of polyimide with a thickness of 51 tm is 11%.It has a monthly cost of 11%.Since it is a thin material, it has little effect on heat conduction. However, in order to soften the mechanical shock from the metal cap 4, 1-
It is thick enough. Well, I didn't show it in detail, but I send air to the heat sink fins using a blower, etc. to efficiently dissipate the heat from the heat sink fins.
次に以」二のようなパッケージを形成する方法を説明す
る。Next, a method for forming the following package will be explained.
まず、ピン８を下側に形成した基板１の上側の面に、保
護膜３を形成したチップ２をダイ心］りする。そして、
このチップ２を囲むように、チップ２の周囲の基板２十
に、ガラスエ、１沁１−シによリタムとよばれる壁を形
成する。ダム］］とチンプ２との間は樹脂６で充１眞さ
れるのだが、樹脂６は、予めこの空間にはまる形に仮硬
化させたものを埋込む。First, the chip 2 on which the protective film 3 is formed is mounted on the upper surface of the substrate 1 on which the pins 8 are formed. and,
A wall called a lithium is formed on the substrate 20 around the chip 2 by using a glass layer so as to surround the chip 2. The space between the dam] and the chimp 2 is filled with resin 6, and the resin 6 is temporarily hardened in advance to fit into this space.
次に、樹脂６で挟まれるテンプ２上に金属キャップ４を
載置し、加熱して樹脂を本硬化させろ。Next, place the metal cap 4 on the balance 2 sandwiched between the resin 6 and heat it to fully harden the resin.
加熱により樹脂は、まんべんなく隙間に広がり、ダム１
１と金属キャップ４とチップ２と基板１とで形成されろ
空間を封止し、第１の樹脂１．・１止領域が形成される
。Due to heating, the resin spreads evenly into the gap, and dam 1
1, the metal cap 4, the chip 2, and the substrate 1. The first resin 1. - A one stop area is formed.
この後、同様にして金属キャップ５とダム１１と基板１
とで形成される領域に、仮硬化させた樹脂７を充填した
後、金属キャップ５をかふ・Ｕて加熱して樹脂７．を硬
化させ、第２の樹脂封止領域を形成する。なお、放熱フ
ィンは、金属キャップ５に予め付しｊておく。After that, the metal cap 5, the dam 11 and the substrate 1 are placed in the same manner.
After filling the area formed by the temporarily hardened resin 7, the metal cap 5 is heated with a cuff to form the resin 7. is cured to form a second resin-sealed region. Note that the heat radiation fins are attached to the metal cap 5 in advance.
以上のように形成したパッケージは、樹脂封止領域が２
重になっているため、外界から水分が浸入しにくく、か
つチップが２つの金属キャップを介して放熱フィンに接
しているので放熱性が良い。The package formed as described above has two resin-sealed areas.
Because they overlap, it is difficult for moisture to enter from the outside world, and since the chip is in contact with the heat dissipation fins via two metal caps, it has good heat dissipation.
以上説明した。１、うに本発明によれば、樹脂封止領域
を２重に形成しているので、耐湿性に優れ、かつチップ
で発生した熱を金属ギャップを介して逃がしてやるので
、放熱性がよく、耐湿性と放熱性の両方で優れた効果を
奏する。This has been explained above. 1. According to the present invention, the resin sealing region is formed in two layers, so it has excellent moisture resistance, and the heat generated in the chip is released through the metal gap, so it has good heat dissipation. It has excellent effects in both moisture resistance and heat dissipation.
従って、本発明は耐湿性と放熱性に優れたＩＣを提供す
ることができ、ＩＣの信頼性を向上させるのに寄与する
とごろが大きい。Therefore, the present invention can provide an IC with excellent moisture resistance and heat dissipation, and can greatly contribute to improving the reliability of the IC.
第１図（ａ）、（ｂ）は、本発明の一実施例のパンケー
ジの断面図及び」−面ばてあり、第２図〜第４図は、従
来のパッケージの断面図である。
１・・・基板 ２・・・チップ３・・・保護膜
４・・・金属キャップ５・・金属キャップ ６
・・・樹脂
７・・・樹脂 ８・・ピン
９・・・放熱フィン １０・・・ワイヤ１
２
１１・・・ダムFIGS. 1(a) and 1(b) are cross-sectional views of a pan cage according to an embodiment of the present invention, and FIGS. 2-4 are cross-sectional views of a conventional package. 1...Substrate 2...Chip 3...Protective film 4...Metal cap 5...Metal cap 6
...Resin 7...Resin 8...Pin 9...Radiating fin 10...Wire 1 2 11...Dam
Claims (1)
けた面とは反対の面上に設けたチップ（２）と、 該チップ（２）の表面に設けた保護膜（３）と、該基板
（１）の該チップ（２）側の面上であって、該チップ（
２）の周りに設けられた壁（１１）と、 第１の面が該保護膜（３）と接し、第２の面が該壁（１
１）と接しているように設けられた第１の金属キャップ
（４）と、 該第１の金属キャップ（４）に接し、該基板（１）を包
みこむ第２の金属キャップ（５）とを有し、 該金属キャップ（４）と壁（１１）との間を樹脂封止し
た第１の樹脂封止領域と、該基板（２）と該ダム（１１
）との間を樹脂封止した第２の樹脂封止領域とを有する
ことを特徴とする半導体装置。[Claims] A substrate (1) provided with pins (8), and a chip provided on the surface of the substrate (1) opposite to the surface provided with the lead pins (8). (2), a protective film (3) provided on the surface of the chip (2), and a protective film (3) provided on the surface of the substrate (1) on the chip (2) side;
a wall (11) provided around the wall (11), a first surface of which is in contact with the protective film (3), and a second surface of which is in contact with the wall (11);
1); a second metal cap (5) that is in contact with the first metal cap (4) and wraps around the substrate (1); a first resin-sealed region in which a space between the metal cap (4) and the wall (11) is sealed with resin, and a region between the substrate (2) and the dam (11);
) and a second resin-sealed region sealed with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151271A JPH0314261A (en) | 1989-06-13 | 1989-06-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1151271A JPH0314261A (en) | 1989-06-13 | 1989-06-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0314261A true JPH0314261A (en) | 1991-01-22 |
Family
ID=15515023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1151271A Pending JPH0314261A (en) | 1989-06-13 | 1989-06-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0314261A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0528291A2 (en) * | 1991-08-08 | 1993-02-24 | Sumitomo Electric Industries, Limited | Semiconductor chip module and method for manufacturing the same |
| JPH06177288A (en) * | 1992-12-03 | 1994-06-24 | Nec Corp | Semiconductor device |
| US5455457A (en) * | 1990-11-27 | 1995-10-03 | Nec Corporation | Package for semiconductor elements having thermal dissipation means |
-
1989
- 1989-06-13 JP JP1151271A patent/JPH0314261A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5455457A (en) * | 1990-11-27 | 1995-10-03 | Nec Corporation | Package for semiconductor elements having thermal dissipation means |
| EP0528291A2 (en) * | 1991-08-08 | 1993-02-24 | Sumitomo Electric Industries, Limited | Semiconductor chip module and method for manufacturing the same |
| EP0528291A3 (en) * | 1991-08-08 | 1994-05-11 | Sumitomo Electric Industries | Semiconductor chip module and method for manufacturing the same |
| US5525835A (en) * | 1991-08-08 | 1996-06-11 | Sumitomo Electric Industries, Ltd. | Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element |
| JPH06177288A (en) * | 1992-12-03 | 1994-06-24 | Nec Corp | Semiconductor device |
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