JPH05226339A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPH05226339A
JPH05226339A JP4012649A JP1264992A JPH05226339A JP H05226339 A JPH05226339 A JP H05226339A JP 4012649 A JP4012649 A JP 4012649A JP 1264992 A JP1264992 A JP 1264992A JP H05226339 A JPH05226339 A JP H05226339A
Authority
JP
Japan
Prior art keywords
bonding pad
resin
film
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4012649A
Other languages
Japanese (ja)
Inventor
Junji Kamioka
純二 上岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4012649A priority Critical patent/JPH05226339A/en
Publication of JPH05226339A publication Critical patent/JPH05226339A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a resin sealed semiconductor device which is highly resistant to resin stress caused by temperature change, by arranging a dummy pattern composed of a conducting film of the same layer as a bonding pad. CONSTITUTION:On a semiconductor substrate 4, an insulating film 5 is laminated. Thereon an aluminum film of 1.1mum in thickness for forming a bonding pad 1 and a dummy pattern 3a-1, 3a-2 is laminated. The upper part of the aluminum film is coated with a cover insulating film 6 of 1.3mum in thickness. The cover insulating film 6 which covers the aluminum film surrounding the periphery of the bonding pad has a structure whose section forms arches having an aspect ratio of 1: 2, so that the resistance to resin stress is large as compared with the outer peripheral part of the conventional bonding pad. Hence the function to protect a passivation film (cover insulating film) in the outer peripheral part of the bonding pad from resin stress is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は樹脂封止半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.

【０００２】[0002]

【従来の技術】従来の樹脂封止半導体装置では図３に示
すようにアイランド７と、これにマウントされた半導体
チップ８と、リード９と、半導体チップ８とリードとを
電気的に接続するボンディングワイヤ１０とこれらを封
止する樹脂１１とを有し、半導体チップ８にはボンディ
ングワイヤ１０をボンディングするためのボンディング
パッド１が設けてある。2. Description of the Related Art In a conventional resin-sealed semiconductor device, as shown in FIG. 3, an island 7, a semiconductor chip 8 mounted on the island 7, a lead 9, and a bonding for electrically connecting the semiconductor chip 8 and the lead to each other. A bonding pad 1 for bonding the bonding wire 10 is provided on the semiconductor chip 8 having a wire 10 and a resin 11 for sealing them.

【０００３】ボンディングパッド１は、通常、半導体集
積回路で用いられる最上部の金属配線層であるアルミニ
ウム膜で形成され一辺が１００μｍないし１５０μｍの
正方形をなす。またパッシベーション膜（カバー絶縁
膜）はチップ全体を覆っており、ボンディングパッドの
箇所は図４に示すようにアルミニウム膜の内のり数μｍ
の大きさでスルーホール２が設けてあり、そこにボンデ
ィングワイヤをボンディングする。The bonding pad 1 is usually formed of an aluminum film which is the uppermost metal wiring layer used in a semiconductor integrated circuit, and has a square shape of 100 μm to 150 μm on a side. Further, the passivation film (cover insulating film) covers the entire chip, and the bonding pad is located within a few μm of the aluminum film as shown in FIG.
There is a through hole 2 having a size of, and a bonding wire is bonded thereto.

【０００４】[0004]

【発明が解決しようとする課題】この従来の樹脂封止半
導体装置では、温度変化による伸縮率がチップと封止樹
脂とで異なり、封止樹脂の伸縮率の方が大きいために、
大幅な温度変化にさらされた場合、チップ表面を封止樹
脂が移動し、ずれ応力がチップ表面に加わりパッシベー
ション膜のクラックやアルミニウム配線のずれなどが生
じる。特にボンディングパッド部はチップ周辺部に位置
するため封止樹脂の応力が強く加わり且つ、形状的には
一辺が１００μｍないし１５０μｍの正方形となってい
るのでこのアルミニウム膜の側壁をおおうパッシベーシ
ョン膜は構造的に、他の細かくパターニングされたアル
ミニウム配線部の上部をおおうパッシベーション膜に比
べて応力に耐して弱くなっている。In this conventional resin-encapsulated semiconductor device, the expansion and contraction rate due to temperature change differs between the chip and the encapsulation resin, and the expansion and contraction rate of the encapsulation resin is larger.
When exposed to a large temperature change, the encapsulating resin moves on the surface of the chip, and shear stress is applied to the surface of the chip, causing cracks in the passivation film and displacement of aluminum wiring. In particular, since the bonding pad portion is located in the peripheral portion of the chip, the stress of the sealing resin is strongly applied and the shape is a square with one side of 100 μm to 150 μm. Therefore, the passivation film covering the side wall of this aluminum film is structurally structured. In addition, it is more resistant to stress and weaker than the passivation film covering the upper portion of the other finely patterned aluminum wiring portion.

【０００５】このように、ボンディングパッド部は温度
変化にさらされた場合、パッシベーション膜クラックが
発生し易いという問題点があった。As described above, when the bonding pad portion is exposed to a temperature change, there is a problem that a passivation film crack is likely to occur.

【０００６】[0006]

【課題を解決するための手段】本発明の樹脂封止半導体
装置は、ボンディングパッドおよび前記ボンディングパ
ッドの周辺部を含んで半導体チップの表面を被覆するカ
バー絶縁膜を有し、前記ボンディングパッドと同層の導
電膜からなるダミーパターンが前記ボンディングパッド
の周囲に設けられているというものである。A resin-sealed semiconductor device of the present invention has a bonding pad and a cover insulating film covering a surface of a semiconductor chip including a peripheral portion of the bonding pad, and the same as the bonding pad. A dummy pattern made of a conductive film of a layer is provided around the bonding pad.

【０００７】[0007]

【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）は本発明の第１の実施例を示すボンディ
ングパッド部の平面図である。The present invention will be described below with reference to the drawings. FIG. 1A is a plan view of a bonding pad portion showing a first embodiment of the present invention.

【０００８】ボンディングパッド１は一辺１２０μｍの
正方形をしたアルミニウム膜で形成されカバー絶縁膜に
設けられたスルーホール２がボンディングパッド１の内
側１０μｍの大きさに穿設されている。ボンディングパ
ッド１の外縁部から２μｍの間隔をおいて幅２μｍのア
ルミニウム膜からなる細帯状のダミーパターン３ａ−
１，３ａ−２が二重にボンディングパッド１を囲む形に
設けられている。The bonding pad 1 is formed of a square aluminum film having a side length of 120 μm, and a through hole 2 provided in the cover insulating film is formed in the bonding pad 1 so as to have a size of 10 μm. A strip-shaped dummy pattern 3a-made of an aluminum film having a width of 2 μm at a distance of 2 μm from the outer edge of the bonding pad 1.
1, 3a-2 are provided so as to double surround the bonding pad 1.

【０００９】図１（ｂ）は図１（ａ）のＡ−Ａ線拡大断
面図である。半導体基板４上に絶縁膜５が積層されその
上部にボンディングパッド１及びダミーパターン３ａ−
１，３ａ−２を形成するアルミニウム膜が厚さ１．１μ
ｍで積層され更にその上部を厚さ１．３μｍのカバー絶
縁膜６が覆っている。ボンディングパッドの周囲を囲む
アルミニウム膜を覆っているカバー絶縁膜６の構造は断
面が縦横比約１：２のアーチ状になっているため、樹脂
の応力に対しては従来のボンディングパッドの外縁部に
比べ強固であり、ボンディングパッドの外縁部のパッシ
ベーション膜（カバー絶縁膜）を樹脂応力から保護する
働きをしている。FIG. 1 (b) is an enlarged sectional view taken along the line AA of FIG. 1 (a). The insulating film 5 is laminated on the semiconductor substrate 4, and the bonding pad 1 and the dummy pattern 3a- are formed on the insulating film 5.
The aluminum film forming 1,3a-2 has a thickness of 1.1 μm.
m, and the upper part thereof is covered with a cover insulating film 6 having a thickness of 1.3 μm. Since the structure of the cover insulating film 6 covering the aluminum film surrounding the bonding pad has an arch-shaped cross section with an aspect ratio of about 1: 2, the outer edge portion of the conventional bonding pad is against the stress of the resin. It is stronger than that of, and acts to protect the passivation film (cover insulating film) on the outer edge of the bonding pad from resin stress.

【００１０】図２は第２の実施例を示すボンディングパ
ッド部の平面図である。本実施例においてはボンディン
グパッド１の外周に櫛歯状にダミーパターン３ｂを設け
た形状となっている。この用な櫛歯状のアルミニウム膜
を覆うパッシベーション膜は第一の実施例と同じく樹脂
応力に対して強固な構造であり、ボンディングパッド１
の外縁部のパッシベーション膜クラックの発生を防ぐ効
果がある。FIG. 2 is a plan view of a bonding pad portion showing a second embodiment. In the present embodiment, the bonding pad 1 has a comb-shaped dummy pattern 3b on the outer periphery thereof. The passivation film covering the comb-shaped aluminum film for this purpose has a strong structure against the resin stress as in the first embodiment.
It is effective in preventing the generation of cracks in the passivation film at the outer edge of the.

【００１１】本実施例では第１の実施例に比べて更にダ
ミーパターンによる凹凸の密度を高くすることができる
ので、樹脂応力に対する強度がより強いものになる。In this embodiment, since the density of the unevenness due to the dummy pattern can be further increased as compared with the first embodiment, the strength against the resin stress becomes stronger.

【００１２】[0012]

【発明の効果】以上説明したように、本発明はボンディ
ングパッドの周囲にボンディングパッドと同層の導電膜
からなるダミーパターンを配置し、これを覆うパッシベ
ーション膜（カバー絶縁膜）に強固な構造を与えること
により従来、温度変化により生じる樹脂応力に対し脆弱
だったボンディングパッド外縁部のパッシベーション膜
を保護し、温度変化による樹脂応力に対し耐性の高い樹
脂封止半導体装置を供給することができる。As described above, according to the present invention, a dummy pattern made of a conductive film in the same layer as the bonding pad is arranged around the bonding pad, and the passivation film (cover insulating film) covering the dummy pattern has a strong structure. By applying the protective layer, it is possible to protect the passivation film on the outer edge of the bonding pad, which was conventionally vulnerable to the resin stress caused by the temperature change, and to supply the resin-sealed semiconductor device having high resistance to the resin stress caused by the temperature change.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例を示す平面図（図１
（ａ））および拡大断面図（図１（ｂ））である。FIG. 1 is a plan view showing a first embodiment of the present invention (see FIG.
It is (a)) and an expanded sectional view (FIG.1 (b)).

【図２】本発明の第２の実施例を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.

【図３】樹脂封止半導体装置を示す断面図である。FIG. 3 is a cross-sectional view showing a resin-sealed semiconductor device.

【図４】従来例を示す平面図である。FIG. 4 is a plan view showing a conventional example.

【符号の説明】[Explanation of symbols]

１ ボンディングパッド ２ スルーホール ３ａ−１，３ａ−２，３ｂ ダミーパターン ４ 半導体基板 ５ 絶縁膜 ６ カバー絶縁膜 ７ アイランド ８ 半導体チップ ９ リード １０ ボンディングワイヤ １１ 封止樹脂 1 Bonding Pad 2 Through Hole 3a-1, 3a-2, 3b Dummy Pattern 4 Semiconductor Substrate 5 Insulation Film 6 Cover Insulation Film 7 Island 8 Semiconductor Chip 9 Lead 10 Bonding Wire 11 Sealing Resin

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ボンディングパッドおよび前記ボンディ
ングパッドの周辺部を含んで半導体チップの表面を被覆
するカバー絶縁膜を有し、前記ボンディングパッドと同
相の導電膜からなるダミーパターンが前記ボンディング
パッドの周囲に設けられていることを特徴とする樹脂封
止半導体装置。1. A bonding insulating film and a cover insulating film covering a surface of a semiconductor chip including a peripheral portion of the bonding pad, and a dummy pattern made of a conductive film having the same phase as the bonding pad is provided around the bonding pad. A resin-encapsulated semiconductor device, which is provided. 【請求項２】 ダミーパターンがボンディングパッドの
周縁と平行に設けられている請求項１記載の樹脂封止半
導体装置。2. The resin-sealed semiconductor device according to claim 1, wherein the dummy pattern is provided in parallel with the peripheral edge of the bonding pad.
JP4012649A 1992-01-28 1992-01-28 Resin sealed semiconductor device Withdrawn JPH05226339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4012649A JPH05226339A (en) 1992-01-28 1992-01-28 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4012649A JPH05226339A (en) 1992-01-28 1992-01-28 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH05226339A true JPH05226339A (en) 1993-09-03

Family

ID=11811217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4012649A Withdrawn JPH05226339A (en) 1992-01-28 1992-01-28 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH05226339A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319883B1 (en) * 1999-03-16 2002-01-10 윤종용 Semiconductor device having dummy pattern around pad
US6614120B2 (en) * 2001-08-01 2003-09-02 Seiko Epson Corporation Semiconductor device
WO2005045931A2 (en) 2003-11-06 2005-05-19 Infineon Technologies Ag Semiconductor chip having flip-chip contacts and method for producing the same
JP2005142351A (en) * 2003-11-06 2005-06-02 Nec Electronics Corp Semiconductor device and its manufacturing method
JP2005142553A (en) * 2003-10-15 2005-06-02 Toshiba Corp Semiconductor device
JP2006303238A (en) * 2005-04-21 2006-11-02 Sharp Corp Semiconductor chip, manufacturing method thereof and semiconductor device
JP2007208209A (en) * 2006-02-06 2007-08-16 Fujitsu Ltd Semiconductor device and method for fabrication thereof
US7514790B2 (en) * 2005-06-02 2009-04-07 Seiko Epson Corporation Semiconductor device and method of manufacturing a semiconductor device
US20170005024A1 (en) * 2015-06-30 2017-01-05 Sii Semiconductor Corporation Semiconductor device
US9596767B2 (en) 2014-06-24 2017-03-14 Fujitsu Limited Electronic component, method of manufacturing electronic component, and electronic device
WO2019012854A1 (en) * 2017-07-13 2019-01-17 富士電機株式会社 Semiconductor device
DE102019200152B4 (en) 2018-01-22 2022-08-11 Globalfoundries U.S. Inc. BOND PADS WITH SURROUNDING CHARGE LINES AND PROCEDURES

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6384464B1 (en) 1999-03-16 2002-05-07 Samsung Electronics Co., Ltd. Integrated circuit device including dummy patterns surrounding pads
KR100319883B1 (en) * 1999-03-16 2002-01-10 윤종용 Semiconductor device having dummy pattern around pad
US6614120B2 (en) * 2001-08-01 2003-09-02 Seiko Epson Corporation Semiconductor device
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