JPH03132993A - Sense amplifier circuit - Google Patents
Sense amplifier circuitInfo
- Publication number
- JPH03132993A JPH03132993A JP1272008A JP27200889A JPH03132993A JP H03132993 A JPH03132993 A JP H03132993A JP 1272008 A JP1272008 A JP 1272008A JP 27200889 A JP27200889 A JP 27200889A JP H03132993 A JPH03132993 A JP H03132993A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- channel
- column selection
- power supply
- misfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 abstract description 18
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 18
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- Static Random-Access Memory (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はセンス増幅回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a sense amplifier circuit.
ＬＳＩを構成する回路素子の微細化と電源電圧の低下に
より、メモリセルから読み出される信号電圧は減少しつ
つある。それにもかかわらず、メモリアクセス時間の高
速化を図るためには、信号電圧を増幅するセンス増幅回
路の高速動作が必須条件となる。Due to miniaturization of circuit elements constituting LSIs and reduction in power supply voltage, the signal voltage read from memory cells is decreasing. Nevertheless, in order to speed up the memory access time, high-speed operation of the sense amplifier circuit that amplifies the signal voltage is an essential condition.
このセンス増幅を高速化するための回路として、例えば
１９８９年ＶＳＬ １回路シンポジウムの予稿集ｒ １
９ｇ９年、シンポジウム・イン・ブイエルニスアイ・サ
ーキット、ダイジェスト・オブ・テクニカル・ヘーパー
ズ（１９８９ＳＹＭＰＯ８ＩＵＭ ＯＮ ＶＳＬＩ Ｃ
ＩＲＣｔＪＩＴＳ、ＤＩＧＥＳＴ ＯＦ ＴＥＣＨＮＩ
ＣＡＬ ＰＡＰＥＲ３）、の１１４ページに記載されて
いるものがある。この回路を第５図に示す。As a circuit for speeding up this sense amplification, for example, Proceedings of the 1989 VSL 1 Circuit Symposium r 1
9g9, Symposium in VLSI Circuit, Digest of Technical Hepers (1989SYMPO8IUM ON VSLI C
IRCtJITS, DIGEST OF TECHNI
There is one described on page 114 of CAL PAPER 3). This circuit is shown in FIG.
このセンス増幅回路は、ＣＭＯＳ型フリップフロップか
らなる増幅回路に加え、該フリップフロップのＰチャネ
ル型ＭＩＳＦＥＴの共通ソースＳＡＰを、センス開始信
号線φｓｐをゲートに接続しなＰチャネル型ＭＩＳＦＥ
ＴのトランスファゲートＱｐを介して電源電圧レベル■
ＣＣに接続し、かつ、Ｎチャネル型ＭＩＳＦＥＴの共通
ソースＳＡＮを、センス開始信号線φＳＮをゲートに接
続したＮチャネル型ＭＩＳＦＥＴのトランスファゲート
ＱＮを介して接地レベル■ＳＳに接続している。In addition to an amplifier circuit consisting of a CMOS type flip-flop, this sense amplifier circuit is a P-channel type MISFE in which the common source SAP of the P-channel type MISFET of the flip-flop is connected to the gate of the sense start signal line φsp.
The power supply voltage level ■ through the transfer gate Qp of T
CC, and the common source SAN of the N-channel MISFET is connected to the ground level SS via the transfer gate QN of the N-channel MISFET whose gate is connected to the sense start signal line φSN.
ここで、φｓｐを低レベルに、φ５Ｎを高レベルにする
ことによりドライバＭ Ｉ Ｓ Ｆ ＥＴ、 Ｑｏｐ。Here, by setting φsp to a low level and φ5N to a high level, the driver MISFET, Qop.
ＱＤＮを動作させ、節点ＳＡＰ、ＳＡＮをプリチャージ
レベルからそれぞれｖｃｃ、ｖｓ、ｓにしてセンス増幅
を行う。Sense amplification is performed by operating the QDN and changing the nodes SAP and SAN from the precharge level to vcc, vs, and s, respectively.
上記のＳＡＰ、ＳＡＮをドライバＭＩＳＦＥＴで駆動す
るのみのセンス増幅では、ＳＡＰ、ＳＡＮの信号線の抵
抗が大きいため増幅が遅い。しかし、これに加えてトラ
ンスファゲートＱｐとＱＮが導通し、節点ＳＡＰ、ＳＡ
Ｎがそれぞれ電源線に短絡されるため、ｖｃｃ、ｖｓｓ
レベルへの到達が速くなる、従って、ビット線の信号増
幅も高速化する。In sense amplification in which the SAP and SAN are only driven by the driver MISFET, the amplification is slow because the resistance of the signal lines of the SAP and SAN is large. However, in addition to this, transfer gates Qp and QN become conductive, and nodes SAP and SA
Since N is short-circuited to the power supply line, vcc and vss
The level is reached faster and therefore the signal amplification on the bit line is also faster.
従来のセンス増幅回路は、φＳＰ＋ φＳＮの信号線の
配線長が長くなり、配線遅延が大きくなり、φｓｐ、φ
ＳＮの立ち下がり、立ち上がりが遅れ、結果としてセン
ス増幅回路中のトランスファゲートＱＰ、ＱＮの導通が
遅れてしまう欠点があった。In the conventional sense amplifier circuit, the wiring length of the signal line of φSP+φSN becomes long, the wiring delay becomes large, and
There was a drawback that the fall and rise of SN were delayed, resulting in a delay in conduction of transfer gates QP and QN in the sense amplifier circuit.
本発明の目的は、上記の抵抗ｒによる動作遅れをなくし
、更に高速センス増幅を実現する回路を提供することに
ある。An object of the present invention is to provide a circuit that eliminates the delay in operation caused by the resistor r and further realizes high-speed sense amplification.
第１の発明のセンス増幅回路は、複数のメモリセルを接
続したビット線、第１及び第２のＰチャネル型ＭＩＳＦ
ＥＴのドレインとゲートを各々交差接続し、かつ、前記
第１と第２のＰチャネル型ＭＩＳＦＥＴのソースを接続
したＰチャネル型ダイナミックフリップフロップ回路、
第１及び第２のＮチャネル型ＭＩＳＦＥＴのドレインと
ゲートを各々交差接続して第２のビット線に接続し、か
つ、前記第１と第２のＮチャネル型ＭＩＳＦＥＴのソー
スを接続したＮチャネル型ダイナミックフリップフロッ
プ回路、前記第１のＰチャネル型ＭＩＳＦＥＴのドレイ
ンと前記第１のＮチャネル型ＭＩＳＦＥＴのドレインと
を接続して第１のビット線に接続し、前記第２のＰチャ
ネル型Ｍ Ｉ Ｓ ＦＥＴのドレインと前記第２のＮチ
ャネル型ＭＩＳＦＥＴのドレインとを接続して第２のビ
ット線に接続したＣＭＯＳ型フリップフロップ回路、前
記第１及び第２のＮチャネル型ＭＩＳＦＥＴの共通ソー
スを、列選択回路の出力たる列選択信号線をゲートに接
続したＮチャネル型ＭＩＳＦＥＴからなるトランスファ
ゲートを介して接地レベル電源線と接続した回路とを含
んで構成される。The sense amplifier circuit of the first invention includes a bit line connecting a plurality of memory cells, first and second P-channel type MISF
a P-channel dynamic flip-flop circuit in which the drains and gates of the ETs are cross-connected, and the sources of the first and second P-channel MISFETs are connected;
an N-channel type MISFET in which the drains and gates of the first and second N-channel type MISFETs are cross-connected and connected to a second bit line, and the sources of the first and second N-channel type MISFETs are connected; a dynamic flip-flop circuit, the drain of the first P-channel MISFET and the drain of the first N-channel MISFET are connected to a first bit line, and the drain of the second P-channel MISFET is connected to the first bit line; A CMOS type flip-flop circuit in which the drain of the FET and the drain of the second N-channel MISFET are connected to a second bit line, and the common source of the first and second N-channel MISFET is connected to the column. It is configured to include a circuit connected to a ground level power supply line via a transfer gate made of an N-channel MISFET whose gate is connected to a column selection signal line which is an output of a selection circuit.
第２の発明のセンス増幅回路は、第１及び第２のＰチャ
ネル型ＭＩＳＦＥＴの共通ソースを、列選択信号の反転
信号を伝達する信号線をゲートに接続したＰチャネル型
ＭＩＳＦＥＴからなるトランスファゲートを介して電源
電圧レベル電源線と接続した回路で構成される。The sense amplifier circuit of the second invention includes a transfer gate made of a P-channel MISFET in which the common source of the first and second P-channel MISFETs is connected to the gate of the signal line that transmits the inverted signal of the column selection signal. It consists of a circuit connected to the power supply voltage level power line through the power supply line.
第３の発明のセンス増幅回路は、第１及び第２のＰチャ
ネル型ＭＩＳＦＥＴの共通ソースを、列選択信号の反転
信号を発生する回路を設け、その出力信号をゲートに接
続したＰチャネル型ＭＩＳＦＥＴからなるトランスファ
ゲートを介して電源電圧レベル電源線と接続した回路で
構成される。The sense amplification circuit of the third invention includes a P-channel MISFET in which the common source of the first and second P-channel MISFETs is provided with a circuit that generates an inverted signal of the column selection signal, and whose output signal is connected to the gate. It is composed of a circuit connected to a power supply voltage level power line through a transfer gate consisting of a power supply voltage level power supply line.
第４の発明のセンス増幅回路は、第１及び第２のＰチャ
ネル型ＭＩＳＦＥＴの共通ソースを、列選択信号線をゲ
ートに接続したＮチャネル型ＭＩＳＦＥＴからなるトラ
ンスファゲートを介して電源電圧レベル電源線と接続し
た回路で構成される。The sense amplifier circuit of the fourth invention connects the common source of the first and second P-channel MISFETs to the power supply voltage level power supply line through a transfer gate consisting of an N-channel MISFET whose gate is connected to the column selection signal line. It consists of a circuit connected to
従来、１ブロツク全てのセンス増幅回路中のトランスフ
ァゲートＱＰ、ＱＮを、信号φＳＰ＋ φＳＮで駆動し
ていたのに対し、本発明においては、当該トランスファ
ゲートを列選択回路からの出力である列選択信号ＹＤＥ
Ｃで駆動する。Conventionally, the transfer gates QP and QN in all the sense amplifier circuits of one block were driven by the signals φSP+φSN, but in the present invention, the transfer gates are driven by the column selection signal output from the column selection circuit. YDE
Driven by C.
一般に列選択信号線はアルミ等の低抵抗配線が用いられ
る。また、配線に関して、φＳＰ＋ φＳＮはドライバ
回路から１ブロツク全てのセンス増幅回路に接続されな
ければならないのに対し、ＹＤＥＣは列選択回路から選
択された１つのセンス増幅回路に接続されればよいため
、上記信号線φＳＰ＋φ５Ｎに比べ配線長が短くできる
。Generally, low resistance wiring such as aluminum is used for the column selection signal line. Regarding wiring, φSP+φSN must be connected to all sense amplifier circuits in one block from the driver circuit, whereas YDEC only needs to be connected to one sense amplifier circuit selected from the column selection circuit. The wiring length can be shortened compared to the signal line φSP+φ5N.
従って、本発明によって、センス増幅回路中のトランス
ファゲートＱＰ、ＱＮを駆動する際の配線遅延の影響が
小さくなり、センス増幅の高速化が図れる。Therefore, according to the present invention, the influence of wiring delay when driving the transfer gates QP and QN in the sense amplification circuit is reduced, and sense amplification can be performed at high speed.
次に本発明の一実施例を図面を参照して説明する。 Next, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
メモリセルからデータを読み出しビット線上に信号電圧
が現われた後、０ＭＯ８型フリップフロップの共通ソー
スＳＡＰ、ＳＡＮをそれぞれのドライバＭ Ｉ Ｓ Ｆ
Ｅ Ｔ 、 ＱＤＰ、 ＱＤＮによって駆動し、初期
増幅を行う。After data is read from the memory cell and a signal voltage appears on the bit line, the common sources SAP and SAN of the 0MO8 type flip-flop are connected to the respective drivers M I S F
It is driven by ET, QDP, and QDN to perform initial amplification.
その後、列選択回路から列選択信号が発生され、ＳＡＮ
と接地線■ＳＳを接続するＱＮが導通し、センス増幅が
加速される。（作用）項で述べたように、従来のセンス
開始信号φＳＮでトランスフアゲ−）ＱＮを駆動する方
式に比べ、本発明の列選択信号ＹＤＥＣで駆動する方式
は配線遅延を小さくすることができ、より高速なセンス
増幅を行うことができる。After that, a column selection signal is generated from the column selection circuit, and the SAN
QN, which connects the ground line ■SS, becomes conductive and sense amplification is accelerated. As described in the (Operation) section, compared to the conventional method of driving the transfer gate QN with the sense start signal φSN, the method of driving with the column selection signal YDEC of the present invention can reduce wiring delay. Faster sense amplification can be performed.
第２図は本発明は第２の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
センス増幅時にＳＡＮと■ＳＳとを接続するの加え、列
選択信号Ｙ Ｄ Ｅ ’Ｃの反転信号ｒσによりＱｐを
導通させ、Ｐチャネル型ダイナミックフリップフロップ
の共通ソースＳＡＰと■ＣＣ電源線とを接続することに
よって、ＳＡＰのＶＣＣレベルへの到達も高速化を図っ
ている。In addition to connecting SAN and ■SS during sense amplification, Qp is made conductive by the inverted signal rσ of the column selection signal YD E 'C, and the common source SAP of the P-channel dynamic flip-flop is connected to the ■CC power line. By doing so, the SAP reaches the VCC level faster.
第３図は本発明の第３の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a third embodiment of the present invention.
第２の発明において、列選択信号ＹＤＥＣの反転信号ｒ
を列選択回路部から発生し、かつメモリセルアレイ上を
ＹＤＥＣとｙｙ丁で−の２本の信号線かはしるという点
を改良し、センス増幅回路にＹＤＥＣの反転信号を発生
する回路を設け、この回路の出力をＱｐのゲートに接続
した。In the second invention, an inverted signal r of the column selection signal YDEC
is generated from the column selection circuit section, and the two signal lines YDEC and YY-D are run on the memory cell array, and a circuit for generating an inverted signal of YDEC is provided in the sense amplifier circuit. The output of the circuit was connected to the gate of Qp.
こうすることにより、メモリセルアレイ上をはしる信号
線を１本に減らし、かつ第２の発明と同様の効果を得る
ことができる。By doing so, the number of signal lines extending over the memory cell array can be reduced to one, and the same effect as the second invention can be obtained.
第４図は本発明の第４の実施例を示す回路図である。FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.
第３の発明で、センス増幅回路に反転回路を設けなけれ
ばならない点を改良し、ＳＡＰとＶｃｃとを接続するト
ランスファゲートＱｐをＮチャネル型ＭＩＳＦＥＴとし
た。こうすることにより、メモリセルアレイ上をはしる
信号線が、Ｙ Ｄ Ｅ Ｃのみでよいうえに、ＹＤＥＣ
の反転信号ｒを発生する必要がなくなる。従って、第３
の発明にあるような反転回路を設ける必要がない。In the third invention, the point that an inverting circuit must be provided in the sense amplifier circuit is improved, and the transfer gate Qp connecting SAP and Vcc is an N-channel MISFET. By doing this, the signal line running over the memory cell array only needs to be YDEC.
There is no need to generate an inverted signal r. Therefore, the third
There is no need to provide an inversion circuit as in the invention of .
以上に述べたように、本発明のセンス増幅回路Ｖよ、セ
ンス増幅回路と電源線を接続するトランスファゲートを
設け、そのトランスファゲートの導通／非導通の制御を
列選択回路からの列選択信号線によって行うことにより
、センス増幅の高速化を実現することができるという効
果がある。As described above, the sense amplifier circuit V of the present invention is provided with a transfer gate that connects the sense amplifier circuit and the power supply line, and the conduction/non-conduction of the transfer gate is controlled by the column selection signal line from the column selection circuit. By doing this, there is an effect that sense amplification can be realized at high speed.
幅回路Ｎチャネル型フリップフロップ共通ソース、φｓ
ｐ、φＳＮ・・・センス開始信号、ＹＤＥＣ・・・列選
択信号線、ＴＴｒσ・・・ＹＤＥＣの反転信号、ＱＮ・
・・ＳＡＮとＶＳＳを接続するトランスファゲート、Ｑ
Ｐ・・・ＳＡＰとＶＣＣを接続するトランスファゲート
、ＱＤｐ・・・ＳＡＰドライバ回路、ＱＤＮ・・・ＳＡ
Ｎドライバ回路、ＹＳＷ・・・ＢＬとＩＯを接続するト
ランスファゲート、ｒ・・・配線抵抗。Width circuit N-channel flip-flop common source, φs
p, φSN... sense start signal, YDEC... column selection signal line, TTrσ... inverted signal of YDEC, QN...
・Transfer gate connecting SAN and VSS, Q
P...Transfer gate connecting SAP and VCC, QDp...SAP driver circuit, QDN...SA
N driver circuit, YSW...transfer gate connecting BL and IO, r...wiring resistance.
Claims (4)
第２のＰチャネル型ＭＩＳＦＥＴのドレインとゲートを
各々交差接続しかつ前記第１と第２のＰチャネル型ＭＩ
ＳＦＥＴのソースを接続したＰチャネル型ダイナミック
フリップフロップ回路、第１及び第２のＮチャネル型Ｍ
ＩＳＦＥＴのドレインとゲートを各々交差接続して第２
のビット線に接続しかつ前記第１と第２のＮチャネル型
ＭＩＳＦＥＴのソースを接続したＮチャネル型ダイナミ
ックフリップフロップ回路、前記第１のＰチャネル型Ｍ
ＩＳＦＥＴのドレインと前記第１のＮチャネル型ＭＩＳ
ＦＥＴのドレインとを接続して第１のビット線に接続し
前記第２のＰチャネル型ＭＩＳＦＥＴのドレインと前記
第２のＮチャネル型ＭＩＳＦＥＴのドレインとを接続し
て第２のビット線に接続したＣＭＯＳ型フリップフロッ
プ回路、前記第１及び第２のＮチャネル型ＭＩＳＦＥＴ
の共通ソースを列選択回路の出力たる列選択信号線をゲ
ートに接続したＮチャネル型ＭＩＳＦＥＴからなるトラ
ンスファゲートを介して接地レベル電源線と接続した回
路とを含むことを特徴とするセンス増幅回路。(1) A bit line connecting a plurality of memory cells, the drains and gates of the first and second P-channel MISFETs are cross-connected, and the first and second P-channel MISFETs are
P-channel type dynamic flip-flop circuit connected to the source of SFET, first and second N-channel type M
Cross-connect the drains and gates of the ISFETs to create a second
an N-channel type dynamic flip-flop circuit connected to the bit line of the first P-channel type MISFET and the sources of the first and second N-channel type MISFETs;
The drain of the ISFET and the first N-channel MIS
The drain of the FET was connected to the first bit line, and the drain of the second P-channel MISFET and the drain of the second N-channel MISFET were connected to the second bit line. CMOS type flip-flop circuit, the first and second N-channel type MISFET
1. A sense amplifier circuit comprising: a circuit in which a common source of a column selection circuit is connected to a ground level power supply line via a transfer gate formed of an N-channel MISFET whose gate is connected to a column selection signal line which is an output of a column selection circuit.
ソースを、列選択信号の反転信号を伝達する信号線をゲ
ートに接続したＰチャネル型ＭＩＳＦＥＴからなるトラ
ンスファゲートを介して電源電圧レベル電源線と接続し
た回路で構成される請求項（１）記載のセンス増幅回路
。(2) The common source of the first and second P-channel MISFETs is connected to a power supply voltage level power supply line through a transfer gate consisting of a P-channel MISFET whose gate is connected to a signal line that transmits an inverted signal of a column selection signal. The sense amplifier circuit according to claim 1, comprising a circuit connected to.
ソースを、列選択信号の反転信号を発生する回路を設け
、その出力信号をゲートに接続したＰチャネル型ＭＩＳ
ＦＥＴからなるトランスファゲートを介して電源電圧レ
ベル電源線と接続した回路で構成される請求項（１）記
載のセンス増幅回路。(3) A P-channel MISFET in which the common source of the first and second P-channel MISFETs is provided with a circuit that generates an inverted signal of the column selection signal, and the output signal is connected to the gate.
2. The sense amplifier circuit according to claim 1, comprising a circuit connected to a power supply voltage level power supply line through a transfer gate formed of a FET.
ソースを、列選択信号をゲートに接続したＮチャネル型
ＭＩＳＦＥＴからなるトランスファゲートを介して電源
電圧レベル電源線と接続した回路で構成される請求項（
１）記載のセンス増幅回路。(4) Consisting of a circuit in which the common sources of the first and second P-channel MISFETs are connected to the power supply voltage level power supply line via a transfer gate consisting of an N-channel MISFET whose gate is connected to a column selection signal. Claims (
1) The sense amplifier circuit described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1272008A JP2605890B2 (en) | 1989-10-18 | 1989-10-18 | Sense amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1272008A JP2605890B2 (en) | 1989-10-18 | 1989-10-18 | Sense amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03132993A true JPH03132993A (en) | 1991-06-06 |
| JP2605890B2 JP2605890B2 (en) | 1997-04-30 |
Family
ID=17507855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1272008A Expired - Lifetime JP2605890B2 (en) | 1989-10-18 | 1989-10-18 | Sense amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2605890B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0411379A (en) * | 1990-04-27 | 1992-01-16 | Nec Corp | Semiconductor memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61158094A (en) * | 1984-12-28 | 1986-07-17 | Toshiba Corp | Sense amplifier drive circuit of dynamic memory |
| JPS62234292A (en) * | 1986-04-04 | 1987-10-14 | Nec Corp | Semiconductor storage device |
| JPH01133286A (en) * | 1987-11-17 | 1989-05-25 | Mitsubishi Electric Corp | Dynamic ram |
| JPH02208894A (en) * | 1989-02-08 | 1990-08-20 | Texas Instr Japan Ltd | Sense amplifier circuit |
-
1989
- 1989-10-18 JP JP1272008A patent/JP2605890B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61158094A (en) * | 1984-12-28 | 1986-07-17 | Toshiba Corp | Sense amplifier drive circuit of dynamic memory |
| JPS62234292A (en) * | 1986-04-04 | 1987-10-14 | Nec Corp | Semiconductor storage device |
| JPH01133286A (en) * | 1987-11-17 | 1989-05-25 | Mitsubishi Electric Corp | Dynamic ram |
| JPH02208894A (en) * | 1989-02-08 | 1990-08-20 | Texas Instr Japan Ltd | Sense amplifier circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0411379A (en) * | 1990-04-27 | 1992-01-16 | Nec Corp | Semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2605890B2 (en) | 1997-04-30 |
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