JPH03123034A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH03123034A JPH03123034A JP25876189A JP25876189A JPH03123034A JP H03123034 A JPH03123034 A JP H03123034A JP 25876189 A JP25876189 A JP 25876189A JP 25876189 A JP25876189 A JP 25876189A JP H03123034 A JPH03123034 A JP H03123034A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- forming
- etching
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 95
- 229910000765 intermetallic Inorganic materials 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- 239000012670 alkaline solution Substances 0.000 claims description 3
- 238000003631 wet chemical etching Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 abstract description 28
- 238000001039 wet etching Methods 0.000 abstract description 12
- 238000001312 dry etching Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 description 26
- 229910021332 silicide Inorganic materials 0.000 description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 13
- 239000010410 layer Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010953 base metal Substances 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体集積回路装置の製造方法に係り、特にサ
リサイド（Ｓｃｌｆ Ａｌｊｇｃｎｄ ５ｉｌｊｃｉｄ
ｃ）構造の半導体集積回路に於ける局所金属配線の形成
方法の改善に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of manufacturing a semiconductor integrated circuit device.
c) relates to an improvement in a method for forming local metal wiring in a semiconductor integrated circuit having a structure.
（従来の技術）
一般に半導体基板上に形成する集積回路の大規模化に従
って回路素子が微細化される方向にある。そして同構造
の回路素子において、その回路素子が固有に有する諸定
数は微細化に伴ないある傾向を持って変化していく。(Prior Art) Generally, as the scale of integrated circuits formed on semiconductor substrates increases, circuit elements tend to become smaller. In circuit elements having the same structure, various constants inherent to the circuit element tend to change as the circuit element becomes finer.
例えばＭＯ３形トランジスタの場合には、各チャンネル
コンダクタンスが大きくなっていくが、これに伴いソー
ス／ドレイン拡散層に寄生する寄生抵抗も相対的に大き
くなっている。For example, in the case of an MO3 type transistor, each channel conductance increases, but as a result, the parasitic resistance in the source/drain diffusion layer also increases relatively.
この結果、前記寄生抵抗の増加と、微細化されたソース
／ドレイン拡散層に接続する配線の抵抗等とによって伝
達遅延時間が遅くなる。さらに前記配線や接続箇所に流
れる電流密度の増加により配線寿命が短くなる等の問題
か生じて（る。As a result, the propagation delay time is delayed due to the increase in the parasitic resistance and the resistance of the wiring connected to the miniaturized source/drain diffusion layer. Furthermore, problems such as a shortened wiring life occur due to an increase in the current density flowing through the wiring and connection points.
これらに対処する方法として、ＭＯ３形トランジスタの
場合には、ソース／ドレイン拡散層上に高融点金属のシ
リサイド膜を形成したサリサイド構造の半導体集積回路
素子がある。As a method for dealing with these problems, in the case of MO3 type transistors, there is a semiconductor integrated circuit element having a salicide structure in which a silicide film of a refractory metal is formed on the source/drain diffusion layer.
すなわち、この回路素子に用いられている高融点シリサ
イド膜は、多結晶シリコン膜に比較すると一桁低い値の
２〜５Ω／口程度のシート抵抗値を持ち、シリコンと密
着性が良いという特徴がある。よって極小な電極の間を
接続する配線として多結晶シリコンの代わりに前記高融
点シリサイド膜を用いた場合に遅延時間を一桁の改善す
ることが可能である。In other words, the high melting point silicide film used in this circuit element has a sheet resistance value of about 2 to 5 Ω/hole, which is an order of magnitude lower than that of a polycrystalline silicon film, and is characterized by good adhesion to silicon. be. Therefore, when the high melting point silicide film is used instead of polycrystalline silicon as a wiring connecting between extremely small electrodes, it is possible to improve the delay time by one order of magnitude.
第３図（ａ）乃至（ｄ）は従来の技術を用いて半導体基
板上に形成されたトランジスタの構成図である。FIGS. 3(a) to 3(d) are block diagrams of transistors formed on a semiconductor substrate using conventional techniques.
すなわち第３図（ａ）において、半導体基板１上の素子
分離領域２に仕切られた回路素子形成領域３の所定位置
にゲート酸化膜４が形成され、その上に多結晶シリコン
からなるゲート電極５が形成されている。またゲート電
極５の形成される工程時に前記素子分離領域２上の所定
位置に多結晶シリコンからなる回路配線６を形成する。That is, in FIG. 3(a), a gate oxide film 4 is formed at a predetermined position in a circuit element formation region 3 partitioned into an element isolation region 2 on a semiconductor substrate 1, and a gate electrode 5 made of polycrystalline silicon is formed on the gate oxide film 4. is formed. Further, during the step of forming the gate electrode 5, a circuit wiring 6 made of polycrystalline silicon is formed at a predetermined position on the element isolation region 2.
第３図（ｂ）において、ゲート電極５に対して自己整合
的にソース／ドレイン領域７となる拡散層が形成された
後に、前記ゲート電極５の側面を囲むように絶縁体から
なる側壁８が形成される。In FIG. 3(b), after a diffusion layer serving as a source/drain region 7 is formed in a self-aligned manner with respect to the gate electrode 5, a side wall 8 made of an insulator is formed to surround the side surface of the gate electrode 5. It is formed.
そして半導体基板１全面上に、チタニュウムＴｉ、コバ
ルトＣｏ、 タンタルＴａ等の金属膜（図示せず）を堆
積させた後、加熱処理装置を用いて６００〜７５０℃程
度の温度で熱処理を施す。After depositing a metal film (not shown) of titanium Ti, cobalt Co, tantalum Ta, or the like on the entire surface of the semiconductor substrate 1, heat treatment is performed at a temperature of about 600 to 750° C. using a heat treatment apparatus.
この処理によって、前記金属膜とシリコン膜とが直接的
に接する回路配線６およびゲート電極５ソース／ドレイ
ン領域７の上にシリサイド膜９が形成され、その他の素
子分離領域２等の領域上の未反応の金属膜は選択的に除
去される。Through this process, a silicide film 9 is formed on the circuit wiring 6 and the gate electrode 5 source/drain region 7 where the metal film and the silicon film are in direct contact with each other, and a silicide film 9 is formed on other regions such as the element isolation region 2. The reactive metal film is selectively removed.
さらに第３図（ｃ）において、半導体基板１全面上に高
融点金属膜１０を堆積させ、所定領域にレジストパター
ン１１を形成し、ウェットもしくはドライエツチング方
法を用いて、前記所定領域外の高融点金属膜１０を削除
する。Furthermore, in FIG. 3(c), a high melting point metal film 10 is deposited on the entire surface of the semiconductor substrate 1, a resist pattern 11 is formed in a predetermined area, and high melting point areas outside the predetermined area are etched using a wet or dry etching method. The metal film 10 is removed.
これによって第３図（ｄ）に示すように、各回路素子の
電極（例えばゲート電極５）や回路配線６間を接続する
ように回路配線１０が形成されている。As a result, as shown in FIG. 3(d), circuit wiring 10 is formed so as to connect the electrodes (for example, gate electrode 5) of each circuit element and the circuit wiring 6.
（発明が解決しようとする課題）
前述したように半導体基板］」二に形成された各回路素
子の電極（例えばゲート電極５）や回路配線６間を接続
するための回路配線１０を形成するにあたって次のよう
な問題が生じる。すなわち、半導体基板］上の所定領域
にマスクとしてレジストパターン１１を形成し、前記所
定領域外の高融点金属膜１０を除去する際に高融点金属
膜］０とシリサイド膜９とのエツチング選択性によって
はシリサイド膜９も同時にエツチングされてしまうこと
が生じる。(Problem to be Solved by the Invention) As described above, in forming the circuit wiring 10 for connecting the electrodes (for example, the gate electrode 5) of each circuit element and the circuit wiring 6 formed on the semiconductor substrate 2. The following problems arise. That is, a resist pattern 11 is formed as a mask in a predetermined region on a semiconductor substrate, and when removing the refractory metal film 10 outside the predetermined region, the etching selectivity between the refractory metal film]0 and the silicide film 9 is In this case, the silicide film 9 may also be etched at the same time.
例えば、前記高融点金属膜１０が窒化チタニュウム（Ｔ
ｉＮ）でその下層のシリサイド膜９がチタニュウムシリ
サイド（ＴｉＳｉ、、）として、弗素糸ガスを反応性ガ
スとするドライエツチング方法を用いて、前記高融点金
属膜］０を除去した場合に、共に金属膜であるためにエ
ツチング選択比は約１．５〜２にすぎない。For example, the high melting point metal film 10 may be made of titanium nitride (T
iN), the underlying silicide film 9 becomes titanium silicide (TiSi, ), and when the high melting point metal film]0 is removed using a dry etching method using fluorine thread gas as a reactive gas, both metals are removed. Since it is a film, the etching selectivity is only about 1.5-2.
よって、前記高融点金属膜１０の除去される領域の高融
点金属膜の膜厚に差があったときには、薄い膜の部分が
除去された後も厚い膜の部分を完全に除去するまでオー
バーエツチングするので、前記薄い膜の部分の下層に形
成されたシリサイド膜がある程度除去されてしまう。Therefore, if there is a difference in the thickness of the high melting point metal film in the region to be removed of the high melting point metal film 10, even after the thin film portion is removed, over-etching is continued until the thick film portion is completely removed. Therefore, the silicide film formed under the thin film portion is removed to some extent.
さらに前記高融点金属膜１０に対してエツチング均一性
が悪い場合も同様に前記シリサイド膜がある程度除去さ
れている。Further, even when the etching uniformity is poor with respect to the high melting point metal film 10, the silicide film is similarly removed to some extent.
またウェットエツチング方法を用いた場合には、前述し
たようにレジストパターン１１を前記高融点金属膜］０
の上に形成し、選択性を有するエツチング溶液に浸す。Furthermore, when a wet etching method is used, the resist pattern 11 is formed by forming the high melting point metal film]0 as described above.
and immersed in a selective etching solution.
この結果、上層に前記レジストパターン］１が形成され
なかった前記高融点金属膜１０は除去される。このウエ
ットエチングの場合、前記のエツチング選択比は大きく
とることが可能で、アルカリ溶液において、約５０とい
う値か実現されている。As a result, the high melting point metal film 10 on which the resist pattern 1 is not formed is removed. In the case of this wet etching, the etching selectivity can be set to a large value, and a value of about 50 has been achieved in an alkaline solution.
しかし、このように前記高融点金属膜にウェットエツチ
ング方法を用いて除去すると第４図に示すようなサイド
エツチングが発生する。すなわち、半導体基板］２上に
高融点金属膜１３が形成され、その上にレジストパター
ン１４が形成されている。However, when the high melting point metal film is removed using the wet etching method, side etching as shown in FIG. 4 occurs. That is, a high melting point metal film 13 is formed on a semiconductor substrate] 2, and a resist pattern 14 is formed thereon.
この半導体基板１２をエツチング溶液に浸して、ウェッ
トエツチングを行うと、ウェットエツチングには等方向
性エツチングの特徴があり、エツチング溶液に接する高
融点金属膜１３の側面部分をエツチングしてしまい第４
図に示すように前記高融点金属膜１３の側面を挾るよう
に除去される。When this semiconductor substrate 12 is immersed in an etching solution and subjected to wet etching, the wet etching has the characteristic of isodirectional etching, and the side portions of the high melting point metal film 13 that are in contact with the etching solution are etched.
As shown in the figure, it is removed so as to sandwich the side surfaces of the high melting point metal film 13.
以上のように一般に微細加工に優れているドライエツチ
ング方法は被エツチング金属と下地金属とのエツチング
選択比が小さく、下地金属となるリサイド膜をある程度
除去してしまい、回路素子の特性を変える場合が生じる
。またウェットエツチング方法はエツチング選択比に関
して優れているが、等方向性エツチングであるために、
被エツチング金属にサイドエツチングを生じさせ、微細
加工に劣っている。As mentioned above, the dry etching method, which is generally excellent for microfabrication, has a low etching selectivity between the metal to be etched and the base metal, and removes some of the lyside film that serves as the base metal, which may change the characteristics of the circuit element. arise. In addition, although the wet etching method is superior in terms of etching selectivity, since it is isodirectional etching,
Side etching occurs on the metal to be etched, resulting in poor microfabrication.
そこで本発明は、半導体基板上に形成される回路素子や
配線等に用いられる金属膜の形成にウェット並びにドラ
イエツチング方法を採用できるようにして、局所金属配
線の形成を可能にすることを１」的とする。Therefore, the present invention aims to enable the formation of local metal wiring by making it possible to employ wet and dry etching methods for forming metal films used for circuit elements, wiring, etc. formed on semiconductor substrates. target
［発明の構成］
（課題を解決するための手段）
本発明は従来技術がもつ課題を解決するために、半導体
基板上に形成された素子分離領域によって包囲される回
路素子形成領域内の所定位置にゲート電極形成体とその
両側に制御電極形成体を形成し、前記素子分離領域上に
回路配線形成体を形成し、前記ゲート電極の側面に絶縁
体壁を形成する第１の工程と、前記第１の工程によって
形成された素子分離領域並びに回路素子形成領域の領域
面上に金属膜を形成する第２の工程と、前記第２の工程
によって形成された金属膜上の所定領域に絶縁膜を形成
する第３の工程と、前記第３の工程の後で前記第１の工
程によって形成された各電極構体に接する前記金属膜部
分を反応させて金属間化合物を自己整合的に形成するた
めに加熱処理を施す第４の工程と、前記第４の工程によ
って前記金属間化合物を形成しない前記金属膜部分を前
記第３の工程による絶縁膜をマスクとして除去する第７
の工程とからなることを特徴とする半導体集積回路装置
の製造方法を用いる。[Structure of the Invention] (Means for Solving the Problems) In order to solve the problems of the prior art, the present invention aims to solve the problems of the prior art, by providing a method for solving the problems of the prior art, by providing a method for detecting a predetermined position in a circuit element formation region surrounded by an element isolation region formed on a semiconductor substrate. a first step of forming a gate electrode forming body and a control electrode forming body on both sides thereof, forming a circuit wiring forming body on the element isolation region, and forming an insulator wall on the side surface of the gate electrode; a second step of forming a metal film on the surface of the element isolation region and circuit element formation region formed in the first step; and a step of forming an insulating film on a predetermined region on the metal film formed in the second step. and a third step of forming an intermetallic compound in a self-aligned manner by reacting the metal film portions in contact with each electrode structure formed in the first step after the third step. a fourth step of performing heat treatment on the metal film; and a seventh step of removing the portion of the metal film in which the intermetallic compound is not formed in the fourth step using the insulating film formed in the third step as a mask.
A method for manufacturing a semiconductor integrated circuit device is used, which is characterized by comprising the following steps.
そして第２の工程において前記絶縁膜が薄膜形成時にお
よそ５００℃以下の低温域で成形する。In a second step, the insulating film is formed at a low temperature of about 500° C. or lower when forming a thin film.
また、前記第３の工程において、前記絶縁膜を選択性を
有する異方性エツチング方法によって除去し、前記第４
の工程において、前記金属間化合物を形成しない前記金
属膜部分をアルカリ溶液による湿式化学エツチング方法
によって除去する製造方法を用いる。。Further, in the third step, the insulating film is removed by a selective anisotropic etching method, and the fourth
In the process, a manufacturing method is used in which the portion of the metal film that does not form the intermetallic compound is removed by a wet chemical etching method using an alkaline solution. .
（作用）
以上のような半導体集積回路の製造方法によって、選択
性を有する異方性エツチング方法並びに湿式化学エツチ
ング方法を採用することが可能０
になり、金属股上に微細な局所金属配線等の導電膜の形
成を行うことができる。(Function) The method for manufacturing semiconductor integrated circuits as described above makes it possible to employ an anisotropic etching method and a wet chemical etching method with selectivity. Formation of a film can be performed.
（実施例）
以下、図面を参照して本発明の実施例につき詳細に説明
する。(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図（ａ）乃至（ｄ）は、本発明の実施例として半導
体基板上に形成されたトランジスタの構成図である。FIGS. 1(a) to 1(d) are configuration diagrams of a transistor formed on a semiconductor substrate as an embodiment of the present invention.
すなわち第１図（ａ）において、半導体基板１上の素子
分離領域２に仕切られた回路素子形成領域３の所定位置
にゲート酸化膜４が形成され、その上に多結晶シリコン
からなるゲート電極５が形成されている。またゲート電
極５の形成する時に前記素子分離領域２上の所定位置に
多結晶シリコンからなる回路配線６をも形成する。さら
に、ゲート電極５に対して自己整合的にソース／ドレイ
ン領域となる拡散層７が形成された後に、前記ゲート電
極５の側面を囲むように絶縁体からなる側壁８が形成さ
れている。That is, in FIG. 1(a), a gate oxide film 4 is formed at a predetermined position in a circuit element formation region 3 partitioned into an element isolation region 2 on a semiconductor substrate 1, and a gate electrode 5 made of polycrystalline silicon is formed on the gate oxide film 4. is formed. Further, when forming the gate electrode 5, a circuit wiring 6 made of polycrystalline silicon is also formed at a predetermined position on the element isolation region 2. Further, after a diffusion layer 7 serving as a source/drain region is formed in a self-aligned manner with respect to the gate electrode 5, a side wall 8 made of an insulator is formed to surround the side surface of the gate electrode 5.
次の第１図（ｂ）において 前記半導体基板１１
上に高融点金属膜１５を堆積する。すなわち、前記半導
体基板１上の全面にチタニュウム膜（Ｔｉ）を５ＯｎＩ
１１の膜厚に堆積し、さらにこの上層に窒化チタニュウ
ム膜（Ｔ ｉ Ｎ）を１１００ｎの膜厚に堆積させた二
種類の高融点金属で成る膜１５としている。Next, in FIG. 1(b), a high melting point metal film 15 is deposited on the semiconductor substrate 11. That is, a titanium film (Ti) is formed on the entire surface of the semiconductor substrate 1 by 5OnI.
The film 15 is made of two types of high-melting point metals, which are deposited to a thickness of 110 nm, and a titanium nitride film (T i N) is further deposited to a thickness of 1100 nm on top of the titanium nitride film.
そして前記高融点金属膜１５上にＣＶＤ（Ｃｈｅｍｉｃ
ａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）装置により
５００℃以下の成膜温度で二酸化シリコン（ＳｉＯ２）
からなる絶縁膜１６を堆積させる。さらに前記絶縁膜１
６上の所定領域にレジストパターン１７を形成し、これ
をマスクとして所定領域外の絶縁膜１６を反応性イオン
エツチングによって除去し、その後に前記レジストパタ
ーン１７を除去する。Then, CVD (Chemical) is applied on the high melting point metal film 15.
Silicon dioxide (SiO2) is deposited at a film-forming temperature of 500°C or less using a vapor deposition system.
An insulating film 16 consisting of the following is deposited. Furthermore, the insulating film 1
A resist pattern 17 is formed in a predetermined region on 6, and using this as a mask, the insulating film 16 outside the predetermined region is removed by reactive ion etching, and then the resist pattern 17 is removed.
第１図（ｃ）において、同図（ｂ）の半導体基板１を窒
素ガスの雰囲気内で、７００℃、２０秒の熱処理を施し
、前記高融点金属膜１５がシリコン膜と接する部分をチ
タニュウムシリサイド（ＴｉＳｉｚ）１８へシリサイド
化反応させた。In FIG. 1(c), the semiconductor substrate 1 shown in FIG. 1(b) is subjected to heat treatment at 700° C. for 20 seconds in a nitrogen gas atmosphere, and the portion where the high melting point metal film 15 contacts the silicon film is made of titanium silicide. (TiSiz)18 was subjected to a silicidation reaction.
この後、１ツチング溶液（水酸化アンモニュウ２
ム、過酸化水素水を含む混合溶液）に前記半導体基板１
を浸して、前記素子分離領域２および側壁８上の未反応
の高融点金属膜１５を除去する。After that, the semiconductor substrate 1 is added to a 1 ttching solution (a mixed solution containing 2 ammonium hydroxide and a hydrogen peroxide solution).
The unreacted high melting point metal film 15 on the element isolation region 2 and the side wall 8 is removed by soaking in water.
ただしこのウェットエツチングの際に絶縁膜１６に覆わ
れている高融点金属膜１５（図中に示すＡ部分）は、絶
縁膜１６がマスクとなり除去されず、後述する第２図の
構造図に示すように残存する。However, during this wet etching, the high melting point metal film 15 (portion A shown in the figure) covered by the insulating film 16 is not removed because the insulating film 16 serves as a mask, as shown in the structural diagram of FIG. 2 described later. remain as such.
そして第１図（ｄ）において、前記絶縁膜１６と同様に
ＣＶＤ装置を用いて、同図（Ｃ）の半導体基板１の全面
に５００℃以下の成膜温度で絶縁膜１９を堆積する。つ
ぎに各回路素子の電極もしくは接続する箇所を設けるた
めに所定領域にドライエツチング方法を用いて、コンタ
クトホール２０を開孔する。Then, in FIG. 1(d), an insulating film 19 is deposited on the entire surface of the semiconductor substrate 1 in FIG. 1(C) at a film-forming temperature of 500° C. or less using a CVD apparatus in the same manner as the insulating film 16. Next, contact holes 20 are formed in predetermined areas using a dry etching method in order to provide electrodes or connection points for each circuit element.
また第２図において、第１図中のＡ部分の拡大された構
造図を示ｔ。Further, in FIG. 2, an enlarged structural diagram of part A in FIG. 1 is shown.
すなわち、高融点金属膜１５は前述した第１図（Ｃ）の
ウェットエツチングの際に、絶縁膜１６がチタニュウム
シリサイド１８まで覆うように形３
成されるため、高融点金属膜１５に対してマスクとなり
除去されずに残存する。従って、サイドエツチングの問
題は生じない。That is, the high melting point metal film 15 is formed so that the insulating film 16 covers the titanium silicide 18 during the wet etching shown in FIG. It remains without being removed. Therefore, the problem of side etching does not occur.
なお、本実施例において高融点金属は、チタニュウム（
Ｔｉ）、窒化チタニュウム（Ｔ ｉ Ｎ）の二層膜によ
る例を示したが、これに限らずタングステン（Ｗ）、コ
バルト（Ｃｏ）、白金（Ｐｔ）。In this example, the high melting point metal is titanium (
Although an example using a two-layer film of titanium nitride (Ti) and titanium nitride (T i N) has been shown, the present invention is not limited to this, and examples include tungsten (W), cobalt (Co), and platinum (Pt).
モリブデン（Ｍ ｏ ）等の金属単層膜もしくはこれら
の金属による合金膜もしくは窒化膜を用いることもでき
る。A single layer film of a metal such as molybdenum (M o ), an alloy film of these metals, or a nitride film can also be used.
従って、以上のことから金属膜からなる回路配線をパタ
ーン形成するときに反応性イオンエツチングを用いたと
しても、被エツチング膜が絶縁膜であるため、下地（下
層に形成される前記高融点金属膜）材料との間にエツチ
ング選択性がある。Therefore, from the above, even if reactive ion etching is used to pattern circuit wiring made of a metal film, since the film to be etched is an insulating film, ) There is etching selectivity between the materials.
さらにシリサイド膜にならなかった高融点金属の除去に
ウェットエツチングを用いたとしても、半導体基板１上
の記素子分離領域２および側壁８上以外の領域は絶縁膜
によって覆われるため、高融点金属膜１５からなる局所
金属配線は除去され４
ずに残存し、サイドエツチングも生じない。Furthermore, even if wet etching is used to remove the high melting point metal that has not become a silicide film, the areas on the semiconductor substrate 1 other than the element isolation region 2 and the side walls 8 are covered with an insulating film, so the high melting point metal film is removed. The local metal wiring consisting of 15 remains without being removed, and no side etching occurs.
従来は、この局所金属配線の形成に伴うサイドエツチン
グによる配線の寸法シフトを考慮して、本来必要な設計
の線幅に寸法変換量を加えた寸法であったため、この配
線を接続する拡散層は不必要な面積を有さねばならず面
積を縮小でなかった。Conventionally, in consideration of the wiring dimension shift due to side etching accompanying the formation of this local metal wiring, the dimension was determined by adding the amount of dimension change to the originally required design line width, so the diffusion layer connecting this wiring was The area could not be reduced because it had unnecessary area.
しかし本発明はサイドエツチングが生じないので、前記
寸法シフトがなくなる。よって、前記局所金属配線は本
来必要な線幅で設計することができると共に拡散層の面
積も従来の面積に対して２／３程度に縮小することがで
きる。However, in the present invention, since no side etching occurs, the above-mentioned dimensional shift is eliminated. Therefore, the local metal wiring can be designed with the originally required line width, and the area of the diffusion layer can be reduced to about 2/3 of the conventional area.
加えて、ソース／ドレイン拡散層の面積が減少するのに
伴い寄生容量も減少し、信号応答速度が１５％程度速く
なる。In addition, as the area of the source/drain diffusion layer decreases, the parasitic capacitance also decreases, and the signal response speed increases by about 15%.
また本発明の実施例ではサリサイド構造の形成に用いて
いるが、本発明はシリサイドに関わらず、金属膜を金属
間化合物に反応させ、これらを接続する金属配線等の形
成に応用することが可能である。Furthermore, although the embodiments of the present invention are used to form a salicide structure, the present invention can be applied to the formation of metal wiring, etc. that connects these by reacting a metal film with an intermetallic compound, regardless of silicide. It is.
また、本発明の実施例に限定されるものではな５
く、他にも発明の要旨を逸脱しない範囲で種々の変形や
応用が可能であることは勿論である。Furthermore, the present invention is not limited to the embodiments, and it goes without saying that various modifications and applications can be made without departing from the gist of the invention.
［発明の効果〕
以上詳述したような本発明による半導体集積回路装置の
局所金属配線の製造方法を採用することにより、絶縁膜
のパターン形成に微細加工に優れている異方性エツチン
グ方法を採用することができるようになり、さらに前記
絶縁膜を金属膜除去のマスクとしても利用することによ
って、微細な局所金属配線等の導電膜の形成が可能とな
る。[Effects of the Invention] By adopting the method for manufacturing local metal wiring of a semiconductor integrated circuit device according to the present invention as detailed above, an anisotropic etching method that is excellent in microfabrication is adopted for pattern formation of an insulating film. Furthermore, by using the insulating film as a mask for removing a metal film, it becomes possible to form a conductive film such as a fine local metal wiring.
第１図（ａ）乃至（ｄ）は本発明の半導体集積回路の製
造工程図、第２図は第１図（ｄ）の部分拡大図、第３図
は従来の半導体集積回路の製造工程図、第４図は従来の
製造方法により生じたサイドエツチングを示す部分拡大
図。
１・・・半導体基板、２・・・素子分離領域、３・・・
回路素子形成領域、４・・・ゲート酸化膜、５・・・ゲ
ート電極、７・・・ゲート／ドレイン拡散層（制御電極
）、１５・・・高融点金属膜、１６・・・絶縁膜、１８
・・・高融６
点シリサイド層（金属間化合物）。
７
ＣＯｎへ−
−１８８＝FIGS. 1(a) to (d) are manufacturing process diagrams of a semiconductor integrated circuit of the present invention, FIG. 2 is a partially enlarged view of FIG. 1(d), and FIG. 3 is a manufacturing process diagram of a conventional semiconductor integrated circuit. , FIG. 4 is a partially enlarged view showing side etching caused by the conventional manufacturing method. 1... Semiconductor substrate, 2... Element isolation region, 3...
Circuit element formation region, 4... Gate oxide film, 5... Gate electrode, 7... Gate/drain diffusion layer (control electrode), 15... High melting point metal film, 16... Insulating film, 18
...High melting 6-point silicide layer (intermetallic compound). 7 To CON- -188=
Claims (4)
包囲される回路素子形成領域内の所定位置にゲート電極
形成体とその両側に制御電極形成体を形成し、前記素子
分離領域上に回路配線形成体を形成し、前記ゲート電極
の側面に絶縁体壁を形成する第１の工程と、 前記第１の工程によって形成された素子分離領域並びに
回路素子形成領域の領域面上に金属膜を形成する第２の
工程と、 前記第２の工程によって形成された金属膜上の所定領域
に絶縁膜を形成する第３の工程と、前記第３の工程の後
で前記第１の工程によって形成された各電極構体に接す
る前記金属膜部分を反応させて金属間化合物を自己整合
的に形成するために加熱処理を施す第４の工程と、 前記第４の工程によって前記金属間化合物を形成しない
前記金属膜部分を前記第３の工程による絶縁膜をマスク
として除去する第７の工程とからなることを特徴とする
半導体集積回路装置の製造方法。(1) A gate electrode formation body and a control electrode formation body are formed on both sides of the gate electrode formation body at a predetermined position in a circuit element formation region surrounded by an element isolation region formed on a semiconductor substrate, and circuit wiring is formed on the element isolation region. a first step of forming a formation body and forming an insulator wall on the side surface of the gate electrode; and forming a metal film on the region surfaces of the element isolation region and the circuit element formation region formed in the first step. a second step of forming an insulating film in a predetermined region on the metal film formed in the second step; a fourth step of performing heat treatment to react the metal film portions in contact with each of the electrode structures to form an intermetallic compound in a self-aligned manner; A method of manufacturing a semiconductor integrated circuit device, comprising: a seventh step of removing the metal film portion using the insulating film formed in the third step as a mask.
項（１）記載の半導体集積回路装置の製造方法。(2) The method for manufacturing a semiconductor integrated circuit device according to claim (1), characterized in that the insulating film is formed at a low temperature of about 500° C. or lower when forming the thin film.
有する異方性エッチング方法によって除去することを特
徴とする請求項（１）記載の半導体集積回路装置の製造
方法。(3) The method for manufacturing a semiconductor integrated circuit device according to claim (1), wherein in the third step, the insulating film is removed by an anisotropic etching method having selectivity.
成しない前記金属膜部分をアルカリ溶液による湿式化学
エッチング方法によって除去することを特徴とする請求
項（１）記載の半導体集積回路装置の製造方法。(4) Manufacturing the semiconductor integrated circuit device according to claim 1, wherein in the fourth step, the portion of the metal film where the intermetallic compound is not formed is removed by a wet chemical etching method using an alkaline solution. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25876189A JPH03123034A (en) | 1989-10-05 | 1989-10-05 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25876189A JPH03123034A (en) | 1989-10-05 | 1989-10-05 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03123034A true JPH03123034A (en) | 1991-05-24 |
Family
ID=17324722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25876189A Pending JPH03123034A (en) | 1989-10-05 | 1989-10-05 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03123034A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4214507A1 (en) * | 1992-05-01 | 1993-11-04 | Minnesota Mining & Mfg | ADHESIVE ADHESIVE WITH FUEL |
-
1989
- 1989-10-05 JP JP25876189A patent/JPH03123034A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4214507A1 (en) * | 1992-05-01 | 1993-11-04 | Minnesota Mining & Mfg | ADHESIVE ADHESIVE WITH FUEL |
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