JPH0311653A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0311653A JPH0311653A JP14640589A JP14640589A JPH0311653A JP H0311653 A JPH0311653 A JP H0311653A JP 14640589 A JP14640589 A JP 14640589A JP 14640589 A JP14640589 A JP 14640589A JP H0311653 A JPH0311653 A JP H0311653A
- Authority
- JP
- Japan
- Prior art keywords
- film
- container
- cap
- brazing material
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005219 brazing Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 16
- 239000000919 ceramic Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 238000007789 sealing Methods 0.000 abstract description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 7
- 229910015363 Au—Sn Inorganic materials 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 3
- 229910000480 nickel oxide Inorganic materials 0.000 abstract description 3
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 abstract description 3
- 238000000605 extraction Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にセラミック封止型半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a ceramic sealed semiconductor device.
従来のセラミック封止型半導体装置は、第３図に示すよ
うに、凹状部を有するセラミック製の容器７に半導体素
子８をロー材等により固着し、セラミック板］の下面に
Ｗ膜２、バリア膜としてのＮｉ膜３及びＡｕメツキ膜４
を設けたキャップを、Ａ ｕ −Ｓ ｎロー材５により
容器７の側壁部に、Ａｕ膜６を介して封止した構造とな
っていた。As shown in FIG. 3, a conventional ceramic-sealed semiconductor device has a semiconductor element 8 fixed to a ceramic container 7 having a concave portion using brazing material or the like, and a W film 2 and a barrier on the lower surface of the ceramic plate. Ni film 3 and Au plating film 4 as films
The structure was such that a cap provided with this was sealed with an Au-Sn brazing material 5 to the side wall of the container 7 via an Au film 6.
上述した従来のセラミック封止型半導体装置は、キャッ
プを構成するセラミック板１の下面が封着用のＡ ｕ−
３ｒｌロー材５となじみの良いＡｕメツキ膜４で覆われ
ているため、封着用のＡｕＳｎロー材５が封着部より内
側に流れ込み、封着部のロー材量が少なくなり、封止の
ボイド等が発生して気密性が悪化し、半導体装置の信頼
性を低下させるという欠点がある。In the conventional ceramic sealed semiconductor device described above, the lower surface of the ceramic plate 1 constituting the cap is A u-
Since it is covered with the Au plating film 4 that is compatible with the 3rl brazing material 5, the AuSn brazing material 5 for sealing flows inward from the sealing part, reducing the amount of brazing material in the sealing part and eliminating voids in the sealing. etc., which deteriorates the airtightness and reduces the reliability of the semiconductor device.
本発明の半導体装置は、凹状部を有するセラミック製容
器と、該容器内に搭載された半導体素子と、少くとも下
面が金属層からなりロー材により前記容器を封止する平
板状キャップとを有する半導体装置において、封止部を
除く前記キャップ下面の金属層の表面を酸化膜で覆った
ものである。A semiconductor device of the present invention includes a ceramic container having a concave portion, a semiconductor element mounted in the container, and a flat cap whose lower surface is made of a metal layer and which seals the container with a brazing material. In the semiconductor device, the surface of the metal layer on the lower surface of the cap except for the sealing portion is covered with an oxide film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
凹状部を有するセラミック製の容器７内には半導体素子
８が搭載されており、この半導体素子８は、Ａｕワイヤ
９を介して容器７の下面に固着された外部引出し電極１
０に接続されている。A semiconductor element 8 is mounted in a ceramic container 7 having a concave portion, and this semiconductor element 8 is connected to an external extraction electrode 1 fixed to the lower surface of the container 7 via an Au wire 9.
Connected to 0.
この容器７を封止するキャップは、セラミック板１とそ
の下面に順次設けられたＷ膜３とバリア膜としてのＮｉ
膜３とから構成されており、封止部のみにＡｕメツキ膜
４が設けられ、露出しなＮｉ膜３の表面は酸化ニッケル
膜１１で覆われている。そして・このキャップは、容器
７の側面とＡｕ膜６を介してＡｕ−３ｎロー材５により
封止されている。The cap for sealing this container 7 consists of a ceramic plate 1, a W film 3 provided in sequence on the lower surface of the ceramic plate 1, and a Ni film as a barrier film.
An Au plating film 4 is provided only on the sealing portion, and the exposed surface of the Ni film 3 is covered with a nickel oxide film 11. This cap is sealed with the Au-3n brazing material 5 via the side surface of the container 7 and the Au film 6.
このように構成された第１実施例によれは、封止部を除
いたＮｉ膜３の表面は酸化ニッケル膜１１により覆われ
ているため、Ａｕ−８ｎロー材５でキャップと容器７と
を封止した場合、ＡｕＳｎロー材５は封止部の内側に流
れ出ることはなくなる。According to the first embodiment configured in this way, the surface of the Ni film 3 except for the sealing part is covered with the nickel oxide film 11, so the cap and the container 7 are connected with the Au-8n brazing material 5. When sealed, the AuSn brazing material 5 will not flow out inside the sealed portion.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
この第２の実施例においては、キャップはコバー板２１
からなっており、封止部を含む表面はＡｕメツキ膜４で
覆われているが、特にこのコバー板２１の下面では、封
止部以外は酸化膜２２で覆われている。In this second embodiment, the cap is attached to the cover plate 21.
The surface including the sealing part is covered with an Au plating film 4, but especially the lower surface of the cover plate 21 is covered with an oxide film 22 except for the sealing part.
このように構成された第２の実施例においても、封止時
のＡｕ−３ｎロー材５は、酸化膜２２が存在するため内
側に流れ出すことはない。更にキャップがコバー板で構
成されているため、第１の実施例に比べて、Ｗ膜やＮｉ
膜を形成する工程が少くなるという利点がある。Also in the second embodiment configured in this manner, the Au-3n brazing material 5 during sealing does not flow inward because of the presence of the oxide film 22. Furthermore, since the cap is made of a cover plate, compared to the first embodiment, the cap is made of a W film and Ni film.
This has the advantage that the number of steps for forming the film is reduced.
以上説明したように本発明は、キャップの下面の封止部
を除く金属層の表面を酸化膜で覆うことにより、容器と
キャップを封止する際に封止用ロー材が内部へ流れ込む
のを防止でき、封着ロー材の量が均一になる。従って気
密性が改善され、半導体装置の信頼性が向上するという
効果がある。As explained above, the present invention covers the surface of the metal layer except for the sealing part on the bottom surface of the cap with an oxide film to prevent the sealing brazing material from flowing into the inside when sealing the container and the cap. This can be prevented and the amount of sealing brazing material can be made uniform. Therefore, the airtightness is improved and the reliability of the semiconductor device is improved.
第１図及び第２図は本発明の第１及び第２の実施例の断
面図、第３図は従来の半導体装置の一例の断面図である
。1 and 2 are cross-sectional views of first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device.
Claims (1)
れた半導体素子と、少くとも下面が金属層からなりロー
材により前記容器を封止する平板状キャップとを有する
半導体装置において、封止部を除く前記キャップ下面の
金属層の表面を酸化膜で覆ったことを特徴とする半導体
装置。A semiconductor device comprising a ceramic container having a concave portion, a semiconductor element mounted in the container, and a flat cap whose lower surface is made of a metal layer and which seals the container with a brazing material. A semiconductor device characterized in that the surface of the metal layer on the lower surface of the cap except for the surface of the metal layer is covered with an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14640589A JPH0311653A (en) | 1989-06-07 | 1989-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14640589A JPH0311653A (en) | 1989-06-07 | 1989-06-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0311653A true JPH0311653A (en) | 1991-01-18 |
Family
ID=15406958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14640589A Pending JPH0311653A (en) | 1989-06-07 | 1989-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0311653A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703397A (en) * | 1991-11-28 | 1997-12-30 | Tokyo Shibaura Electric Co | Semiconductor package having an aluminum nitride substrate |
| KR100237669B1 (en) * | 1992-11-28 | 2000-01-15 | 윤종용 | Multi layer ceramic package |
| US6046074A (en) * | 1995-06-05 | 2000-04-04 | International Business Machines Corporation | Hermetic thin film metallized sealband for SCM and MCM-D modules |
| US6388887B1 (en) | 1993-12-27 | 2002-05-14 | Hitachi, Ltd. | Surface mount type package unit |
| JP2007281245A (en) * | 2006-04-07 | 2007-10-25 | Mitsubishi Electric Corp | Electronic apparatus |
| US10183360B2 (en) | 2013-10-03 | 2019-01-22 | Hitachi Metals, Ltd. | Hermetic sealing cap, electronic component housing package, and method for manufacturing hermetic sealing cap |
-
1989
- 1989-06-07 JP JP14640589A patent/JPH0311653A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703397A (en) * | 1991-11-28 | 1997-12-30 | Tokyo Shibaura Electric Co | Semiconductor package having an aluminum nitride substrate |
| KR100237669B1 (en) * | 1992-11-28 | 2000-01-15 | 윤종용 | Multi layer ceramic package |
| US6388887B1 (en) | 1993-12-27 | 2002-05-14 | Hitachi, Ltd. | Surface mount type package unit |
| US6463804B2 (en) | 1993-12-27 | 2002-10-15 | Hitachi, Ltd. | Acceleration sensor |
| US6561030B2 (en) | 1993-12-27 | 2003-05-13 | Hitachi, Ltd. | Acceleration sensor |
| US6566742B1 (en) * | 1993-12-27 | 2003-05-20 | Hitachi, Ltd. | Structure for mounting components |
| US6046074A (en) * | 1995-06-05 | 2000-04-04 | International Business Machines Corporation | Hermetic thin film metallized sealband for SCM and MCM-D modules |
| JP2007281245A (en) * | 2006-04-07 | 2007-10-25 | Mitsubishi Electric Corp | Electronic apparatus |
| US10183360B2 (en) | 2013-10-03 | 2019-01-22 | Hitachi Metals, Ltd. | Hermetic sealing cap, electronic component housing package, and method for manufacturing hermetic sealing cap |
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