JPH03110847U - - Google Patents
Info
- Publication number
- JPH03110847U JPH03110847U JP2030390U JP2030390U JPH03110847U JP H03110847 U JPH03110847 U JP H03110847U JP 2030390 U JP2030390 U JP 2030390U JP 2030390 U JP2030390 U JP 2030390U JP H03110847 U JPH03110847 U JP H03110847U
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead pins
- integrated circuit
- exposed portion
- molding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000465 moulding Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
第１図ないし第３図は本考案に係る集積回路パ
ツケージの第１実施例を示し、第１図は組立状態
を示す斜視図、第２図は第１図における構成のも
のを成形前にアタツチメントを挿入した状態を示
す要部断面図、第３図は第１図における構成のも
のを成形するための金型及び被成形部品の断面図
である。第４図は本考案に係る集積回路パツケー
ジの第２実施例を示す断面図である。
１……パツケージ、３……リードピン、４……
基板、５……電子素子、６……アタツチメント、
１１……端子。
1 to 3 show a first embodiment of an integrated circuit package according to the present invention, FIG. 1 is a perspective view showing an assembled state, and FIG. 2 shows an attachment of the structure shown in FIG. 1 before molding. FIG. 3 is a cross-sectional view of a mold and a molded part for molding the structure shown in FIG. 1. FIG. 4 is a sectional view showing a second embodiment of the integrated circuit package according to the present invention. 1...Package cage, 3...Lead pin, 4...
Substrate, 5... Electronic element, 6... Attachment,
11...Terminal.
Claims (1)
直に立設し、金型を用いて樹脂で封止したパツケ
ージにおいて、前記パツケージは、成形前に予め
前記リードピンに挿入しかつ密着し成形後に取出
し可能なアタツチメントによる露出部を有し、こ
の露出部を端子として構成したことを特徴とする
集積回路パツケージ。 In a package in which lead pins are vertically set up on the surface of a substrate on which an integrated circuit is formed and sealed with resin using a mold, the package is inserted into the lead pins before molding, is brought into close contact with the lead pins, and can be removed after molding. What is claimed is: 1. An integrated circuit package having an exposed portion formed by an attachment, the exposed portion being configured as a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2030390U JPH03110847U (en) | 1990-02-28 | 1990-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2030390U JPH03110847U (en) | 1990-02-28 | 1990-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03110847U true JPH03110847U (en) | 1991-11-13 |
Family
ID=31523399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2030390U Pending JPH03110847U (en) | 1990-02-28 | 1990-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03110847U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998008251A1 (en) * | 1996-08-20 | 1998-02-26 | Hitachi, Ltd. | Semiconductor and method for manufacturing the same |
| JP2003007966A (en) * | 2001-06-19 | 2003-01-10 | Mitsubishi Electric Corp | Semiconductor device |
-
1990
- 1990-02-28 JP JP2030390U patent/JPH03110847U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998008251A1 (en) * | 1996-08-20 | 1998-02-26 | Hitachi, Ltd. | Semiconductor and method for manufacturing the same |
| JP2003007966A (en) * | 2001-06-19 | 2003-01-10 | Mitsubishi Electric Corp | Semiconductor device |
| JP4540884B2 (en) * | 2001-06-19 | 2010-09-08 | 三菱電機株式会社 | Semiconductor device |
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