JPH03108734A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03108734A JPH03108734A JP16319689A JP16319689A JPH03108734A JP H03108734 A JPH03108734 A JP H03108734A JP 16319689 A JP16319689 A JP 16319689A JP 16319689 A JP16319689 A JP 16319689A JP H03108734 A JPH03108734 A JP H03108734A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring pattern
- semiconductor device
- electrode
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 239000011347 resin Substances 0.000 claims abstract description 45
- 229920005989 resin Polymers 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000010931 gold Substances 0.000 claims abstract description 31
- 229910052738 indium Inorganic materials 0.000 claims abstract description 31
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052737 gold Inorganic materials 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 35
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims description 11
- 230000008018 melting Effects 0.000 claims description 11
- 229920001187 thermosetting polymer Polymers 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 11
- 238000012360 testing method Methods 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 229910001128 Sn alloy Inorganic materials 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000005470 impregnation Methods 0.000 description 6
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000008439 repair process Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 2
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000005361 soda-lime glass Substances 0.000 description 2
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 2
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- -1 ITO Chemical compound 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- IHWJXGQYRBHUIF-UHFFFAOYSA-N [Ag].[Pt] Chemical compound [Ag].[Pt] IHWJXGQYRBHUIF-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000000123 paper Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体素子と基板とを接続してなる半導体装
置に係り、特に半導体素子のフェイスダウンボンディン
グの改良をはかった半導体装置及びその製造方法に関す
る。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device formed by connecting a semiconductor element and a substrate, and particularly aims to improve face-down bonding of the semiconductor element. The present invention relates to a semiconductor device and its manufacturing method.
（従来の技術）
近年、半導体集積回路技術の進歩により、端子数が１０
０を超える素子が出現してきている。(Conventional technology) In recent years, with advances in semiconductor integrated circuit technology, the number of terminals has increased to 10.
Elements with more than 0 are appearing.
それに伴い、絶縁基板上に形成された配線パタンに高密
度集積回路素子を効率的にボンディングする技術が望ま
れている。Accordingly, a technology for efficiently bonding high-density integrated circuit elements to a wiring pattern formed on an insulating substrate is desired.
半導体素子の多数の電極端子を、絶縁基板上に形成され
た配線パターンに一括してボンディングする方法として
、特開昭６２−１３２３３１号公報及び特開昭６２−１
６９４３３号公報等が提案されている。これらの提案で
は、第７図（ａ）に示すように、配線パターン２２を有
する絶縁基板２１上に樹脂１４をポツティングした後に
、半導体素子１１のバンプ電極１２と導体配線パターン
２２とを位置合せする。その後、第７図（ｂ）に示すよ
うに、半導体索子１１を絶縁基板２１に圧接しながら、
樹脂１４を硬化収縮させることにより、半導体素子１１
のバンプ電極１２と絶縁基板２１上の配線パターン２２
とを接続している。As a method for collectively bonding a large number of electrode terminals of a semiconductor element to a wiring pattern formed on an insulating substrate, Japanese Patent Laid-Open No. 62-132331 and Japanese Patent Laid-Open No. 62-1
Publication No. 69433 and the like have been proposed. In these proposals, as shown in FIG. 7(a), after potting the resin 14 on the insulating substrate 21 having the wiring pattern 22, the bump electrodes 12 of the semiconductor element 11 and the conductive wiring pattern 22 are aligned. . Thereafter, as shown in FIG. 7(b), while pressing the semiconductor cord 11 against the insulating substrate 21,
By curing and shrinking the resin 14, the semiconductor element 11
bump electrode 12 and wiring pattern 22 on the insulating substrate 21
is connected to.
しかしながら、この種の方法にあっては次のような問題
があった。即ち、半導体素子のバンプ電極と配線パター
ンとの接続が樹脂の硬化後に初めて生成されるため、樹
脂を硬化させる前に加圧を除去すると、樹脂の応力によ
って接続が不安定になったり、またそれによって樹脂自
身がバンプ電極と配線パターンとの接続部に入り込んだ
りする。このため、硬化前に加圧力を除去することはで
きず、バンプ電極と配線バタンとを位置合せした後、樹
脂が硬化するまで加圧を続ける必要がある。従って、位
置合せ機構の付いた高価な機械の専有時間が長くなり、
生産性か悪い。また、半導体素子の不良或いは実装不良
か生じた場合に半導体素子を取り替えるには、硬化した
樹脂を除去しなければならず、リペア−が極めて困難で
ある。However, this type of method has the following problems. In other words, since the connection between the bump electrode of the semiconductor element and the wiring pattern is created only after the resin is cured, if the pressure is removed before the resin is cured, the stress in the resin may cause the connection to become unstable or As a result, the resin itself may enter the connection portion between the bump electrode and the wiring pattern. For this reason, it is not possible to remove the pressurizing force before curing, and after aligning the bump electrode and the wiring button, it is necessary to continue pressurizing until the resin is cured. Therefore, the exclusive use time of expensive machines with alignment mechanisms increases,
Productivity is bad. Further, in order to replace the semiconductor element in the event of a defective semiconductor element or poor mounting, the cured resin must be removed, making repair extremely difficult.
（発明が解決しようとする課題）
このように従来、樹脂の硬化を利用して半導体素子を絶
縁性基板にフェイスダウンでマウントする方法では、十
分な電気的接続が取れるとは言えず接続の信頼性が低い
。また、樹脂が硬化するまで加圧を続ける必要があり生
産性が悪く、さらに半導体素子を取り替えるには樹脂を
除く必要があり、リペア−が極めて困難である等の問題
があった。(Problem to be Solved by the Invention) As described above, the conventional method of mounting semiconductor elements face-down on an insulating substrate using curing of resin does not allow for sufficient electrical connection, resulting in poor connection reliability. low gender. In addition, it is necessary to continue applying pressure until the resin hardens, resulting in poor productivity.Furthermore, in order to replace the semiconductor element, it is necessary to remove the resin, making repair extremely difficult.
本発明は、上記問題を考慮してなされたもので、その目
的とするところは、半導体素子を絶縁性基板にフェイス
ダウンでマウントすることができ、且つ接続部の信頼性
向上及び半導体素子交換の容易化等をはかり得る半導体
装置及びその製造方法を提供することにある。The present invention has been made in consideration of the above problems, and its purpose is to enable semiconductor elements to be mounted face-down on an insulating substrate, and to improve the reliability of connection parts and facilitate the replacement of semiconductor elements. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can be simplified.
［発明の構成コ
（課題を解決するための手段）
本発明の骨子は、半導体素子と絶縁性基板とを樹脂で接
着するのではなく、インジウム等の金属を含む接続用突
起電極によって接続することにあり、樹脂は該電極によ
る接続の補強材として用いることにある。[Structure of the Invention (Means for Solving the Problems) The gist of the present invention is to connect a semiconductor element and an insulating substrate not by bonding them with resin, but by connecting protruding electrodes containing a metal such as indium. The purpose is to use the resin as a reinforcing material for the connection by the electrodes.
即ち本発明は、配線パターンが形成された基板上に半導
体素子をフェイスダウンでマウントした半導体装置にお
いて、前記半導体素子の電極上に金バンプを設け、この
金バンプと前記配線パターンとをインジウムを含む金属
（接続用突起電極）を介して接合するようにしたもので
あり、さらに望ましくはインジウムを含む金属を金バン
プの配線パターンとの接合面側の側面まで到達するよう
に設けたものである。That is, the present invention provides a semiconductor device in which a semiconductor element is mounted face-down on a substrate on which a wiring pattern is formed, in which gold bumps are provided on the electrodes of the semiconductor element, and the gold bumps and the wiring pattern are bonded to each other in a manner that contains indium. The bonding is performed through a metal (projection electrode for connection), and more preferably, a metal containing indium is provided so as to reach the side surface of the gold bump on the bonding surface side with the wiring pattern.
また本発明は、絶縁基板上に半導体素子をフェイスダウ
ンでマウントしてなる半導体装置の製造方法において、
半導体素子に形成された接続用突起電極と絶縁基板上に
形成された配線パターンとを、接続用突起電極の融点以
下の温度で加熱・加圧して接合を行い、接合を行った後
に半導体素子と絶縁基板との隙間に光硬化性若しくは熱
硬化性の樹脂を含浸し、この樹脂を硬化させて接続強度
を上げるようにしたものである。The present invention also provides a method for manufacturing a semiconductor device in which a semiconductor element is mounted face down on an insulating substrate.
The connecting protruding electrodes formed on the semiconductor element and the wiring pattern formed on the insulating substrate are bonded by heating and pressurizing them at a temperature below the melting point of the connecting protruding electrodes, and after bonding, the semiconductor element and A photocurable or thermosetting resin is impregnated into the gap between the insulating substrate and the resin is cured to increase the connection strength.
また本発明は、上記接続用突起電極として、インジウム
、スズ、鉛若しくは銀、又はこれらの少なくとも２種の
合金を用い、該合金を前記半導体素子のバンプ電極上に
形成するようにした方法である。The present invention also provides a method in which indium, tin, lead, silver, or an alloy of at least two of these is used as the connection protrusion electrode, and the alloy is formed on the bump electrode of the semiconductor element. .
さらに、上記合金の製造方法として、半導体素子のバン
プ側をインジウムを含む金属の溶液中に浸漬することに
より、インジウムを含む球面状の金属を形成する、或い
は加熱された半導体素子のバンプ側をインジウムを含む
金属をシート状にしたシート部材に接触させることによ
り、インジウムを含む針状の金属を形成するようにした
方法である。Furthermore, as a manufacturing method of the above alloy, the bump side of a semiconductor element is immersed in a solution of a metal containing indium to form a spherical metal containing indium, or the bump side of a heated semiconductor element is immersed in a solution of a metal containing indium. In this method, a needle-shaped metal containing indium is formed by bringing the metal containing indium into contact with a sheet member.
（作用）
本発明によれば、半導体素子と配線パターンを有する絶
縁基板とを、インジウム、スズ、鉛。(Function) According to the present invention, a semiconductor element and an insulating substrate having a wiring pattern are made of indium, tin, and lead.
銀又はこれらの合金材料からなる接続用突起電極を介し
て、その接続用突起電極の融点以下の温度で圧接する。Pressure is applied via a protruding connecting electrode made of silver or an alloy thereof at a temperature below the melting point of the protruding connecting electrode.
このため、接続用突起電極自身の塑性変形により、界面
に存在する酸化層が除去されて電気的接続が得うれる。Therefore, the oxidized layer existing at the interface is removed by plastic deformation of the connecting protruding electrode itself, and electrical connection can be obtained.
また、この段階で不良が生じた場合、樹脂が充填されて
いないため、半導体素子を機械的に除去するだけでよく
、素子のりペアーが容易である。さらに、半導体素子の
接続用突起電極と配線パターンを接合した後、素子・基
板間の隙間に樹脂を含浸することによって、半導体素子
と基板との接着強度を上げ高い信頼性で接続することが
可能となる。In addition, if a defect occurs at this stage, since the resin is not filled, it is sufficient to mechanically remove the semiconductor element, and the elements can be easily re-paired. Furthermore, by impregnating the gap between the element and the substrate with resin after bonding the protruding electrodes for connection of the semiconductor element and the wiring pattern, it is possible to increase the adhesive strength between the semiconductor element and the substrate and to connect with high reliability. becomes.
また、インジウムを含む金属（接続用突起電極）をバン
プの側面まで到達するように設けることにより、バンプ
と接続用突起電極との接続の安定性及び接触抵抗の低減
をはかり得る。さらに、半導体素子のバンプ側をインジ
ウムを含む金属の溶液中に浸漬する、或いはインジウム
を含む金属をシート状にしたシート部材に接触させるこ
とにより、接続用突起電極を容易に形成することが可能
となる。Furthermore, by providing the metal containing indium (projection electrode for connection) so as to reach the side surface of the bump, stability of the connection between the bump and the projection electrode for connection and reduction in contact resistance can be achieved. Furthermore, protruding electrodes for connection can be easily formed by immersing the bump side of the semiconductor element in a solution of a metal containing indium or by bringing it into contact with a sheet member made of a metal containing indium. Become.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図は本発明の第１の実施例に係わる半導体装置の製
造工程を示す断面図である。まず、第１図（ａ）に示す
如く、バンプ電極１２上に接続用突起電極１３が形成さ
れた半導体素子１１と、導体配線パターン２２が形成さ
れた絶縁基板（配線基板）２１を用意する。FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG. 1(a), a semiconductor element 11 having connection protruding electrodes 13 formed on bump electrodes 12 and an insulating substrate (wiring board) 21 having a conductor wiring pattern 22 formed thereon are prepared.
次いで、第１図（ｂ）に示す如く、絶縁基板２１を支持
台３２上に載置し、絶縁基板２１上に形成された導体配
線パターン２２と、半導体素子１１のバンプ電極１２上
に形成された接続用突起電極１３とを位置合せして接触
させる。Next, as shown in FIG. 1(b), the insulating substrate 21 is placed on the support stand 32, and the conductor wiring pattern 22 formed on the insulating substrate 21 and the bump electrode 12 of the semiconductor element 11 are placed on the insulating substrate 21. The connecting projection electrodes 13 are aligned and brought into contact with each other.
この状態で、加熱ヘッド３１により半導体素子０
１１を絶縁基板２１側に押圧すると共に、接続用突起電
極１３をその融点以下の温度に加熱する。In this state, the heating head 31 presses the semiconductor element 011 toward the insulating substrate 21 and heats the connection protrusion electrode 13 to a temperature below its melting point.
次いで、加熱・加圧を終了した後、第１図（ｃ）に示す
如く、半導体素子１１と絶縁基板２１との隙間に熱硬化
性樹脂１４を含浸させ、これに熱を加えて硬化させるこ
とにより、半導体素子１１の絶縁基板２１へのマウント
（フェイスダウンボンディング）が終了する。Next, after completing the heating and pressurization, as shown in FIG. 1(c), a thermosetting resin 14 is impregnated into the gap between the semiconductor element 11 and the insulating substrate 21, and heat is applied to cure the resin. This completes the mounting (face-down bonding) of the semiconductor element 11 onto the insulating substrate 21.
ここで、絶縁基板２１には、ガラス、セラミック ガラ
スエポキシ、金属コア基板、ポリイミド及び紙フエノー
ル基板等を用いることができ、導体配線パターン２２と
しては、ニッケル。Here, the insulating substrate 21 can be made of glass, ceramic glass epoxy, metal core substrate, polyimide, paper phenol substrate, etc., and the conductor wiring pattern 22 can be made of nickel.
銅、チタン、ＩＴＯ，クロム、アルミニウム。Copper, titanium, ITO, chromium, aluminum.
モリブテン、タンタル、タングステン、金、銀或いはこ
れらの金属の合金を用いることができる。導体配線パタ
ーン２２の形成方法としては、スパッタ、蒸着及びメツ
キ等が用いられる。例えば、絶縁基板２１として厚さ１
、１ｍｍのソーダライムガラスを用いる。このガラス
基板上に１
ＳｉＯ２を約１００人デイツプ形成した後、ＩＴＯを厚
さ１０００人蒸着し、さらに５０００人のニッケルの無
電解メツキを行い、導体配線パターン２２を形成する。Molybdenum, tantalum, tungsten, gold, silver, or alloys of these metals can be used. As a method for forming the conductive wiring pattern 22, sputtering, vapor deposition, plating, etc. are used. For example, the thickness of the insulating substrate 21 is 1
, 1 mm soda lime glass is used. After about 100 layers of 1 SiO2 are formed on the glass substrate, ITO is deposited to a thickness of 1000 layers, and electroless plating of nickel is further applied to 5000 layers to form a conductive wiring pattern 22.
半導体素子１１は、アルミポンディングパッド上に適当
なバンプ電極１２を有しており、さらに接続用突起電極
１３として、インジウム。The semiconductor element 11 has a suitable bump electrode 12 on an aluminum bonding pad, and furthermore, a protruding electrode 13 for connection is made of indium.
スズ、鉛、銀又はこれらの２種以上を含む合金からなる
電極が形成されている。ここで、適当なバンプ電極１２
としては、Ａｕバンプ、Ｎｉバンプ、Ｃｕバンプ及び半
田バンプ等を用いることができる。該バンプの形成方法
としては、ウェハ状態でアルミポンディングパッド上に
薄膜、ＰＥＰ、プロセスにより、バリア層及び接着層を
形成し、電気メツキによりバンプを形成するいわゆる湿
式バンプ法を用いることができる。さらに、別の支持台
上に前述と同様の方法でバンプを形成しておき、該バン
プを半導体素子側に転写するいわゆる転写バンプ方式を
用いて形成することもできる。本実施例では、湿式バン
プ法で形成したＡｕバンプを有する半導体素子を用いた
。パンプザイズは８５Ｘ８５μｍ１高さは１８μｍ±２
μｍ１バンプ数は９９個、最小バンプピッチは１３０μ
ｍである。An electrode made of tin, lead, silver, or an alloy containing two or more of these is formed. Here, a suitable bump electrode 12
As examples, Au bumps, Ni bumps, Cu bumps, solder bumps, etc. can be used. As a method for forming the bumps, a so-called wet bump method can be used in which a barrier layer and an adhesive layer are formed on an aluminum bonding pad in a wafer state by a thin film, PEP process, and bumps are formed by electroplating. Furthermore, it is also possible to form bumps using a so-called transfer bump method in which bumps are formed on another support base in the same manner as described above and then transferred to the semiconductor element side. In this example, a semiconductor element having Au bumps formed by a wet bump method was used. Pump size is 85 x 85 μm 1 height is 18 μm ± 2
The number of bumps per μm is 99, and the minimum bump pitch is 130 μm.
It is m.
接続用突起電極１３の形成方法としては、半導体素子を
接続用突起電極の合金溶融液中に浸漬して形成する所謂
デイツプ法、又は第２図に示す転写法を用いることがで
きる。ここで、転写法では、第２図（ａ）（ｂ）に示し
たように、厚さ数１０μｍのインジウム、スズ、鉛及び
銀等を含む金属シート４２を形成した基板４１を用意し
、半導体素子１１を加熱しながら金属シート４２に加圧
・圧着し、数秒〜数１０秒間保持する。その後、そのま
ま引き上げると、第２図（ｅ）に示す如く、Ａｕバンプ
１２上に先端が尖った針状の接続用突起電極１３が形成
される。また、接続用突起電極］３は、デイツプ法、転
写法によってバリアメタルの上に直接形成することも可
能である。As a method for forming the connecting protruding electrodes 13, the so-called dip method, in which the semiconductor element is immersed in an alloy melt of the connecting protruding electrodes, or the transfer method shown in FIG. 2 can be used. Here, in the transfer method, as shown in FIGS. 2(a) and 2(b), a substrate 41 on which a metal sheet 42 containing indium, tin, lead, silver, etc. with a thickness of several tens of micrometers is formed is prepared, and a semiconductor The element 11 is pressed and bonded to the metal sheet 42 while being heated, and held for several seconds to several tens of seconds. Thereafter, when it is pulled up as it is, a needle-shaped connecting protrusion electrode 13 with a sharp tip is formed on the Au bump 12, as shown in FIG. 2(e). Further, the connecting protruding electrode] 3 can also be formed directly on the barrier metal by a dip method or a transfer method.
本実施例では、接続用突起電極１３としてイ］３
ンジウム・スズ合金を用いてデイツプ法により形成した
。このとき、予めロジン系のフラックスを半導体素子の
表面に塗布したのち、１８０ ’Ｃのインジウム・スズ
合金溶融液中に半導体素子をデイツプした後、有機洗浄
を行いＡｕバンプ電極１２上に接続用突起電極１３を形
成した。In this example, the connecting protruding electrode 13 was formed by the dip method using an indium-tin alloy. At this time, after applying rosin-based flux to the surface of the semiconductor element in advance, the semiconductor element is dipped in an indium-tin alloy melt at 180'C, organic cleaning is performed, and connection protrusions are formed on the Au bump electrodes 12. Electrode 13 was formed.
ここでは、接続用突起電極１３を半導体素子１１側に形
成したが、同様の方法を導体配線パターン２２側に行っ
て接続用突起電極１３を形成しても同じである。Here, the connection protrusion electrode 13 is formed on the semiconductor element 11 side, but the same method can be applied to form the connection protrusion electrode 13 on the conductor wiring pattern 22 side.
半導体素子１１の接続用突起電極１３と絶縁基板２１上
の導体配線パターン２２とは、位置合せを行った後、半
導体素子１］及び絶縁基板２１を接続用突起電極１３の
融点以下の温度に加熱しながら加圧することにより接続
することができ、これにより半導体素子１１と導体配線
パターン２２との電気的接続及び機械的接続を得ること
ができる。この接続用突起電極１３は適当な加圧により
塑性変形するため、導体配線パターン２２の表面や接続
用突起電極１３の表４
面の酸化膜が除去され、電気的１機械的な接続を良好に
行うことができる。After the protruding electrodes 13 for connection of the semiconductor element 11 and the conductor wiring pattern 22 on the insulating substrate 21 are aligned, the semiconductor element 1] and the insulating substrate 21 are heated to a temperature below the melting point of the protruding electrodes 13 for connection. The connection can be made by pressurizing the semiconductor element 11 and the conductive wiring pattern 22, thereby achieving electrical and mechanical connection between the semiconductor element 11 and the conductor wiring pattern 22. Since the connecting protruding electrode 13 is plastically deformed by applying appropriate pressure, the oxide film on the surface of the conductor wiring pattern 22 and the front surface of the connecting protruding electrode 13 is removed, and good electrical and mechanical connections are achieved. It can be carried out.
接合温度が接続用突起電極１３の融点以下であるのは、
本実施例のようにインジウム・スズ合金を用いた場合に
は、第３図に示すように固相温度以上の１２０℃及び液
相温度以上の１３５℃では接合時における不良率が増え
、からである。The reason why the bonding temperature is below the melting point of the connection protrusion electrode 13 is because
When an indium-tin alloy is used as in this example, as shown in Figure 3, the defect rate increases during bonding at 120°C above the solidus temperature and 135°C above the liquidus temperature. be.
これは、接続用突起電極１３がそれの融点以上では半導
体素子１１と導体配線パターン２２との接続の前に既に
溶けており、従って接続用突起電極１３の塑性変成によ
る酸化膜の除去が充分に発揮できないためである。This is because the connecting protruding electrode 13 is already melted before the connection between the semiconductor element 11 and the conductive wiring pattern 22 at temperatures above its melting point, and therefore the oxide film due to plastic deformation of the connecting protruding electrode 13 is not sufficiently removed. This is because they cannot perform to their full potential.
本実施例では、接続時の条件として、半導体素子１１を
１１０℃、絶縁基板２１を６０℃に加熱し、１パッド当
り１５ｇの加圧力、時間５秒にて圧着接合した。加圧力
に関してもワイヤーボンディング法、ＴＡＢ法の１バン
プ当り５０ｇ以上より低く行えるので、半導体素子１１
及び絶縁基板２１へのダメージを小さくすることができ
た。In this example, the conditions for connection were that the semiconductor element 11 was heated to 110° C., the insulating substrate 21 was heated to 60° C., and pressure bonding was performed at a pressure of 15 g per pad for 5 seconds. The pressing force can be lower than 50 g or more per bump in the wire bonding method and TAB method, so the semiconductor device 11
And damage to the insulating substrate 21 could be reduced.
５
ここで、加圧力の最適条件を求めるために、テスト用の
ＬＳＩチップとガラス基板を用い、接続時の荷重と抵抗
、不良率の関係を調べた。5. Here, in order to find the optimal conditions for the pressurizing force, we used a test LSI chip and a glass substrate to examine the relationship between the load during connection, resistance, and defective rate.
テスト用ＬＳＩの接続用電極パッドの大きさは８５μｍ
角、７７μｍ間隔（１６２μｍピッチ）で、その数は９
９個である。接続抵抗は、ガラス基板上の接続電極から
４本の配線が出ている。接続部に一定電流を流し、これ
らの配線を使い４端子法のように電流と電圧を測定する
。接続抵抗値が１００以上を不良と判定した。The size of the connection electrode pad of the test LSI is 85 μm.
corner, 77 μm apart (162 μm pitch), the number is 9
There are 9 pieces. The connection resistor has four wires coming out from the connection electrode on the glass substrate. A constant current is passed through the connections, and the current and voltage are measured using these wires like the four-terminal method. A connection resistance value of 100 or more was determined to be defective.
加圧は１チップ当り ０．５〜３ ｋｇの範囲で変えた
。ＬＳＩチップを１１５〜１２５℃、ガラス基板は５５
〜６０℃に加熱した状態で接続する。実装する基板側も
加熱した方が、ＬＳＩチップとの温度差が小さく接合部
への応力も小さいためである。接続時間は１０秒以下と
短い。The pressure was varied in the range of 0.5 to 3 kg per chip. LSI chip at 115-125℃, glass substrate at 55℃
Connect while heated to ~60°C. This is because heating the board to be mounted also reduces the temperature difference with the LSI chip and reduces the stress on the bonding portion. Connection time is short, less than 10 seconds.
第５図に示すように、加圧力が１チップ当り０．５ｋｇ
のときは接続できないが、１〜３ｋｇの範囲では接続不
良が殆ど発生していない。このとき、８５μｍ角のＩｎ
合金（接続用突起電極）が６
潰れて広がる面積は１００μｍ角程度と小さく、隣接し
たバンプ同士が接触する可能性は極めて少ない。接続抵
抗は平均１Ω／バンプ以下であり、良好な接続が得られ
ることが判った。なかでも、１．５〜２ｋｇ／チップの
範囲は、平均的に接続抵抗の平均値が低く、さらにバラ
つきも小さく最適である。１チツプに９９個バンプを付
けているため、１バンプ当りの加圧力は１５〜２０ｇに
なる。従来のワイヤーボンディングやＴＡＢに比べｌ／
３以下の荷重であるため、ＬＳＩチップに与える損傷も
少ない。As shown in Figure 5, the pressure is 0.5 kg per chip.
However, in the range of 1 to 3 kg, there are almost no connection failures. At this time, an 85 μm square In
The area where the alloy (projection electrode for connection) is crushed and expanded is as small as about 100 μm square, and the possibility that adjacent bumps will come into contact with each other is extremely small. The connection resistance was on average 1Ω/bump or less, indicating that a good connection could be obtained. Among these, the range of 1.5 to 2 kg/chip is optimal because the average value of connection resistance is low and the variation is also small. Since 99 bumps are attached to one chip, the pressing force per bump is 15 to 20 g. l/ compared to conventional wire bonding and TAB
Since the load is 3 or less, there is little damage to the LSI chip.
また、接続用突起電極１３に用いるインジウム、スズ、
鉛及び銀等の効果について述べると、スズ・鉛合金は一
般的に固相温度が１８３℃と低く、特に液晶パネル等へ
の接続を考えた場合には接合温度を１８０℃以下にでき
るため、液晶パネル等への温度によるダメージを少なく
することができる。この効果は、液晶パネル上に駆動用
の半導体素子を直接実装することを可能とするため、液
晶パネルを用いた電子機器の高密度７
化及び小型化に極めて有効である。また、スズ・鉛合金
は柔らかいので、接続による半導体素子１１及び絶縁基
板２１へのダメージを少なくすることができる。さらに
、インジウムを用いることによって合金の固相温度を下
げることができ、合金自身も柔らかくなるので接続によ
るダメージを一層少なくできる。一方、銀を添加するの
は導体配線材料として例えば、銀バラジニウム。銀白金
、銀自身等の銀系の材料を用いたときに、拡散防止効果
が顕著であることによる。In addition, indium, tin,
Regarding the effects of lead, silver, etc., tin-lead alloys generally have a low solidus temperature of 183℃, and especially when considering connection to liquid crystal panels, etc., the bonding temperature can be lowered to 180℃ or less. Damage to liquid crystal panels and the like due to temperature can be reduced. This effect makes it possible to directly mount driving semiconductor elements on the liquid crystal panel, and is therefore extremely effective in increasing the density and downsizing of electronic devices using liquid crystal panels. Furthermore, since the tin-lead alloy is soft, damage to the semiconductor element 11 and the insulating substrate 21 due to connection can be reduced. Furthermore, by using indium, the solidus temperature of the alloy can be lowered, and the alloy itself becomes softer, so that damage caused by connections can be further reduced. On the other hand, silver is added to conductor wiring materials such as silver valadinium. This is because when a silver-based material such as silver platinum or silver itself is used, the diffusion prevention effect is remarkable.
また、本実施例では、第１図（ｅ）に示す樹脂含浸工程
の前に、半導体素子１１と導体配線パターン２２との電
気的検査を、ブロービング等によって行う。このとき、
半導体素子１１の不良や接続不良等が生じていた場合、
半導体素子１１と絶縁基板２１とは１素子あたり ２５
０ｇ ｆ以上の剪断力を加えれば容易に剥すことができ
、導体配線パターン２２上に残った接続用突起電極１３
を溶剤等で拭き落とせば、絶縁基板２１８
を再使用することができる。従って、従来方法のように
樹脂がある場合に比べ、遥かに容易にリペア−ができる
。Furthermore, in this embodiment, before the resin impregnation step shown in FIG. 1(e), the semiconductor element 11 and the conductor wiring pattern 22 are electrically inspected by blowing or the like. At this time,
If there is a defect in the semiconductor element 11 or a poor connection,
The semiconductor element 11 and the insulating substrate 21 are 25 per element.
It can be easily peeled off by applying a shearing force of 0 g f or more, and the connecting protruding electrode 13 remaining on the conductor wiring pattern 22
The insulating substrate 218 can be reused by wiping it off with a solvent or the like. Therefore, repair can be performed much more easily than in the conventional method where resin is used.
電気検査で異常がなければ、第１図（Ｃ）のように半導
体素子１１と絶縁基板２１との間に樹脂１４を含浸する
。この時の樹脂は、例えばエポキシ樹脂、フェノール樹
脂、シリコーン樹脂。If there is no abnormality in the electrical test, a resin 14 is impregnated between the semiconductor element 11 and the insulating substrate 21 as shown in FIG. 1(C). Examples of the resin at this time include epoxy resin, phenol resin, and silicone resin.
ポリイミド樹脂、アクリル樹脂、熱硬化型１２ポリブタ
ジエン樹脂等の熱或いは光硬化性樹脂である。樹脂は粘
度が５００ｃｐｓ程度であれば毛細管現像によって素早
く含浸される。室温で粘度が高い樹脂であっても数１０
度に加温するか、或いは１０−’Ｔｏｒｒ程度に減圧す
れば容易に含浸させることができる。It is a heat or photo-curable resin such as polyimide resin, acrylic resin, thermosetting 12 polybutadiene resin, etc. If the resin has a viscosity of about 500 cps, it can be quickly impregnated by capillary development. Even for resins with high viscosity at room temperature, the number of
Impregnation can be easily carried out by heating to a certain temperature or by reducing the pressure to about 10-'Torr.
本実施例では、熱硬化性エポキシ樹脂を用いて６０℃に
加熱して含浸した。樹脂含浸後、所定の条件で硬化させ
ることにより電気的１機械的接続の信頼性を高めること
ができる。このとき、ニッケルパターンと半導体素子の
接触抵抗は１バンプ当り平均１Ω以下であり、樹脂の含
浸硬 ９
化による不良の発生はなかった。接続用突起電極はその
合金自身を直接デイツプ或いは転写によって形成するの
で、銀ペースト法等のバインダー樹脂を含むものより接
触抵抗が低く且つ信頼性が高い。In this example, a thermosetting epoxy resin was used and heated to 60° C. for impregnation. After resin impregnation, the reliability of electrical and mechanical connections can be increased by curing under predetermined conditions. At this time, the contact resistance between the nickel pattern and the semiconductor element was on average 1 Ω or less per bump, and no defects were caused by impregnation and hardening of the resin. Since the connecting protruding electrodes are formed by directly dipping or transferring the alloy itself, the contact resistance is lower and the reliability is higher than that using a binder resin such as the silver paste method.
さらに、テストサンプルを作って一４０〜１００℃で１
サイクル各３０分の熱衝撃試験を３００サイクル行った
ところ、第６図（ｂ）に示す結果が得られた。そして、
３００サイクル後の接触抵抗値も平均１Ω以下であった
。また、７０℃、９０％Ｒ，Ｈの高温高湿試験を５００
時間行ったところ、第６図（ａ）に示すような結果が得
られた。そして、５００時間後の接触抵抗も平均１Ω以
下であった。なお、熱衝撃試験では接続抵抗が僅かなが
ら減少しているが、これは樹脂の収縮と考えられる。し
かし、全体的には接続抵抗の変動が少なく安定している
。Furthermore, a test sample was made and
When a thermal shock test was conducted for 300 cycles of 30 minutes each, the results shown in FIG. 6(b) were obtained. and,
The contact resistance value after 300 cycles was also 1Ω or less on average. In addition, we conducted a high temperature and high humidity test at 70°C, 90% R and H for 500
After testing for several hours, the results shown in FIG. 6(a) were obtained. The contact resistance after 500 hours was also 1Ω or less on average. Note that in the thermal shock test, the connection resistance decreased slightly, but this is thought to be due to resin contraction. However, overall, the connection resistance is stable with little variation.
〈比較例〉
上述の実施例と同様に、絶縁基板２１としての厚さ１．
１ｍｍのソーダライムガラス基板上に０
Ｓｉｎ２を約１００人デイツプ形成した後、ＩＴＯを厚
さ１０００人蒸着し、５０００人のニッケルの無電解メ
ツキを行い導体配線パターン２２を形成したものを用い
た。一方、半導体素子１１は、アルミボンディンブパッ
ド上に湿式バンプ法で金バンプ電極１２を有し、さらに
接続用突起電極１３としてインジウム・スズ合金をデイ
ツプ法によって形成した素子を使用した。<Comparative Example> As in the above embodiment, the thickness of the insulating substrate 21 was 1.
After about 100 layers of 0 Sin2 were formed on a 1 mm soda lime glass substrate, ITO was deposited to a thickness of 1000 layers, and electroless plating of 5000 layers of nickel was performed to form a conductive wiring pattern 22. On the other hand, the semiconductor element 11 had a gold bump electrode 12 formed on an aluminum bonding pad by a wet bump method, and an indium-tin alloy was formed as a connecting protrusion electrode 13 by a dip method.
次いで、半導体素子１１を接続用突起電極１３の融点（
１２０℃）以上である １２５℃に加熱し、また該絶縁
基板２１を６０℃に保ち、接合力１５ｇ／パッド、接合
時間を５秒で圧着接合した。Next, the melting point (
The insulating substrate 21 was heated to 125° C. (120° C.) or higher, and the insulating substrate 21 was kept at 60° C., and pressure bonding was performed with a bonding force of 15 g/pad and a bonding time of 5 seconds.
その結果、前記第３図に示したように９９パツドのうち
３０パツドで接続不良が生じ、接続用突起電極１３の融
点以上の温度で接合した場合に十分な信頼性が得られな
いことが判った。As a result, as shown in FIG. 3, 30 out of 99 pads had connection failures, indicating that sufficient reliability could not be obtained when bonding was performed at a temperature higher than the melting point of the connection protrusion electrode 13. Ta.
かくして本実施例によれば、半導体素子１１と導体配線
パターン２２との接続を接続用突起電極１３の融点以下
で行うために、接続用突起電極１３の塑性変形によって
、それ自身及び導１
体配線パターン２２の酸化膜を除去することができる。Thus, according to this embodiment, in order to connect the semiconductor element 11 and the conductor wiring pattern 22 at a temperature below the melting point of the connection protrusion electrode 13, the connection protrusion electrode 13 is plastically deformed to form a connection between itself and the conductor wiring pattern 22. The oxide film of the pattern 22 can be removed.
従って、その電気的１機械的接続を取ることができる。Therefore, the electrical and mechanical connections can be made.
さらに、樹脂１４を含浸させることによって、接続の信
頼性を向上させることができる。また、樹脂１４を充填
する前に電気的検査を行えるので、不良が生じた場合の
りペアーが極めて容易である。また、位置合せ機構の付
いた機械の専有時間を短くできるので、生産性を上げる
ことができる。また、圧接接合と樹脂を含浸硬化させる
のみであるから、実装工程が簡単でありコストを低減で
きる等の利点がある。Furthermore, by impregnating the resin 14, the reliability of the connection can be improved. Furthermore, since an electrical test can be performed before filling the resin 14, it is extremely easy to repair the glue pair if a defect occurs. Furthermore, since the exclusive use time of the machine equipped with the positioning mechanism can be shortened, productivity can be increased. Furthermore, since only pressure bonding and resin impregnation and curing are required, the mounting process is simple and costs can be reduced.
次に、本発明の第２の実施例について説明する。第４図
は同実施例に係わる半導体装置の製造工程を示す断面図
である。Next, a second embodiment of the present invention will be described. FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the same embodiment.
まず、先の実施例と同様に、半導体素子１１にＡｕバン
プ電極１２を形成する。Ａｕバンプ電極１２の形成には
、先にも説明したように湿式バンプ法や転写バンプ方式
を用いることができる。本実施例では、湿式バンプ法で
形成し、２
Ａｕバンプのサイズは８５Ｘ８５μｍ１高さは１８±２
μｍ１バンプ数は９９個、最小バンプピッチは１３０μ
ｍとした。First, as in the previous embodiment, Au bump electrodes 12 are formed on the semiconductor element 11. For forming the Au bump electrodes 12, the wet bump method or the transfer bump method can be used as described above. In this example, the wet bump method was used to form the Au bumps, and the size of the two Au bumps was 85 x 85 μm and the height was 18 ± 2.
The number of bumps per μm is 99, and the minimum bump pitch is 130 μm.
It was set as m.
次いで、第４図（ａ） （ｂ）に示す工程で、半導体素
子１１のバンプ電極１２上に接続用突起電極１３を形成
する。即ち、ロジン系フラックスを半導体素子１１の表
面に塗布した後、第４図（ａ）に示す如く、容器５１内
に充填された金属電極溶融体５２中に半導体素子１１の
表面（バンプ電極側）をデイツプする。溶融体５２とし
てはインジウム・スズ合金を用い、このときの形成条件
は、デイツプ温度１８３℃、デイツプ時間３ ｓｅｃと
した。次いで、第４図（ｂ）に示す如く、半導体素子１
１を溶融体５２から引上げ、半導体素子１１の表面に付
着したフラックスを適当な有機用材で洗浄除去した。こ
れにより、バンプ電極１２上に球状の接続用突起電極１
３が形成された。Next, in the steps shown in FIGS. 4(a) and 4(b), connecting protruding electrodes 13 are formed on the bump electrodes 12 of the semiconductor element 11. That is, after applying the rosin-based flux to the surface of the semiconductor element 11, as shown in FIG. Deepen. An indium-tin alloy was used as the melt 52, and the forming conditions at this time were a dip temperature of 183° C. and a dip time of 3 seconds. Next, as shown in FIG. 4(b), the semiconductor element 1
1 was pulled up from the melt 52, and the flux adhering to the surface of the semiconductor element 11 was washed away with an appropriate organic material. As a result, the spherical connection protrusion electrode 1 is placed on the bump electrode 12.
3 was formed.
次いで、第４図（ｃ）に示すように、絶縁基板２１を支
持台３２上に載置し、絶縁基板２１上３
に形成された導体配線パターン２２と、半導体素子１１
のバンプ電極１２上に形成された接続用突起電極１３と
を位置合せして接触させる。Next, as shown in FIG. 4(c), the insulating substrate 21 is placed on the support stand 32, and the conductor wiring pattern 22 formed on the insulating substrate 21 and the semiconductor element 11 are placed on the support base 32.
The connecting projection electrodes 13 formed on the bump electrodes 12 are aligned and brought into contact with each other.
この状態で、加熱ヘッド３１により半導体素子１１を絶
縁基板２１側に押圧すると共に、接続用突起電極１３を
その融点以下の温度に加熱する。このとき、加熱、加圧
条件を適当に設定すれば、電極１３はバンプ電極１２の
側面まで回り込むことになる。そして、バンプ電極１２
と配線パターン２２とは、インジウム・スズ合金からな
る接続用突起電極１３を介して接合されることになる。In this state, the heating head 31 presses the semiconductor element 11 toward the insulating substrate 21 and heats the connecting protruding electrode 13 to a temperature below its melting point. At this time, if the heating and pressurizing conditions are set appropriately, the electrode 13 will wrap around to the side surface of the bump electrode 12. Then, the bump electrode 12
and the wiring pattern 22 are connected to each other via the connection protrusion electrode 13 made of an indium-tin alloy.
加熱・加圧による接合を終了した後は、前記第１図（ｅ
）に示す如く、半導体素子１１と絶縁基板２１との隙間
に熱硬化性樹脂１４を含浸させ、これに熱を加えて硬化
させることにより、半導体素子１１の絶縁基板２１への
マウント（フェイスダウンボンディング）が終了する。After completing the bonding by heating and pressurizing, the process shown in FIG.
), by impregnating the gap between the semiconductor element 11 and the insulating substrate 21 with a thermosetting resin 14 and curing it by applying heat, the semiconductor element 11 is mounted on the insulating substrate 21 (face-down bonding). ) ends.
なお、熱硬化性樹脂は必ずしも接合工程後に用いる必要
はなく、第４図（Ｃ）に示す工程の前に４
絶縁基板２１上に配置しておいてもよい。Note that the thermosetting resin does not necessarily need to be used after the bonding step, and may be placed on the insulating substrate 21 before the step shown in FIG. 4(C).
かくして本実施例によれば、先の実施例と同様に、接続
用突起電極１３を用いて半導体素子１１のバンプ電極１
２と基板２１の導体配線パターン２２との電気的１機械
的接続を取ることができる。さらに、樹脂１４を含浸さ
せることによる接続の信頼性向上、不良が生じた場合の
りペアーの容易化、生産性の向上、コストの低減化等を
はかることができる。これに加えて、接続用突起電極１
３がバンプ電極１２の側面に回り込んだ構成となってい
るので、バンプ電極１２と接続用突起電極１３との接続
安定性の向上、さらにはこれらの接触抵抗の低減をはか
り得る利点がある。Thus, according to this embodiment, as in the previous embodiment, the bump electrode 1 of the semiconductor element 11 is connected using the connection protrusion electrode 13.
2 and the conductive wiring pattern 22 of the substrate 21 can be electrically and mechanically connected. Furthermore, by impregnating the resin 14, it is possible to improve the reliability of the connection, facilitate the pairing of adhesives in the event of a defect, improve productivity, and reduce costs. In addition to this, connection protrusion electrode 1
3 wraps around the side surface of the bump electrode 12, which has the advantage of improving the connection stability between the bump electrode 12 and the connection protrusion electrode 13, and further reducing the contact resistance between them.
なお、本発明は上述した実施例に限定されるものではな
く、その要旨を逸脱しない範囲で、種々変形して実施す
ることができる。Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof.
［発明の効果］
以上詳述したように本発明によれば、半導体素子と絶縁
性基板とを樹脂で接着するのではな５
く、接続用突起電極によって接続し、これに加えて樹脂
の含浸により接続強度を補強しているので、半導体素子
のフェイスダウンボンディングを良好に行い得ると共に
、接続の信頼性を高くすることができ、またリペア−の
ための半導体素子の交換を容易にすることができる。[Effects of the Invention] As detailed above, according to the present invention, the semiconductor element and the insulating substrate are not bonded with resin, but are connected by protruding connection electrodes, and in addition, impregnated with resin. Since the connection strength is reinforced, it is possible to perform face-down bonding of semiconductor elements well, increase the reliability of the connection, and facilitate the replacement of semiconductor elements for repair. can.
第１図は本発明の第１の実施例に係わる半導体装置の製
造工程を示す断面図、第２図は接続用突起電極の形成方
法を説明するための工程断面図、第３図は半導体素子と
導体配線パターンの接合温度と接合不良率の関係を示す
特性図、第４図は本発明の第２の実施例を説明するため
の工程断面図、第５図は加圧力に対する抵抗不良率及′
び接続抵抗の変化を示す特性図、第６図は試験時間及び
試験サイクルに対する接続抵抗の変化を示す特性図、第
７図は従来の半導体装置の製造工程を示す断面図である
。
１１・・・半導体素子、
１２・・・バンプ電極、
６
３・・・接続用突起電極、
４・・・樹脂、
１・・・絶縁基板、
２・・・導体配線パターン、
１・・・加熱ヘッド、
２・・・支持台、
１・・・基板、
２・・・金属ジート
ド・・容器、
２・・・金属溶融体。FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to the first embodiment of the present invention, FIG. 2 is a process sectional view illustrating a method of forming a connection protrusion electrode, and FIG. 3 is a semiconductor device. FIG. 4 is a process sectional view for explaining the second embodiment of the present invention, and FIG. ′
FIG. 6 is a characteristic diagram showing changes in connection resistance with respect to test time and test cycles, and FIG. 7 is a cross-sectional view showing the manufacturing process of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 11... Semiconductor element, 12... Bump electrode, 6 3... Protruding electrode for connection, 4... Resin, 1... Insulating substrate, 2... Conductor wiring pattern, 1... Heating Head, 2...Support stand, 1...Substrate, 2...Metal jet container, 2...Metal molten body.
Claims (8)
フェイスダウンでマウントした半導体装置において、前
記半導体素子の電極上に金バンプが設けられ、この金バ
ンプと前記配線パターンとがインジウムを含む金属を介
して接合されてなることを特徴とする半導体装置。(1) In a semiconductor device in which a semiconductor element is mounted face down on a substrate on which a wiring pattern is formed, gold bumps are provided on the electrodes of the semiconductor element, and the gold bumps and the wiring pattern are made of a metal containing indium. A semiconductor device characterized in that the semiconductor device is bonded via a.
板上に設けた配線パターンとをインジウムを含む金属を
介して接合してなる半導体装置であって、前記インジウ
ムを含む金属は、前記金バンプの配線パターンとの接合
面側の側面まで到達するように設けられていることを特
徴とする半導体装置。(2) A semiconductor device in which a gold bump provided on an electrode of a semiconductor element and a wiring pattern provided on a wiring board are bonded via a metal containing indium, wherein the metal containing indium is A semiconductor device characterized in that the gold bumps are provided so as to reach the side surface of the bonding surface with the wiring pattern.
装置において、前記半導体素子の電極上に金バンプが設
けられ、前記液晶パネル上に配線パターンが設けられ、
金バンプと配線パターンとがインジウムを含む金属によ
り接合されてなることを特徴とする半導体装置。(3) In a semiconductor device in which a semiconductor element is mounted on a liquid crystal panel, gold bumps are provided on the electrodes of the semiconductor element, and a wiring pattern is provided on the liquid crystal panel,
A semiconductor device characterized in that a gold bump and a wiring pattern are bonded by a metal containing indium.
、前記半導体素子の金バンプ側をインジウムを含む金属
の溶液中に浸漬する工程と、前記インジウムを含む金属
の溶液から前記半導体素子を離間して該素子の金バンプ
上にインジウムを含む球面状の金属を形成する工程と、
前記半導体素子の球面状の金属と前記配線基板の配線パ
ターンとを接触させ、これらを加熱、加圧して接合する
工程とを含むことを特徴とする半導体装置の製造方法。(4) forming gold bumps on the electrodes of a semiconductor element; immersing the gold bump side of the semiconductor element in a metal solution containing indium; and removing the semiconductor element from the indium-containing metal solution. forming a spherical metal containing indium on the gold bumps of the element at a distance;
A method for manufacturing a semiconductor device, comprising the step of bringing a spherical metal of the semiconductor element into contact with a wiring pattern of the wiring board, and bonding them by heating and pressurizing them.
、インジウムを含む金属をシート状にしたシート部材に
、加熱された半導体素子の金バンプ側を接触させる工程
と、前記シート部材から前記半導体素子を離間して該素
子の金バンプ上にインジウムを含む針状の金属を形成す
る工程と、前記半導体素子の針状の金属と前記配線基板
の配線パターンとを接触させ、これらを加熱、加圧して
接合する工程とを含むことを特徴とする半導体装置の製
造方法。(5) forming gold bumps on the electrodes of the semiconductor element; bringing the heated gold bump side of the semiconductor element into contact with a sheet member made of a metal containing indium; a step of separating the semiconductor element and forming an acicular metal containing indium on the gold bump of the element; bringing the acicular metal of the semiconductor element into contact with the wiring pattern of the wiring board; heating them; 1. A method for manufacturing a semiconductor device, comprising the step of bonding by applying pressure.
ントするに際し、前記半導体素子に形成された接続用突
起電極と前記絶縁基板上に形成された配線パターンとを
位置合わせし、これらを接続用突起電極の融点以下の温
度で加熱・加圧して接合する工程と、次いで前記半導体
素子と絶縁基板との隙間に光硬化性若しくは熱硬化性の
樹脂を含浸したのち、該樹脂を硬化させる工程とを含む
ことを特徴とする半導体装置の製造方法。(6) When mounting a semiconductor element face down on an insulating substrate, align the connection protrusion electrodes formed on the semiconductor element with the wiring pattern formed on the insulating substrate, and connect them to the connection protrusions. A step of bonding by heating and pressurizing at a temperature below the melting point of the electrode, and a step of impregnating a photocurable or thermosetting resin into the gap between the semiconductor element and the insulating substrate, and then curing the resin. A method of manufacturing a semiconductor device, comprising:
鉛若しくは銀、又はこれらの少なくとも２種の合金を用
い、該合金を前記半導体素子のバンプ電極上に形成した
ことを特徴とする請求項６記載の半導体装置の製造方法
。(7) As the connection protruding electrode, indium, tin,
7. The method of manufacturing a semiconductor device according to claim 6, wherein lead, silver, or an alloy of at least two thereof is used, and the alloy is formed on the bump electrode of the semiconductor element.
性を低くするか、又は前記半導体素子及び絶縁基板を減
圧下に置くことを特徴とする請求項６記載の半導体装置
の製造方法。(8) The method of manufacturing a semiconductor device according to claim 6, wherein when impregnating the resin, the resin is heated to lower its viscosity, or the semiconductor element and the insulating substrate are placed under reduced pressure.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/477,504 US5071787A (en) | 1989-03-14 | 1990-02-09 | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
| DE69022087T DE69022087T2 (en) | 1989-03-14 | 1990-02-14 | Method of manufacturing a semiconductor device. |
| EP90301542A EP0388011B1 (en) | 1989-03-14 | 1990-02-14 | Method of manufacturing a semiconductor device. |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-61634 | 1989-03-14 | ||
| JP6163489 | 1989-03-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03108734A true JPH03108734A (en) | 1991-05-08 |
| JP2755696B2 JP2755696B2 (en) | 1998-05-20 |
Family
ID=13176824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1163196A Expired - Fee Related JP2755696B2 (en) | 1989-03-14 | 1989-06-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2755696B2 (en) |
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| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
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| JP2007165671A (en) * | 2005-12-15 | 2007-06-28 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| RU2571436C1 (en) * | 2014-10-20 | 2015-12-20 | Российская Федерация, От Имени Которой Выступает Министерство Промышленности И Торговли Российской Федерации | Method for manufacturing indium microcontacts |
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| RU2571436C1 (en) * | 2014-10-20 | 2015-12-20 | Российская Федерация, От Имени Которой Выступает Министерство Промышленности И Торговли Российской Федерации | Method for manufacturing indium microcontacts |
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|---|---|
| JP2755696B2 (en) | 1998-05-20 |
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