JPH098207A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPH098207A
JPH098207A JP7176898A JP17689895A JPH098207A JP H098207 A JPH098207 A JP H098207A JP 7176898 A JP7176898 A JP 7176898A JP 17689895 A JP17689895 A JP 17689895A JP H098207 A JPH098207 A JP H098207A
Authority
JP
Japan
Prior art keywords
inner lead
lead frame
lead
resin
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7176898A
Other languages
Japanese (ja)
Inventor
Junichi Yamada
淳一 山田
Masaru Sasaki
賢 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP7176898A priority Critical patent/JPH098207A/en
Publication of JPH098207A publication Critical patent/JPH098207A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: To provide a resin sealed semiconductor device which can cope with the increased number of terminals and can be reduced more in size by providing the electrode sections of semiconductor elements between inner leads and electrically connecting the electrode sections to the front ends of inner leads on the side opposite to the semiconductor element mounting side through wires. CONSTITUTION: A semiconductor element 110 is mounted on and fixed to inner leads 131 with an insulating adhesive material 150 so that an electrode section (pad) 111 on the electrode section 111 side surface of the element 110 can be put between the leads 131. The electrode section 111 is electrically connected to the second surfaces 31Ab of the leads 131 at the front ends of inner lead sections 131 through wires 120. The thickness of the inner lead sections 131 is adjusted to 40μm and the thickness of portion other than the sections 131 is maintained at the thickness of a lead frame material which is 0.15mm. The arranging pitch of the inner leads is adjusted to as narrow as 0.12mm so that the number of terminals can be increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は，半導体装置の多端子化
に対応でき、且つ、実装性の良い小型化が可能な樹脂封
止型半導体装置に関するもので、特に、エッチング加工
により、インナーリード部をリードフレーム素材の厚さ
よりも薄肉に外形加工したリードフレームを用いた樹脂
封止型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device capable of accommodating a large number of terminals of a semiconductor device and having good mountability and, more particularly, to an inner lead formed by etching. The present invention relates to a resin-encapsulated semiconductor device using a lead frame whose outer portion is processed to be thinner than the thickness of the lead frame material.

【０００２】[0002]

【従来の技術】従来より用いられている樹脂封止型の半
導体装置（プラスチックリードフレームパッケージ）
は、一般に図１１（ａ）に示されるような構造であり、
半導体素子１１２０を搭載するダイパッド部１１１１や
周囲の回路との電気的接続を行うためのアウターリード
部１１１３、アウターリード部１１１３に一体となった
インナーリード部１１１２、該インナーリード部１１１
２の先端部と半導体素子１１２０の電極パッド１１２１
とを電気的に接続するためのワイヤ１１３０、半導体素
子１１２０を封止して外界からの応力、汚染から守る樹
脂１１４０等からなっており、半導体素子１１２０をリ
ードフレームのダイパッド１１１１部等に搭載した後
に、樹脂１１４０により封止してパッケージとしたもの
で、半導体素子１１２０の電極パッド１１２１に対応で
きる数のインナーリード１１１２を必要とするものであ
る。そして、このような樹脂封止型の半導体装置の組立
部材として用いられる（単層）リードフレームは、一般
には図１１（ｂ）に示すような構造のもので、半導体素
子を搭載するためのダイパッド１１１１と、ダイパッド
１１１１の周囲に設けられた半導体素子と結線するため
のインナーリード１１１２、該インナーリード１１１２
に連続して外部回路との結線を行うためのアウターリー
ド１１１３、樹脂封止する際のダムとなるダムバー１１
１４、リードフレーム１１１０全体を支持するフレーム
（枠）部１１１５等を備えており、通常、コバール、４
２合金（４２％ニッケル−鉄合金）、銅系合金のような
導電性に優れた金属を用い、プレス法もしくはエッチン
グ法により形成されていた。2. Description of the Related Art Conventionally used resin-encapsulated semiconductor devices (plastic lead frame packages)
Generally has a structure as shown in FIG.
An outer lead portion 1113 for making electrical connection with a die pad portion 1111 on which the semiconductor element 1120 is mounted, a peripheral circuit, an inner lead portion 1112 integrated with the outer lead portion 1113, and the inner lead portion 111.
2 and the electrode pad 1121 of the semiconductor element 1120
And a wire 1130 for electrically connecting the semiconductor element 1120 and a resin 1140 for sealing the semiconductor element 1120 to protect the semiconductor element 1120 from external stress and contamination. The semiconductor element 1120 is mounted on the die pad 1111 of the lead frame and the like. Later, it is sealed with resin 1140 to form a package, which requires a number of inner leads 1112 corresponding to the electrode pads 1121 of the semiconductor element 1120. A (single layer) lead frame used as an assembly member for such a resin-sealed semiconductor device generally has a structure as shown in FIG. 11B, and has a die pad for mounting a semiconductor element. 1111, an inner lead 1112 for connecting to a semiconductor element provided around the die pad 1111, and the inner lead 1112
Outer lead 1113 for connecting to an external circuit continuously, and dam bar 11 to be a dam for resin sealing
14, a frame (frame) portion 1115 for supporting the entire lead frame 1110, and the like.
It was formed by a pressing method or an etching method using a metal having excellent conductivity such as 2 alloy (42% nickel-iron alloy) and copper alloy.

【０００３】このようなリードフレームを利用した樹脂
封止型の半導体装置（プラスチックリードフレームパッ
ケージ）においても、電子機器の軽薄短小化の時流と半
導体素子の高集積化に伴い、小型薄型化かつ電極端子の
増大化が顕著で、その結果、樹脂封止型半導体装置、特
にＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）及び
ＴＱＦＰ（Ｔｈｉｎ Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａ
ｇｅ）等では、リードの多ピン化が著しくなってきた。
上記の半導体装置に用いられるリードフレームは、微細
なものはフオトリソグラフイー技術を用いたエッチング
加工方法により作製され、微細でないものはプレスによ
る加工方法による作製されるのが一般的であったが、こ
のような半導体装置の多ピン化に伴い、リードフレーム
においても、インナーリード部先端の微細化が進み、当
初は、微細なものに対しては、プレスによる打ち抜き加
工によらず、リードフレーム部材の板厚が０．２５ｍｍ
程度のものを用い、エッチング加工で対応してきた。こ
のエッチング加工方法の工程について以下、図１０に基
づいて簡単に述べておく。先ず、銅合金もしくは４２％
ニッケル−鉄合金からなる厚さ０．２５ｍｍ程度の薄板
（リードフレーム素材１０１０）を十分洗浄（図１０
（ａ））した後、重クロム酸カリウムを感光剤とした水
溶性カゼインレジスト等のフオトレジスト１０２０を該
薄板の両表面に均一に塗布する。（（図１０（ｂ）） 次いで、所定のパターンが形成されたマスクを介して高
圧水銀灯でレジスト部を露光した後、所定の現像液で該
感光性レジストを現像して（図１０（ｃ））、レジスト
パターン１０３０を形成し、硬膜処理、洗浄処理等を必
要に応じて行い、塩化第二鉄水溶液を主たる成分とする
エッチング液にて、スプレイにて該薄板（リードフレー
ム素材１０１０）に吹き付け所定の寸法形状にエッチン
グし、貫通させる。（図１０（ｄ）） 次いで、レジスト膜を剥膜処理し（図１０（ｅ））、洗
浄後、所望のリードフレームを得て、エッチング加工工
程を終了する。このように、エッチング加工等によって
作製されたリードフレームは、更に、所定のエリアに銀
メッキ等が施される。次いで、洗浄、乾燥等の処理を経
て、インナーリード部を固定用の接着剤付きポリイミド
テープにてテーピング処理したり、必要に応じて所定の
量タブ吊りバーを曲げ加工し、ダイパッド部をダウンセ
ットする処理を行う。しかし、エッチング加工方法にお
いては、エッチング液による腐蝕は被加工板の板厚方向
の他に板幅（面）方向にも進むため、その微細化加工に
も限度があるのが一般的で、図１０に示すように、リー
ドフレーム素材の両面からエッチングするため、ライン
アンドスペース形状の場合、ライン間隔の加工限度幅
は、板厚の５０〜１００％程度と言われている。又、リ
ードフレームの後工程等のアウターリードの強度を考え
た場合、一般的には、その板厚は約０．１２５ｍｍ以上
必要とされている。この為、図１０に示すようなエッチ
ング加工方法の場合、リードフレームの板厚を０．１５
ｍｍ〜０．１２５ｍｍ程度まで薄くすることにより、ワ
イヤボンデイングのための必要な平坦幅７０〜８０確保
し、０．１６５ｍｍピッチ程度の微細なインナーリード
部先端のエッチングによる加工を達成してきたが、これ
が限度とされていた。Even in a resin-sealed semiconductor device (plastic lead frame package) using such a lead frame, the size and thickness of electrodes and electrodes have been reduced due to the trend of electronic devices becoming lighter, thinner, shorter and smaller, and higher integration of semiconductor elements. The number of terminals is remarkably increased, and as a result, a resin-sealed semiconductor device, particularly a QFP (Quad Flat Package) and a TQFP (Thin Quad Flat Package).
In the case of ge) and the like, the increase in the number of pins on the lead has become remarkable.
The lead frame used in the above-mentioned semiconductor device is generally manufactured by an etching method using a photolithographic technique for fine ones, and is generally manufactured by a pressing method for non-fine ones. With the increase in the number of pins of such semiconductor devices, miniaturization of the tips of the inner lead portions also progresses in the lead frame. Initially, for fine ones, the lead frame member Thickness is 0.25mm
We have dealt with the etching process by using some grade. The steps of this etching method will be briefly described below with reference to FIG. First, copper alloy or 42%
Thoroughly clean a thin plate (lead frame material 1010) of nickel-iron alloy with a thickness of about 0.25 mm (Fig. 10).
After (a)), a photoresist 1020 such as a water-soluble casein resist using potassium dichromate as a photosensitizer is uniformly applied to both surfaces of the thin plate. ((FIG. 10 (b)) Next, after exposing the resist portion with a high-pressure mercury lamp through a mask on which a predetermined pattern is formed, the photosensitive resist is developed with a predetermined developing solution (FIG. 10 (c)). ), A resist pattern 1030 is formed, hardening treatment, cleaning treatment, etc. are performed as necessary, and the thin plate (lead frame material 1010) is sprayed on the thin plate (lead frame material 1010) with an etching solution containing a ferric chloride aqueous solution as a main component. Then, the resist film is sprayed and etched into a predetermined size and shape (FIG. 10D). Then, the resist film is stripped (FIG. 10E), and after cleaning, a desired lead frame is obtained and an etching process is performed. In this way, the lead frame manufactured by the etching process is further subjected to silver plating in a predetermined area, etc. Then, after undergoing treatments such as washing and drying, the inner frame is finished. The tape part is taped with an adhesive-attached polyimide tape for fixing, or the tab suspension bar is bent by a predetermined amount if necessary, and the die pad part is downset. Is corroded by the etching solution in the plate width direction (plane) direction as well as in the plate thickness direction of the plate to be processed, so that there is a limit to the miniaturization process in general, and as shown in FIG. Since the lead frame material is etched from both sides, in the case of the line and space shape, the processing limit width of the line interval is said to be about 50 to 100% of the plate thickness. In consideration of the strength of, the plate thickness is generally required to be about 0.125 mm or more. Therefore, in the case of the etching processing method as shown in FIG. The thickness of the plate is 0.15
By making the thickness as thin as about mm to 0.125 mm, the required flat width 70 to 80 for wire bonding is secured, and the processing by etching of the fine inner lead portion tip of about 0.165 mm pitch has been achieved. It was a limit.

【０００４】しかしながら、近年、樹脂封止型半導体装
置は、小パッケージでは、電極端子であるインナーリー
ドのピッチが０．１６５ｍｍピッチを経て、既に０．１
５〜０．１３ｍｍピッチまでの狭ピッチ化要求がでてき
た事と、エッチング加工において、リード部材の板厚を
薄した場合には、アセンブリ工程や実装工程といった後
工程におけるアウターリードの強度確保が難しいという
点から、単にリード部材の板厚を薄くしてエッチング加
工を行う方法にも限界が出てきた。However, in recent years, in the resin-sealed type semiconductor device, in a small package, the pitch of the inner leads, which are the electrode terminals, has been 0.165 mm, and is already 0.1.
There is a demand for a narrower pitch of 5 to 0.13 mm, and when the thickness of the lead member is reduced in the etching process, it is possible to secure the strength of the outer lead in the post process such as the assembly process and the mounting process. From the point of difficulty, there is a limit to the method of simply reducing the plate thickness of the lead member and performing the etching process.

【０００５】これに対応する方法として、アウターリー
ドの強度を確保したまま微細化を行う方法で、インナー
リード部分をハーフエッチングもしくはプレスにより薄
くしてエッチング加工を行う方法が提案されている。し
かし、プレスにより薄くしてエッチング加工をおこなう
場合には、後工程においての精度が不足する（例えば、
めっきエリアの平滑性）、ボンデイング、モールデイン
グ時のクランプに必要なインナーリードの平坦性、寸法
精度が確保されない、製版を２度行なわなければならな
い等製造工程が複雑になる、等問題点が多くある。そし
て、インナーリード部分をハーフエッチングにより薄く
してエッチング加工を行う方法の場合にも、製版を２度
行なわなければならず、製造工程が複雑になるという問
題があり、いずれも実用化には、未だ至っていないのが
現状である。As a method for dealing with this, there has been proposed a method of miniaturizing while maintaining the strength of the outer leads, and a method of etching the inner leads by thinning them by half etching or pressing. However, if the thickness is reduced by pressing and etching is performed, the accuracy in the subsequent process is insufficient (for example,
(Smoothness of plating area), flatness of inner leads required for clamping during bonding and molding, dimensional accuracy is not secured, and the plate making process must be performed twice, which complicates the manufacturing process. is there. Also, in the case of a method in which the inner lead portion is thinned by half etching and etching is performed, plate making must be performed twice, and there is a problem that the manufacturing process becomes complicated. The current situation is that it has not arrived yet.

【０００６】[0006]

【発明が解決しようとする課題】一方、電子機器の軽薄
短小化の時流に伴い、半導体パッケージにおいても、小
型で実装性が良いものが求められるようになってきて、
外形寸法をほぼ半導体素子に合わせて、封止用樹脂によ
り樹脂封止したＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋ
ａｇｅ）と言われるパッケージが提案されるようになっ
てきた。ＣＳＰを使う恩恵を以下に簡単に述べる。 第一にピン数が同じなら、ＱＦＰ（Ｑｕａｄ Ｆｌａ
ｔ Ｐａｃｋａｇｅ）やＢＧＡ（Ｂａｌｌ Ｇｒｉｄ
Ａｒｒａｙ）に比べ実装面積を格段に小さくできる。 第二に、パッケージ寸法が同じならＱＦＰやＢＧＡよ
りもピン数を多くとれる。ＱＦＰについては、パッケー
ジや基板の反りを考えると、実用的にを使える寸法は最
大４０ｍｍ角であり、アウターリードピッチが０．５ｍ
ｍピッチのＱＦＰでは３０４ピンが限界となる。さらに
ピン数を増やすためには、０．４ｍｍピッチや０．３ｍ
ｍピッチが必要となるが、この場合には、ユーザが量産
性の高い実装（一括リフロー・ハンダ付け）を行うのが
難しくなってくる。一般にはＱＦＰの製造に関してはア
ウターリードピッチが０．３ｍｍピッチ以下ではコスト
を上げずに量産するのは困難と言われている。ＢＧＡ
は、上記ＱＦＰの限界を打破するものとし注目を集め始
めたもので、外部端子を二次元アレイ状にし、外部端子
ピッチを広げることで実装の負担を軽減しようとするも
のである。ＢＧＡの場合、外部端子が３００ピンを超え
る領域でも、従来通りの一括リフロー・ハンダ付けはで
きるが、３０ｍｍ〜４０ｍｍ角になると、温度サイクル
によって外部端子のハンダ・バンプにクラックが入るた
め、６００ピン〜７００ピン、最大でも１０００ピンが
実用の限界と一般には言われている。外部端子をパッケ
ージ裏面に二次元アレイに設けたＣＳＰの場合には、Ｂ
ＧＡのコンセプトを引継ぎ、且つ、アレイ状の端子ピッ
チを増やすことが可能となる。また、ＢＧＡ同様、一括
リフロー・ハンダ付けが可能である。 第三に、ＱＦＰやＢＧＡに比べるとパッケージ内部の
配線長が短かくなるため、寄生容量が小さくなり伝搬遅
延時間が短くなる。ＬＳＩクロック周波数が１００ＭＨ
ｚを超えるようになると、ＱＦＰではパッケージ内の伝
搬が問題になってしまう。内部配線長を短かくしたＣＳ
Ｐの方が有利である。しかしながら、ＣＳＰは実装面で
は優れるものの、多端子化に対しては、端子のピッチを
さらに狭めることが必要で、この面での限界がある。本
発明は、このような状況のもと、リードフレームを用い
た樹脂封止型半導体装置において、多端子化に対応で
き、且つ、一層の小型化に対応できる半導体装置を提供
しようとするものである。On the other hand, along with the current trend of making electronic devices lighter, thinner, shorter and smaller, semiconductor packages are also required to be small and have good mountability.
The CSP (Chip Size Pack) is resin-encapsulated with encapsulation resin so that the external dimensions are almost matched to those of the semiconductor element.
A package called "age" has been proposed. The benefits of using CSP are briefly described below. First, if the number of pins is the same, QFP (Quad Fla)
t Package) and BGA (Ball Grid)
The mounting area can be markedly smaller than that of Array. Secondly, if the package size is the same, the number of pins can be larger than that of QFP or BGA. With regard to QFP, considering the warpage of the package and substrate, the maximum practical size is 40 mm square, and the outer lead pitch is 0.5 m.
304 pins are the limit for the m-pitch QFP. To increase the number of pins, 0.4mm pitch or 0.3m
Although m pitches are required, in this case, it becomes difficult for the user to perform mass-production mounting (collective reflow soldering). It is generally said that it is difficult to mass-produce QFP without increasing the cost when the outer lead pitch is 0.3 mm or less. BGA
Has begun to attract attention because it breaks the limit of the QFP, and attempts to reduce the mounting load by forming external terminals in a two-dimensional array and widening the external terminal pitch. In the case of BGA, batch reflow soldering can be done as usual even in the area where the external terminals exceed 300 pins, but if the size is 30 mm to 40 mm square, the solder bumps of the external terminals will crack due to the temperature cycle, so 600 pins are required. It is generally said that ~ 700 pins, and 1000 pins at the maximum is the limit of practical use. In the case of a CSP in which external terminals are provided on the back surface of the package in a two-dimensional array, B
It is possible to inherit the concept of GA and increase the array-like terminal pitch. Also, like BGA, batch reflow soldering is possible. Thirdly, since the wiring length inside the package is shorter than that of QFP or BGA, the parasitic capacitance is reduced and the propagation delay time is shortened. LSI clock frequency is 100 MH
When z is exceeded, propagation in the package becomes a problem in QFP. CS with short internal wiring length
P is more advantageous. However, although the CSP is excellent in terms of mounting, in order to increase the number of terminals, it is necessary to further narrow the terminal pitch, and there is a limit in this aspect. Under the circumstances, the present invention is to provide a resin-sealed semiconductor device using a lead frame, which is capable of coping with multiple terminals and further miniaturization. is there.

【０００７】[0007]

【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、２段エッチング加工によりインナーリードの
厚さがリードフレーム素材の厚さよりも薄肉に外形加工
されたリードフレームを用い、外形寸法をほぼ半導体素
子に合わせて封止用樹脂により樹脂封止したＣＳＰ（Ｃ
ｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型の半導体装置で
あって、前記リードフレームは、リードフレーム素材よ
りも薄肉のインナーリードと、該インナーリードに一体
的に連結したリードフレーム素材と同じ厚さの外部回路
と接続するための柱状の端子柱とを有し、且つ、端子柱
はインナーリードの外部側においてインナーリードに対
して厚み方向に直交し、かつ半導体素子搭載側と反対側
に設けられており、端子柱の先端面に半田等からなる端
子部を設け、端子部を封止用樹脂部から露出させ、端子
柱の外部側の側面を封止用樹脂部から露出させており、
半導体素子は、半導体素子の電極部（パッド）を有する
面にて、インナーリード部に絶縁接着材を介して搭載さ
れており、半導体素子の電極部（パッド）はインナーリ
ード間に設けられ、半導体素子搭載側とは反対側のイン
ナーリード先端面とワイヤにて電気的に結線されている
ことを特徴とするものである。また、本発明の樹脂封止
型半導体装置は、２段エッチング加工によりインナーリ
ードの厚さがリードフレーム素材の厚さよりも薄肉に外
形加工されたリードフレームを用い、外形寸法をほぼ半
導体素子に合わせて封止用樹脂により樹脂封止したＣＳ
Ｐ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型の半導体
装置であって、前記リードフレームは、リードフレーム
素材よりも薄肉のインナーリードと、該インナーリード
に一体的に連結したリードフレーム素材と同じ厚さの外
部回路と接続するための柱状の端子柱とを有し、且つ、
端子柱はインナーリードの外部側においてインナーリー
ドに対して厚み方向に直交し、かつ半導体素子搭載側と
反対側に設けられており、端子柱の先端の一部を封止用
樹脂部から露出させて端子部とし、端子柱の外部側の側
面を封止用樹脂部から露出させており、半導体素子は、
半導体素子の電極部（パッド）を有する面にて、インナ
ーリード部に絶縁接着材を介して搭載されており、半導
体素子の電極部（パッド）はインナーリード間に設けら
れ、半導体素子搭載側とは反対側のインナーリード先端
面とワイヤにて電気的に結線されていることを特徴とす
るものである。そして上記において、請求項１ないし２
において、リードフレームはダイパッドを有しており、
半導体素子はその電極部（パッド）をインナーリード部
とダイパッド部との間に設けていることを特徴とするも
のである。また、本発明の樹脂封止型半導体装置は、２
段エッチング加工によりインナーリードの厚さがリード
フレーム素材の厚さよりも薄肉に外形加工されたリード
フレームを用い、外形寸法をほぼ半導体素子に合わせて
封止用樹脂により樹脂封止したＣＳＰ（Ｃｈｉｐ Ｓｉ
ｚｅ Ｐａｃｋａｇｅ）型の半導体装置であって、前記
リードフレームは、リードフレーム素材よりも薄肉のイ
ンナーリードと、該インナーリードに一体的に連結した
リードフレーム素材と同じ厚さの外部回路と接続するた
めの柱状の端子柱とを有し、且つ、端子柱はインナーリ
ードの外部側においてインナーリードに対して厚み方向
に直交し、かつ半導体素子搭載側と反対側に設けられて
おり、端子柱の先端面に半田等からなる端子部を設け、
端子部を封止用樹脂部から露出させ、端子柱の外部側の
側面を封止用樹脂部から露出させており、半導体素子
は、半導体素子の一面に設けられたバンプを介してイン
ナーリード部に搭載され、半導体素子とインナーリード
部とが電気的に接続していることを特徴とするものであ
る。また、本発明の樹脂封止型半導体装置は、２段エッ
チング加工によりインナーリードの厚さがリードフレー
ム素材の厚さよりも薄肉に外形加工されたリードフレー
ムを用い、外形寸法をほぼ半導体素子に合わせて封止用
樹脂により樹脂封止したＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ
Ｐａｃｋａｇｅ）型の半導体装置であって、前記リード
フレームは、リードフレーム素材よりも薄肉のインナー
リードと、該インナーリードに一体的に連結したリード
フレーム素材と同じ厚さの外部回路と接続するための柱
状の端子柱とを有し、且つ、端子柱はインナーリードの
外部側においてインナーリードに対して厚み方向に直交
し、かつ半導体素子搭載側と反対側に設けられており、
端子柱の先端の一部を封止用樹脂部から露出させて端子
部とし、端子柱の外部側の側面を封止用樹脂部から露出
させており、半導体素子は、半導体素子の一面に設けら
れたバンプを介してインナーリード部に搭載され、半導
体素子とインナーリード部とが電気的に接続しているこ
とを特徴とするものである。そして上記において、イン
ナーリードは、断面形状が略方形で第１面、第２面、第
３面、第４面の４面を有しており、かつ第１面はリード
フレーム素材と同じ厚さの他の部分の一方の面と同一平
面上にあって第２面に向き合っており、第３面、第４面
はインナーリードの内側に向かって凹んだ形状に形成さ
れていることを特徴とするものである。尚、ここでは、
ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型の半
導体装置とは、半導体素子の厚み方向を除いた、Ｘ、Ｙ
方向の外形寸法にほぼ近い形で封止用樹脂により樹脂封
止した半導体装置の総称を言っており、本発明の半導体
装置は、その中でもリードフレームを用いたものであ
る。また、上記において、端子柱の先端面に半田等から
なる端子部を設け、端子部を封止用樹脂部から露出させ
る場合、半田等からなる端子部は封止用樹脂部から突出
したものが一般的であるが、必ずしも突出する必要はな
い。また、必要に応じて、封止用樹脂部から露出された
端子柱の外部側の側面部分を接着材等を介して保護枠で
覆っても良い。SUMMARY OF THE INVENTION A resin-sealed semiconductor device of the present invention uses a lead frame whose outer leads are thinned by a two-step etching process to be thinner than a lead frame material. The size of the CSP (C
In a semiconductor device of a "hip Size Package" type, the lead frame is connected to an inner lead thinner than a lead frame material and an external circuit having the same thickness as the lead frame material integrally connected to the inner lead. A columnar terminal column for, and the terminal column is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and provided on the side opposite to the semiconductor element mounting side. A terminal portion made of solder or the like is provided on the tip surface, the terminal portion is exposed from the sealing resin portion, and the external side surface of the terminal pillar is exposed from the sealing resin portion,
The semiconductor element is mounted on the inner lead portion via an insulating adhesive on the surface having the electrode portion (pad) of the semiconductor element, and the electrode portion (pad) of the semiconductor element is provided between the inner leads. It is characterized in that it is electrically connected to the tip end surface of the inner lead on the side opposite to the element mounting side with a wire. Further, the resin-sealed semiconductor device of the present invention uses a lead frame whose inner lead is thinned by the two-step etching process to be thinner than the thickness of the lead frame material. CS resin-sealed with sealing resin
A P (Chip Size Package) type semiconductor device, wherein the lead frame includes an inner lead that is thinner than a lead frame material, and an external circuit that is integrally connected to the inner lead and has the same thickness as the lead frame material. And a columnar terminal column for connection, and
The terminal post is provided on the outer side of the inner lead at right angles to the inner lead in the thickness direction and on the side opposite to the semiconductor element mounting side, and a part of the tip of the terminal post is exposed from the sealing resin part. As a terminal part, and the side surface on the outer side of the terminal pillar is exposed from the sealing resin part.
The semiconductor element is mounted on the inner lead portion via an insulating adhesive on the surface having the electrode section (pad), and the electrode section (pad) of the semiconductor element is provided between the inner leads and is mounted on the semiconductor element mounting side. Is electrically connected to the tip end surface of the inner lead on the opposite side with a wire. And in the above, claim 1 or 2
In, the lead frame has a die pad,
The semiconductor element is characterized in that its electrode portion (pad) is provided between the inner lead portion and the die pad portion. Further, the resin-encapsulated semiconductor device of the present invention is
A CSP (Chip Si) is used in which a lead frame whose inner leads are thinner than the thickness of the lead frame material by a step etching process is used and the outer dimensions of the lead frame are substantially resin-sealed with a sealing resin.
ze Package) type semiconductor device, wherein the lead frame is connected to an inner lead that is thinner than the lead frame material and an external circuit that has the same thickness as the lead frame material that is integrally connected to the inner lead. And the terminal post is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and on the side opposite to the semiconductor element mounting side. Provide a terminal part made of solder etc. on the surface,
The terminal part is exposed from the encapsulating resin part, and the outer side surface of the terminal pillar is exposed from the encapsulating resin part.The semiconductor element is the inner lead part via the bump provided on one surface of the semiconductor element. The semiconductor element and the inner lead portion are electrically connected to each other. Further, the resin-sealed semiconductor device of the present invention uses a lead frame whose inner lead is thinned by the two-step etching process to be thinner than the thickness of the lead frame material. (Chip Size)
And a lead frame for connecting to an inner lead thinner than a lead frame material and an external circuit having the same thickness as the lead frame material integrally connected to the inner lead. And a columnar terminal column, and the terminal column is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and on the side opposite to the semiconductor element mounting side,
Part of the tip of the terminal pillar is exposed from the encapsulating resin portion to form the terminal portion, and the external side surface of the terminal pillar is exposed from the encapsulating resin portion.The semiconductor element is provided on one surface of the semiconductor element. The semiconductor element and the inner lead portion are electrically connected to each other by being mounted on the inner lead portion via the formed bumps. In addition, in the above, the inner lead has a substantially rectangular cross-section and has four surfaces, a first surface, a second surface, a third surface, and a fourth surface, and the first surface has the same thickness as the lead frame material. The second surface of the other part is flush with the second surface and faces the second surface, and the third surface and the fourth surface are formed in a concave shape toward the inner side of the inner lead. To do. In addition, here
The CSP (Chip Size Package) type semiconductor device means X, Y excluding the thickness direction of the semiconductor element.
This is a general term for semiconductor devices that are resin-sealed with a sealing resin in a shape that is almost close to the external dimensions in the direction. The semiconductor device of the present invention uses a lead frame among them. Further, in the above, when a terminal portion made of solder or the like is provided on the tip end surface of the terminal pillar and the terminal portion is exposed from the sealing resin portion, the terminal portion made of solder or the like should be projected from the sealing resin portion. Generally, it is not always necessary to project. Further, if necessary, the external side surface portion of the terminal pillar exposed from the sealing resin portion may be covered with a protective frame via an adhesive or the like.

【０００８】[0008]

【作用】本発明の樹脂封止型半導体装置は、上記のよう
に構成することにより、リードフレームを用いた樹脂封
止型半導体装置において、多端子化に対応でき、且つ、
実装性の良い小型の半導体装置の提供を可能とするもの
であり、同時に、従来の図１１（ｂ）に示す単層リード
フレームを用いた場合のように、ダムバーのプレスによ
る除去工程や、アウターリードのフオーミング工程を必
要としないため、これらの工程に起因して発生していた
アウターリードのスキューの問題やアウターリードの平
坦性（コープラナリティー）の問題を全く無くすことが
できる半導体装置の提供を可能とするものである。詳し
くは、２段エッチング加工によりインナーリード部の厚
さが素材の厚さよりも薄肉に外形加工された、即ち、イ
ンナーリードを微細に加工された多ピンのリードフレー
ムを用いているたとにより、半導体装置の多端子化に対
応できるものとしており、且つ、外形寸法をほぼ半導体
素子に合わせて、封止用樹脂により樹脂封止したＣＳＰ
（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）型の半導体装
置としていることにより、小型化して作製することを可
能としている。更に、後述する、図８に示す２段エッン
チングにより作製された、インナーリードは、断面形状
が略方形で第１面、第２面、第３面、第４面の４面を有
しており、かつ第１面はリードフレーム素材と同じ厚さ
の他の部分の一方の面と同一平面上にあって第２面に向
き合っており、第３面、第４面はインナーリードの内側
に向かって凹んだ形状に形成されていることにより、イ
ンナーリード部の第２面は平坦性を確保でき、ワイヤボ
ンデイング性の良いものとしている。また第１面も平坦
面で、第３面、第４面はインナーリード側に凹状である
ためインナーリード部は、安定しており、且つ、ワイヤ
ボンデイングの平坦幅を広くとれる。The resin-encapsulated semiconductor device of the present invention, which is configured as described above, can accommodate multiple terminals in the resin-encapsulated semiconductor device using the lead frame, and
This makes it possible to provide a small-sized semiconductor device with good mountability, and at the same time, as in the case of using the conventional single-layer lead frame shown in FIG. Since a lead forming process is not required, it is possible to provide a semiconductor device capable of completely eliminating the skew problem of outer leads and the flatness (coplanarity) of outer leads caused by these processes. Is possible. More specifically, the inner lead portion is thinned by the two-step etching process to be thinner than the material, that is, the inner lead is finely processed. A CSP that is designed to be compatible with the multi-terminals of devices and is resin-sealed with a sealing resin in conformity with the external dimensions of semiconductor devices.
The use of the (Chip Size Package) type semiconductor device enables miniaturization and manufacture. Further, the inner lead, which will be described later and which is produced by the two-step etching shown in FIG. 8, has a substantially rectangular cross-section and has four surfaces, a first surface, a second surface, a third surface, and a fourth surface. The first surface is flush with one surface of the other portion having the same thickness as the lead frame material and faces the second surface, and the third and fourth surfaces face the inner side of the inner lead. The second surface of the inner lead portion can have a flatness and a good wire bonding property by being formed in a concave shape. Further, the first surface is also a flat surface, and the third surface and the fourth surface are concave toward the inner lead side, so that the inner lead portion is stable and the flat width of the wire bonding can be widened.

【０００９】また、本発明の樹脂封止型半導体装置は、
半導体素子が、半導体素子の一面に設けられたバンプを
介してインナーリード部に搭載され、半導体素子とイン
ナーリード部とが電気的に接続していることにより、ワ
イヤボンデイングの必要がなく、一括したボンデイング
を可能としている。The resin-sealed semiconductor device of the present invention is
Since the semiconductor element is mounted on the inner lead portion via the bump provided on the one surface of the semiconductor element and the semiconductor element and the inner lead portion are electrically connected, there is no need for wire bonding, so Bonding is possible.

【００１０】[0010]

【実施例】本発明の樹脂封止型半導体装置の実施例を図
にそって説明する。先ず、実施例１を図１に示し、説明
する。図１（ａ）は実施例１の樹脂封止型半導体装置の
断面図であり、図１（ｂ）（イ）は図１（ａ）のＡ１−
Ａ２におけるインナーリード部の断面図で、図１（ｂ）
（ロ）は図１（ａ）のＢ１−Ｂ２における端子柱部の断
面図である。図１中、１００は半導体装置、１１０は半
導体素子、１１１は電極部（パッド）、１２０はワイ
ヤ、１３０はリードフレーム、１３１はインナーリー
ド、１３１Ａａは第１面、１３１Ａｂは第２面、１３１
Ａｃは第３面、１３１Ａｄは第４面、１３３は端子柱、
１３３Ａは端子部、１３３Ｂは側面、１４０は封止用樹
脂、１５０は絶縁接着材、１６０は補強用テープある。
本実施例１の樹脂封止型半導体装置においては、半導体
素子１１０は、半導体素子の電極部（パッド）１１１側
の面で電極部（パッド）１１１がインナーリード間に収
まるようにして、インナーリード１３１に絶縁接着材１
５０を介して搭載固定されている。そして、電極部１１
１は、ワイヤ１２０にて、インナーリード部１３１の先
端の第２面１３１Ａｂと電気的に結線されている。本実
施例１の半導体装置１００と外部回路との電気的な接続
は、端子柱１３３先端部に設けられた半球状の半田から
なる端子部１３３Ａを介してプリント基板等へ搭載され
ることにより行われる。実施例１の半導体装置１００に
使用のリードフレーム１３０は、４２％ニッケル−鉄合
金を素材としたもので、そして、図６（ａ）に示すよう
な形状をしたエッチングにより外形加工されたリードフ
レームを用いたものである。端子柱１３３他の部分より
薄肉に形成されたインナーリード１３１をもつ。ダムバ
ー１３６は樹脂封止する際のダムとなる。尚、図６
（ａ）に示すような形状をしたエッチングにより外形加
工されたリードフレームを、本実施例においては用いた
が、インナーリード部１３１と端子柱部１３３以外は６
最終的に不要なものであるから、特にこの形状に限定は
されない。インナーリード部１３１の厚さｔは４０μ
ｍ、インナーリード部１３１以外の厚さｔ0 は０．１５
ｍｍでリードフレーム素材の板厚のままである。また、
インナーリードピッチは０．１２ｍｍと狭いピッチで、
半導体装置の多端子化に対応できるものとしている。イ
ンナーリード部１３１の第２面１３１Ａｂは平坦状でワ
イヤボンデイィングし易い形状となっており、第３面１
３１Ａｃ、第４面１３１Ａｄはインナーリード側へ凹ん
だ形状をしており、第２ワイヤボンディング面を狭くし
ても強度的に強いものとしている。尚、図６（ｂ）は図
６（ａ）のＣ１−Ｃ２における断面を示している。補強
用テープ１６０はインナーリード部にヨレが発生しない
ように固定しておくものである。尚、インナーリードの
長さが短かい場合には直接図６（ａ）に示す形状のリー
ドフレームをエッチング加工にして作製し、これに後述
する方法により半導体素子を搭載して樹脂封止できる
が、インナーリードが長く、インナーリードにヨレを生
じ易い場合には直接図６（ａ）に示す形状にエッチング
加工することは出来ないため、図６（ｃ）（イ）に示す
ようにインナーリード先端部を連結部１３１Ｂにて固定
した状態にエッチング加工した後、インナーリード１３
１部を補強テープ１６０で固定し（図６（ｃ）
（ロ））、次いでプレスにて、半導体装置作製の際には
不要の連結部１３１Ｂを除去し、この状態で半導体素子
を搭載して半導体装置を作製する。（図６（ｃ）
（ハ）） 図６（ｃ）（ロ）中Ｅ１−Ｅ２はプレスにて切断するラ
インを示している。Embodiments of the resin-sealed semiconductor device of the present invention will be described with reference to the drawings. First, Example 1 is shown in FIG. 1 and described. 1A is a cross-sectional view of the resin-sealed semiconductor device of Example 1, and FIG. 1B and FIG. 1A are A1- of FIG.
1B is a sectional view of the inner lead portion taken along line A2 of FIG.
2B is a cross-sectional view of the terminal pillar portion taken along line B1-B2 of FIG. In FIG. 1, 100 is a semiconductor device, 110 is a semiconductor element, 111 is an electrode portion (pad), 120 is a wire, 130 is a lead frame, 131 is an inner lead, 131Aa is the first surface, 131Ab is the second surface, 131.
Ac is the third surface, 131Ad is the fourth surface, 133 is the terminal post,
133A is a terminal portion, 133B is a side surface, 140 is a sealing resin, 150 is an insulating adhesive, and 160 is a reinforcing tape.
In the resin-encapsulated semiconductor device according to the first embodiment, the semiconductor element 110 has an inner lead so that the electrode portion (pad) 111 fits between the inner leads on the surface of the semiconductor element on the electrode portion (pad) 111 side. Insulation adhesive 1 on 131
It is mounted and fixed via 50. And the electrode part 11
1 is electrically connected to the second surface 131Ab at the tip of the inner lead portion 131 by a wire 120. The electrical connection between the semiconductor device 100 according to the first embodiment and an external circuit is performed by mounting the semiconductor device 100 on a printed circuit board or the like through a terminal portion 133A made of hemispherical solder provided at the tip of the terminal pillar 133. Be seen. The lead frame 130 used in the semiconductor device 100 of Example 1 is made of 42% nickel-iron alloy as a raw material, and is lead frame externally processed by etching having a shape as shown in FIG. 6A. Is used. The terminal post 133 has inner leads 131 that are thinner than the other parts. The dam bar 136 serves as a dam for resin sealing. Incidentally, FIG.
Although a lead frame having an outer shape processed by etching having a shape as shown in (a) was used in this embodiment, 6 except for the inner lead portion 131 and the terminal pillar portion 133.
The shape is not particularly limited to this shape because it is not necessary in the end. The thickness t of the inner lead portion 131 is 40μ
m, the thickness t 0 other than the inner lead portion 131 is 0.15
The thickness of the lead frame material remains the same in mm. Also,
Inner lead pitch is as narrow as 0.12mm,
It is supposed to be able to cope with multi-terminals of semiconductor devices. The second surface 131Ab of the inner lead portion 131 is flat and has a shape that facilitates wire bonding.
The surface 31 </ b> Ac and the fourth surface 131 </ b> Ad are recessed toward the inner lead side, and are strong in strength even if the second wire bonding surface is narrowed. Note that FIG. 6B shows a cross section taken along line C1-C2 of FIG. The reinforcing tape 160 is fixed to the inner lead portion so as not to cause twisting. When the length of the inner lead is short, the lead frame having the shape shown in FIG. 6 (a) may be directly formed by etching, and a semiconductor element may be mounted on the lead frame by a method described later to seal the resin. When the inner lead is long and the inner lead is apt to be twisted, the shape of the inner lead cannot be directly etched, as shown in FIG. 6 (c) (a). The inner lead 13 is etched after the portion is fixed by the connecting portion 131B.
One part is fixed with a reinforcing tape 160 (Fig. 6 (c)
(B)) Then, by pressing, unnecessary connecting portions 131B are removed when the semiconductor device is manufactured, and a semiconductor element is mounted in this state to manufacture a semiconductor device. (Fig. 6 (c)
(C)) E1-E2 in FIG. 6 (c) (b) indicate lines cut by a press.

【００１１】次に本実施例１の樹脂封止型半導体装置の
製造方法を図５に基づいて簡単に説明する。先ず、後述
するエッチング加工にて作製され、不要の部分をカッテ
イング処理等で除去されたものを、インナーリード先端
部薄肉部が図５で上になるようにして用意した。尚、イ
ンナーリード１３１部の長さが長い場合には、必要に応
じて、インナーリードの先端部がポリイミドテープによ
りテーピング固定されているものを用意する。次いで半
導体素子１１０の電極部１１１側面を図５で下にして、
インナーリード１３１間に納め、絶縁接着材１５０を介
してインナーリード１３１に搭載固定した。（図５
（ａ）） 半導体素子１１０をリードフレーム１３０に接着固定し
た後、リードフレーム側１３０を半導体の上にして、半
導体素子１１０の電極部１１１とインナーリード部１３
１の先端部とをワイヤ１２０にてボンデイング接続し
た。（図５（ｂ）） 次いで、通常の封止用樹脂１４０で樹脂封止を行った。
（図５（ｃ）） 樹脂による封止は所定の型を用いて行うが、半導体素子
１１０のサイズで、且つ、リードフレームの端子柱の外
側の面が若干樹脂から外部へ突出した状態で封止した。
次いで、不要なリードフレーム１３０の封止用樹脂１４
０面から突出している部分をプレスにて切断し、端子柱
１３３を形成するとともに端子柱１３３の側面１３３Ｂ
を形成した。（図５（ｄ）） この時、切断されるリードフレームのラインには、切断
がし易いように、切り欠きを設けておくと良い。特に、
これらの切り欠きはエッチング時に、併せて加工してお
けば手間が省ける。図６に示すリードフレーム１１０の
ダムバー１３６、フレーム部１３７等が除去される。こ
の後、リードフレームの端子柱の外側の面に半田からな
る端子部１３３Ａを作製して半導体装置を作製した。
（図５（ｅ）） この半田からなる端子部１３３Ａは外部回路基板と接続
する際に、接続し易いように設けてあるが特に設けなく
ても良い。Next, a method of manufacturing the resin-encapsulated semiconductor device of the first embodiment will be briefly described with reference to FIG. First, a product prepared by an etching process described below and having unnecessary portions removed by a cutting process or the like was prepared so that the thin portion of the inner lead tip end portion was on the upper side in FIG. When the length of the inner lead 131 is long, the inner lead whose tip is fixed by taping with a polyimide tape is prepared if necessary. Next, the side surface of the electrode portion 111 of the semiconductor element 110 is turned down in FIG.
It was housed between the inner leads 131 and mounted and fixed on the inner leads 131 via an insulating adhesive material 150. (Fig. 5
(A)) After the semiconductor element 110 is adhesively fixed to the lead frame 130, the lead frame side 130 is placed on the semiconductor, and the electrode portion 111 and the inner lead portion 13 of the semiconductor element 110 are placed.
The tip end of No. 1 was bonded by a wire 120. (FIG. 5B) Next, resin sealing was performed with a normal sealing resin 140.
(FIG. 5C) Sealing with a resin is performed by using a predetermined mold, but with the size of the semiconductor element 110 and the outer surface of the terminal post of the lead frame slightly protruding from the resin to the outside. I stopped.
Then, the unnecessary resin 14 for sealing the lead frame 130
The part protruding from the 0 plane is cut by a press to form the terminal post 133 and the side surface 133B of the terminal post 133.
Was formed. (FIG. 5D) At this time, it is preferable to provide a notch in the line of the lead frame to be cut so that the line can be easily cut. Especially,
If these notches are also processed at the time of etching, the time and effort can be saved. The dam bar 136 and the frame portion 137 of the lead frame 110 shown in FIG. 6 are removed. After that, a terminal portion 133A made of solder was formed on the outer surface of the terminal column of the lead frame to manufacture a semiconductor device.
(FIG. 5 (e)) This terminal portion 133A made of solder is provided so as to be easily connected to the external circuit board, but it may not be provided.

【００１２】本発明の半導体装置に用いられるリードフ
レームの製造方法を以下、図にそって説明する。図８
は、本実施例１の樹脂封止型半導体装置に用いられたリ
ードフレームの製造方法を説明するための、インナーリ
ード先端部を含む要部における各工程断面図であり、こ
こで作製されるリードフレームを示す平面図である図６
（ａ）のＤ１−Ｄ２部の断面部における製造工程図であ
る。図８中、８１０はリードフレーム素材、８２０Ａ、
８２０Ｂはレジストパターン、８３０は第一の開口部、
８４０は第二の開口部、８５０は第一の凹部、８６０は
第二の凹部、８７０は平坦状面、８８０はエッチング抵
抗層、１３１Ａはインナーリード先端部、１３１Ａｂは
インナーリードの第２面を示す。先ず、４２％ニッケル
−鉄合金からなり、厚みが０．１５ｍｍのリードフレー
ム素材８１０の両面に、重クロム酸カリウムを感光剤と
した水溶性カゼインレジストを塗布した後、所定のパタ
ーン版を用いて、所定形状の第一の開口部８３０、第二
の開口部８４０をもつレジストパターン８２０Ａ、８２
０Ｂを形成した。（図８（ａ）） 第一の開口部８３０は、後のエッチング加工においてリ
ードフレーム素材８１０をこの開口部からベタ状にリー
ドフレーム素材よりも薄肉に腐蝕するためのもので、レ
ジストの第二の開口部８４０は、インナーリード先端部
の形状を形成するためのものである。第一の開口部８３
０は、少なくともリードフレーム８１０のンナーリード
先端部形成領域を含むが、後工程において、テーピング
の工程や、リードフレームを固定するクランプ工程で、
ベタ状に腐蝕され部分的に薄くなった部分との段差が邪
魔になる場合があるので、エッチングを行うエリアはイ
ンナーリード先端の微細加工部分だけにせず大きめにと
る必要がある。次いで、液温５７°Ｃ、比重４８ボーメ
の塩化第二鉄溶液を用いて、スプレー圧２．５ｋｇ／ｃ
ｍ2 にて、レジストパターンが形成されたリードフレー
ム素材８１０の両面をエッチングし、ベタ状（平坦状）
に腐蝕された第一の凹部８５０の深さｈがリードフレー
ム部材の約２／３程度に達した時点でエッチングを止め
た。（図８（ｂ）） 上記第１回目のエッチングにおいては、リードフレーム
素材８１０の両面から同時にエッチングを行ったが、必
ずしも両面から同時にエッチングする必要はない。少な
くとも、インナーリード先端部形状を形成するための、
所定形状の開口部をもつレジストパターン８２０Ｂが形
成された面側から腐蝕液によるエッチング加工を行い、
腐蝕されたインナーリード先端部形成領域において、所
定量エッチング加工し止めることができれば良い。本実
施例のように、第１回目のエッチングにおいてリードフ
レーム素材８１０の両面から同時にエッチングする理由
は、両面からエッチングすることにより、後述する第２
回目のエッチング時間を短縮するためで、レジストパタ
ーン８２０Ｂ側からのみの片面エッチングの場合と比
べ、第１回目エッチングと第２回目エッチングのトータ
ル時間が短縮される。次いで、第一の開口部８３０側の
腐蝕された第一の凹部８５０にエッチング抵抗層８８０
としての耐エッチング性のあるホットメルト型ワックス
（ザ・インクテエック社製の酸ワックス、型番ＭＲ−Ｗ
Ｂ６）を、ダイコータを用いて、塗布し、ベタ状（平坦
状）に腐蝕された第一の凹部８５０に埋め込んだ。レジ
ストパターン８２０Ｂ上も該エッチング抵抗層８８０に
塗布された状態とした。（図８（ｃ）） エッチング抵抗層８８０を、レジストパターン８２０Ｂ
上全面に塗布する必要はないが、第一の凹部８５０を含
む一部にのみ塗布することは難し為に、図８（ｃ）に示
すように、第一の凹部８５０とともに、第一の開口部８
３０側全面にエッチング抵抗層８８０を塗布した。本実
施例で使用したエッチング抵抗層８８０は、アルカリ溶
解型のワックスであるが、基本的にエッチング液に耐性
があり、エッチング時にある程度の柔軟性のあるもの
が、好ましく、特に、上記ワックスに限定されず、ＵＶ
硬化型のものでも良い。このようにエッチング抵抗層８
８０をインナーリード先端部の形状を形成するためのパ
ターンが形成された面側の腐蝕された第一の凹部８５０
に埋め込むことにより、後工程でのエッチング時に第一
の凹部８５０が腐蝕されて大きくならないようにしてい
るとともに、高精細なエッチング加工に対しての機械的
な強度補強をしており、スプレー圧を高く（２．５ｋｇ
／ｃｍ2 以上）とすることができ、これによりエッチン
グが深さ方向に進行し易すくなる。この後、第２回目エ
ッチングを行い、ベタ状（平坦状）に腐蝕された第一の
凹部８５０形成面側からリードフレーム素材８１０をエ
ッチングし、貫通させ、インナーリード先端部８９０を
形成した。（図８（ｄ）） 第１回目のエッチング加工にて作製された、リードフレ
ーム面に平行なエッチング形成面は平坦であるが、この
面を挟む２面はインナーリード側にへこんだ凹状であ
る。次いで、洗浄、エッチング抵抗層８８０の除去、レ
ジスト膜（レジストパターン８２０Ａ、８２０Ｂ）の除
去を行い、インナーリード先端部８９０が微細加工され
た図６（ａ）に示すリードフレームを得た。エッチング
抵抗層８８０とレジスト膜（レジストパターン８２０
Ａ、８２Ｂ０）の除去は水酸化ナトリウム水溶液により
溶解除去した。A method of manufacturing a lead frame used in the semiconductor device of the present invention will be described below with reference to the drawings. FIG.
4A to 4C are cross-sectional views of each step in the main part including the tip of the inner lead for explaining the method of manufacturing the lead frame used in the resin-sealed semiconductor device of the first embodiment. FIG. 6 is a plan view showing the frame.
It is a manufacturing-process figure in the cross section of D1-D2 part of (a). In FIG. 8, 810 is a lead frame material, 820A,
820B is a resist pattern, 830 is a first opening,
840 is the second opening, 850 is the first recess, 860 is the second recess, 870 is the flat surface, 880 is the etching resistance layer, 131A is the inner lead tip, 131Ab is the second surface of the inner lead. Show. First, after applying a water-soluble casein resist using potassium dichromate as a photosensitizer to both surfaces of a lead frame material 810 having a thickness of 0.15 mm and made of 42% nickel-iron alloy, a predetermined pattern plate was used. , Resist patterns 820A, 82 having a first opening 830 and a second opening 840 of a predetermined shape.
OB was formed. (FIG. 8A) The first opening 830 is used to corrode the lead frame material 810 through the opening in a later etching process so as to be solid and thinner than the lead frame material. The opening 840 is for forming the shape of the tip of the inner lead. First opening 83
0 includes at least the inner lead tip portion forming region of the lead frame 810, but in a subsequent step, a taping step or a clamp step of fixing the lead frame,
Since there is a case where a step with a portion which is corroded in a solid shape and partially thinned becomes an obstacle, it is necessary to set a large etching area, not only the finely processed portion of the tip of the inner lead. Then, using a ferric chloride solution having a liquid temperature of 57 ° C and a specific gravity of 48 Baume, a spray pressure of 2.5 kg / c.
At m 2 , both sides of the lead frame material 810 having the resist pattern formed thereon are etched to obtain a solid (flat) shape.
The etching was stopped when the depth h of the first recess 850, which had been corroded by the above, reached about 2/3 of the lead frame member. (FIG. 8B) In the first etching, the lead frame material 810 was simultaneously etched from both sides, but it is not always necessary to simultaneously etch from both sides. At least for forming the inner lead tip shape,
Etching with a corrosive liquid is performed from the surface side where the resist pattern 820B having an opening of a predetermined shape is formed,
It suffices that a predetermined amount can be etched and stopped in the corroded inner lead tip forming region. The reason why the lead frame material 810 is simultaneously etched from both sides in the first etching as in the present embodiment is that the etching is performed from both sides to be described later.
In order to shorten the etching time of the first time, the total time of the first etching and the second etching is shortened as compared with the case of single-sided etching only from the resist pattern 820B side. Next, the etching resistance layer 880 is formed in the corroded first concave portion 850 on the first opening 830 side.
Hot-melt type wax with etching resistance (acid wax manufactured by The Inktech Corporation, model number MR-W
B6) was applied using a die coater and embedded in the first recess 850 which was corroded to be solid (flat). The resist pattern 820B was also applied to the etching resistance layer 880. (FIG. 8C) The etching resistance layer 880 is formed on the resist pattern 820B.
Although it is not necessary to apply it to the entire upper surface, it is difficult to apply it only to a part including the first recess 850. Therefore, as shown in FIG. 8C, together with the first recess 850, the first opening is formed. Part 8
An etching resistance layer 880 was applied to the entire surface on the 30 side. The etching resistance layer 880 used in this embodiment is an alkali-soluble wax, but it is preferable that it is basically resistant to an etching solution and has some flexibility during etching, and is particularly limited to the above wax. Not UV
A hardening type may be used. Thus, the etching resistance layer 8
80 is the first recessed portion 850 in which the pattern for forming the shape of the inner lead tip portion is formed and which is corroded on the surface side.
By embedding it in the substrate, the first concave portion 850 is prevented from being corroded during the etching in a later process so as to be large, and the mechanical strength is reinforced for high-definition etching processing, and the spray pressure is increased. High (2.5 kg
/ Cm 2 or more), which facilitates etching to proceed in the depth direction. After that, a second etching was performed to etch the lead frame material 810 from the side of the surface where the first recess 850 was corroded in a solid (flat) shape, and penetrated to form the inner lead tip 890. (FIG. 8 (d)) The surface formed by the first etching process and parallel to the lead frame surface is flat, but the two surfaces sandwiching this surface are recessed to the inner lead side. . Then, cleaning, removal of the etching resistance layer 880, and removal of the resist films (resist patterns 820A and 820B) were performed to obtain the lead frame shown in FIG. 6A in which the inner lead tip portion 890 was finely processed. Etching resistance layer 880 and resist film (resist pattern 820
A, 82B0) was removed by dissolution with an aqueous sodium hydroxide solution.

【００１３】尚、上記のように、エッチングを２段階に
わけて行うエッチング加工方法を、一般には２段エッチ
ング加工方法といっており、特に、微細加工に有利な加
工方法である。本発明に用いた図６（ａ）、図６（ｂ）
に示す、リードフレーム１３０の製造においては、２段
エッチング加工方法と、パターン形状を工夫することに
より部分的にリードフレーム素材を薄くしながら外形加
工する方法とが伴行して採られている。上記の方法によ
るインナーリード先端部１３１Ａの微細化加工は、第二
の凹部８６０の形状と、最終的に得られるインナーリー
ド先端部の厚さｔに左右されるもので、例えば、板厚ｔ
を５０μｍまで薄くすると、図８（ｅ）に示す、平坦幅
Ｗ１を１００μｍとして、インナーリード先端部ピッチ
ｐが０．１５ｍｍまで微細加工可能となる。板厚ｔを３
０μｍ程度まで薄くし、平坦幅Ｗ１を７０μｍ程度とす
ると、インナーリード先端部ピッチｐが０．１２ｍｍ程
度まで微細加工ができるが、板厚ｔ、平坦幅Ｗ１のとり
方次第ではインナーリード先端部ピッチｐは更に狭いピ
ッチまで作製が可能となる。Incidentally, the above-described etching processing method in which etching is divided into two steps is generally called a two-step etching processing method, and is a processing method particularly advantageous for fine processing. 6 (a) and 6 (b) used in the present invention
In the manufacturing of the lead frame 130 shown in (1), a two-step etching method and a method of externally machining the lead frame material while partially thinning it by devising the pattern shape are adopted together. The miniaturization of the inner lead tip portion 131A by the above method depends on the shape of the second recess 860 and the thickness t of the inner lead tip portion finally obtained.
When the thickness is reduced to 50 μm, it becomes possible to finely process the inner lead tip pitch p to 0.15 mm with the flat width W1 shown in FIG. 8E set to 100 μm. Plate thickness t is 3
When the thickness is reduced to about 0 μm and the flat width W1 is set to about 70 μm, fine processing can be performed up to the inner lead tip pitch p of about 0.12 mm, but the inner lead tip pitch p depends on the plate thickness t and the flat width W1. Can manufacture even narrower pitches.

【００１４】このようにエッチング加工にて、インナー
リードの長さが短かい場合等、製造工程でインナーリー
ドのヨレが発生しにくい場合には直接図６（ａ）に示す
形状のリードフレーム得るが、インナーリードの長さが
実施例１の場合に比べ長い場合はインナーリードにヨレ
が発生し易い為、図６（ｃ）（イ）に示ように、インナ
ーリード先端部から連結部１３１Ｂを設けてインナーリ
ード先端部同士を繋げた形状にして形成したものをッチ
ング加工にて得て、この後、半導体作製には不必要な連
結部１３１Ｂをプレス等により切断除去して図６（ａ）
に示す形状を得る。図７（ａ）、図７（ｂ）に示すダイ
パッド２３５を有するリードフレーム２３０を作製する
場合には、図７（ｃ）（イ）に示すように、インナーリ
ード２３１の先端に連結部２３１Ｂを設けてダイパッド
と直接繋がった形状にエッチングにより外形加工した後
に、プレス等により切断しても良い。尚、図７（ｂ）は
図７（ａ）のＣ１１−Ｃ２１における断面図で、図７
（ｃ）中Ｅ１１−Ｅ２１は切断ラインを示している。そ
して、めっきした後に切断除去すると、治具めっき方式
でインナーリードをめっきする場合には、めっきの裏漏
れがなく良い品質のリードフレームが得られる。尚、前
述のように、図６（ｃ）に示すものを切断し、図６
（ａ）に示す形状にする際には、図６（ｃ）（ロ）に示
すように、通常、補強のため補強用テープ１６０（ポリ
イミドテープ）を使用する。図７（ｃ）に示すものを切
断する場合も同様である。図６（ｃ）（ロ）の状態で、
プレス等により連結部１３１Ｂを切断除去するが、半導
体素子は、テープをつけた状態のままで、リードフレー
ムに搭載され、そのまま樹脂封止される。In this way, when the inner lead is not easily twisted during the manufacturing process, such as when the inner lead is short in length by the etching process, the lead frame having the shape shown in FIG. 6A is directly obtained. When the length of the inner lead is longer than that in the first embodiment, the inner lead is apt to be twisted. Therefore, as shown in FIG. 6 (c) (a), the connecting portion 131B is provided from the tip of the inner lead. 6A is obtained by subjecting the inner lead tips to a shape in which the leading end portions of the inner leads are connected to each other by a etching process, and thereafter the connecting portion 131B unnecessary for semiconductor fabrication is cut and removed by a press or the like.
Obtain the shape shown in. When the lead frame 230 having the die pad 235 shown in FIGS. 7A and 7B is manufactured, as shown in FIGS. 7C and 7A, the connecting portion 231B is provided at the tip of the inner lead 231. It is also possible to form the shape provided by being directly connected to the die pad by etching and then cut it by a press or the like. 7B is a cross-sectional view taken along line C11-C21 of FIG.
In (c), E11-E21 indicate cutting lines. Then, when the inner lead is plated by the jig plating method by cutting and removing after plating, a lead frame of good quality with no back leakage of plating can be obtained. Incidentally, as described above, by cutting the one shown in FIG.
When forming the shape shown in FIG. 6A, a reinforcing tape 160 (polyimide tape) is usually used for reinforcement as shown in FIGS. The same applies to the case of cutting the one shown in FIG. In the state of FIG. 6 (c) (b),
Although the connecting portion 131B is cut and removed by a press or the like, the semiconductor element is mounted on the lead frame with the tape still attached, and is resin-sealed as it is.

【００１５】本実施例１の半導体装置に用いられたリー
ドフレームのインナーリード先端部１３１Ａの断面形状
は、図９（イ）に示すようになっており、エッチング平
坦面１３１Ａｂ側の幅Ｗ１は反対側の面の幅Ｗ２より若
干大きくなっており、Ｗ１、Ｗ２（約１００μｍ）とも
この部分の板厚さ方向中部の幅Ｗよりも大きくなってい
る。このようにインリーリード先端部の両面は広くなっ
た断面形状であるため、図８（ロ）に示すように、どち
らの面を用いても半導体素子（図示せず）とインナーリ
ード先端部１３１Ａとワイヤ１２０Ａ、１２０Ｂによる
結線（ボンデイング）がし易すいものとなっているが、
本実施例の場合はエッチング面側（図９（ロ）（ａ））
をボンデイング面としている。図中１３１Ａｂはエッチ
ング加工による平坦面、１３１Ａａはリードフレーム素
材面、１２１Ａ、１２１Ｂはめっき部である。エッチン
グ平坦状面がアラビの無い面であるため、図９（ロ）の
（ａ）の場合は、特に結線（ボンデイング）適性が優れ
る。図９（ハ）は図１０に示す加工方法にて作製された
リードフレームのインナーリード先端部８３１Ｃと半導
体素子（図示せず）との結線（ボンデイング）を示すも
のであるが、この場合もインナーリード先端部９３１Ｃ
の両面は平坦ではあるが、この部分の板厚方向の幅に比
べ大きくとれない。また両面ともリードフレーム素材面
である為、結線（ボンデイング）適性は本実施例のエッ
チング平坦面より劣る。図９（ニ）はプレスによりイン
ナーリード先端部を薄肉化した後にエッチング加工によ
りインナーリード先端部９３１Ｄ、９３１Ｅを加工した
ものの、半導体素子（図示せず）との結線（ボンデイン
グ）を示したものであるが、この場合はプレス面側が図
に示すように平坦になっていないため、どちらの面を用
いて結線（ボンデイング）しても、図９（ニ）の
（ａ）、（ｂ）に示すように結線（ボンデイング）の際
に安定性が悪く品質的にも問題となる場合が多い。The sectional shape of the inner lead tip portion 131A of the lead frame used in the semiconductor device of the first embodiment is as shown in FIG. 9A, and the width W1 on the side of the etching flat surface 131Ab is opposite. It is slightly larger than the width W2 of the side surface, and both W1 and W2 (about 100 μm) are larger than the width W of the central portion in the plate thickness direction of this portion. In this way, since both sides of the tip end portion of the inlay lead have a broadened cross-sectional shape, as shown in FIG. 8B, the semiconductor element (not shown) and the tip end portion 131A of the inner lead may be used regardless of which surface is used. Although it is easy to connect (bonding) with the wires 120A and 120B,
In the case of the present embodiment, the etching surface side (FIG. 9 (b) (a))
Is the bonding surface. In the figure, 131Ab is a flat surface by etching, 131Aa is a lead frame material surface, and 121A and 121B are plated portions. Since the flat etching surface is a surface free of arabic, in the case of FIG. 9B, the suitability for connection (bonding) is particularly excellent. FIG. 9C shows a connection (bonding) between the inner lead tip portion 831C of the lead frame manufactured by the processing method shown in FIG. 10 and the semiconductor element (not shown). Lead tip 931C
Although both sides of are flat, they cannot be made wider than the width of this portion in the plate thickness direction. Further, since both surfaces are lead frame material surfaces, the suitability for connection (bonding) is inferior to the flat etching surface of this embodiment. FIG. 9D shows a connection (bonding) with a semiconductor element (not shown), although the inner lead tips 931D and 931E are processed by etching after thinning the inner lead tips by pressing. However, in this case, since the pressing surface side is not flat as shown in the figure, whichever surface is used for connection (bonding), it is shown in (a) and (b) of FIG. 9D. As described above, there are many cases in which the stability is poor and the quality is a problem during connection (bonding).

【００１６】次に実施例１の樹脂封止型半導体装置の変
形例を挙げる。図２（ａ）は実施例１の樹脂封止型半導
体装置の変形例の断面図であり、図２（ｃ）は変形例半
導体装置の外観を示すもので、図２（ｃ）（ロ）は下
（底）側から見た図で、図２（ｃ）（イ）は正面図で、
図２（ｂ）は図１（ａ）のＡ１−Ａ２に対応する位置で
の端子柱の断面図である。変形例半導体装置は、実施例
１の半導体装置とは端子部１３３Ａが異なるもので、端
子部は端子柱１３３の先端側を樹脂１４０から突出した
ようにしており、且つ、先端部の表面には溝１３３ｃが
設けられており、溝を設けた状態で表面には半田を塗膜
した状態にする、そして実装する際には、この溝１３３
ｃ部を通り半田が行き渡るようにしている。変形例の半
導体体装置１００Ａは、端子部１３３Ａ以外は、実施例
１の半導体装置と同じである。Next, a modification of the resin-encapsulated semiconductor device of the first embodiment will be described. 2A is a cross-sectional view of a modified example of the resin-encapsulated semiconductor device of the first embodiment, and FIG. 2C is an external view of the modified semiconductor device, and FIGS. Is a view from the bottom (bottom) side, and FIGS. 2 (c) and (a) are front views.
FIG. 2B is a sectional view of the terminal pillar at a position corresponding to A1-A2 in FIG. The modified semiconductor device is different from the semiconductor device of the first embodiment in the terminal portion 133A, and the terminal portion is configured such that the tip end side of the terminal pillar 133 is projected from the resin 140, and the surface of the tip portion is not formed. The groove 133c is provided, and when the groove is provided, the surface of the groove 133c is coated with solder.
Solder is made to pass through the c section. The semiconductor device 100A of the modification is the same as the semiconductor device of the first embodiment except for the terminal portion 133A.

【００１７】次いで、実施例２の樹脂封止型半導体装置
を挙げる。図３（ａ）は実施例２の樹脂封止型半導体装
置の断面図であり、図３（ｂ）は図３（ａ）のＡ３−Ａ
４におけるインナーリード部の断面図で、図３（ｃ）
（イ）は図３（ａ）のＢ３−Ｂ４における端子柱部の断
面図である。図３中、２００は半導体装置、２１０は半
導体素子、２１１は電極部（パッド）、２２０はワイ
ヤ、２３０はリードフレーム、２３１はインナーリー
ド、２３１Ａａは第１面、２３１Ａｂは第２面、２３１
Ａｃは第３面、２３１Ａｄは第４面、２３３は端子柱
部、２３３Ａは端子部、２３３Ｂは側面、２３５はダイ
パッド、２４０は封止用樹脂、２５０は絶縁接着材、２
５０Ａは接着材、２６０は補強用テープある。本実施例
２の場合も、実施例１と同様に、半導体素子２１０は、
半導体素子の電極部（パッド）２１１側の面で電極部
（パッド）２１１がインナーリード間に収まるようにし
て、インナーリード２３１に絶縁接着材２５０を介して
搭載固定されており、電極部２１１は、ワイヤ２２０に
て、インナーリード部２３１の先端の第２面２３１Ａｂ
と電気的に結線されているが、リードフレームにダイパ
ッド２３５を有するもので、半導体素子２１０の電極部
２１１はインナーリード部２３１とダイパッド２３５間
に設けらている。また、本実施例２の場合も、実施例１
と同様に、半導体装置２００と外部回路との電気的な接
続は、端子柱２３３先端部に設けられた半球状の半田か
らなる端子部２３３Ａを介してプリント基板等へ搭載さ
れることにより行われる。本実施例においては、ダイパ
ッド２３５と半導体素子２１０を接着する接着材２５０
Ａを導電性としており、且つ、ダイパッド２３５と端子
柱部２３３とはインナーリード（吊りリード）にて接続
されていることにより、半導体素子にて発生した熱をダ
イパッドを介して外部回路へ放散させることができる。
尚、接着材２５０Ａを導電性の接着材と必ずしもする必
要はないが、ダイパッド２３５を端子柱部２３３を介し
てグランドラインに接続すると、半導体素子２１０がノ
イズに強くなるとともに、ノイズを受けない構造とな
る。Next, the resin-sealed semiconductor device of the second embodiment will be described. 3A is a cross-sectional view of the resin-sealed semiconductor device according to the second embodiment, and FIG. 3B is A3-A of FIG. 3A.
3 (c) is a sectional view of the inner lead portion in FIG.
3B is a cross-sectional view of the terminal pillar portion taken along line B3-B4 of FIG. In FIG. 3, 200 is a semiconductor device, 210 is a semiconductor element, 211 is an electrode portion (pad), 220 is a wire, 230 is a lead frame, 231 is an inner lead, 231Aa is the first surface, 231Ab is the second surface, 231.
Ac is the third surface, 231Ad is the fourth surface, 233 is a terminal pillar portion, 233A is a terminal portion, 233B is a side surface, 235 is a die pad, 240 is a sealing resin, 250 is an insulating adhesive material, 2
50A is an adhesive, and 260 is a reinforcing tape. Also in the case of the second embodiment, as in the first embodiment, the semiconductor element 210 is
The electrode portion (pad) 211 of the semiconductor element is mounted and fixed on the inner lead 231 via the insulating adhesive 250 so that the electrode portion (pad) 211 fits between the inner leads on the surface on the electrode portion (pad) 211 side. , The second surface 231Ab of the tip of the inner lead portion 231 with the wire 220.
However, the lead frame has the die pad 235, and the electrode portion 211 of the semiconductor element 210 is provided between the inner lead portion 231 and the die pad 235. In the case of the second embodiment, the first embodiment
Similarly, the electrical connection between the semiconductor device 200 and the external circuit is performed by mounting the semiconductor device 200 on a printed circuit board or the like through the terminal portion 233A made of hemispherical solder provided at the tip of the terminal pillar 233. . In this embodiment, the adhesive 250 that bonds the die pad 235 and the semiconductor element 210 together.
Since A is conductive and the die pad 235 and the terminal pillar portion 233 are connected by the inner lead (suspension lead), the heat generated in the semiconductor element is dissipated to the external circuit through the die pad. be able to.
Note that the adhesive 250A does not necessarily have to be a conductive adhesive, but when the die pad 235 is connected to the ground line via the terminal pillar portion 233, the semiconductor element 210 becomes resistant to noise and does not receive noise. Becomes

【００１８】実施例２の半導体装置に使用のリードフレ
ーム２３０も、実施例１にて使用のリードフレームと同
様に、４２％ニッケル−鉄合金を素材としたものである
が、、図７（ａ）、図７（ｂ）に示すように、ダイパッ
ド２３５を有する形状をしており、端子柱２３３部分よ
り薄肉に形成されたインナーリード２３１をもつ。イン
ナーリード部２３１の厚さは４０μｍ、端子柱２３３厚
さは０．１５ｍｍである。そして、インナーリードピッ
チは０．１２ｍｍと狭いピッチで、半導体装置の多端子
化に対応できるものとしている。インナーリード部２３
１の第２面２３１Ａｂは平坦状でワイヤボンディングし
易い形状となっており、第３面２３１Ａｃ、第４面２３
１Ａｄはインナーリード側へ凹んだ形状をしており、第
２ワイヤボンディング面を狭くしても強度的に強いもの
としている。また、実施例２の樹脂封止型半導体装置の
作製は、実施例１の場合とほぼ同じ工程にて行う。The lead frame 230 used in the semiconductor device of the second embodiment is also made of 42% nickel-iron alloy as in the lead frame used in the first embodiment. ), As shown in FIG. 7B, it has a shape having a die pad 235, and has an inner lead 231 formed thinner than the terminal pillar 233. The inner lead portion 231 has a thickness of 40 μm, and the terminal pillar 233 has a thickness of 0.15 mm. Further, the inner lead pitch is as narrow as 0.12 mm, which is adapted to the multi-terminal of semiconductor devices. Inner lead part 23
The second surface 231Ab of No. 1 is flat and has a shape that facilitates wire bonding.
1Ad has a shape recessed toward the inner lead side, and is strong in strength even if the second wire bonding surface is narrowed. Further, the production of the resin-encapsulated semiconductor device of Example 2 is carried out in almost the same steps as in Example 1.

【００１９】実施例２の樹脂封止型半導体装置の変形例
としては、図２に示す実施例１の変形例の場合と同様
に、端子柱２３３の先端部に溝２３３Ｃ（図３（ｃ）
（ロ））を設け、封止用樹脂２４０から、突出させて、
端子柱の先端部をそのまま端子２３３Ａにしたものが挙
げられる。As a modified example of the resin-encapsulated semiconductor device of the second embodiment, a groove 233C (FIG. 3C) is formed at the tip of the terminal pillar 233 as in the modified example of the first embodiment shown in FIG.
(B)) is provided, and is projected from the sealing resin 240,
An example is one in which the tip of the terminal pillar is directly used as the terminal 233A.

【００２０】次いで、実施例３の樹脂封止型半導体装置
を挙げる。図４（ａ）は実施例３の樹脂封止型半導体装
置の断面図であり、図３（ｂ）は図４（ａ）のＡ５−Ａ
６におけるインナーリード部の断面図で、図３（ｃ）
（イ）は図３（ａ）のＢ５−Ｂ６における端子柱部の断
面図である。図４中、３００は半導体装置、３１０は半
導体素子、３１１はバンプ、３３０はリードフレーム、
３３１はインナーリード、３３１Ａａは第１面、３３１
Ａｂは第２面、３３１Ａｃは第３面、３３１Ａｄは第４
面、３３３は端子柱部、３３３Ａは端子部、３３３Ｂは
側面、３３５はダイパッド、３４０は封止用樹脂、３６
０は補強用テープある。本実施例の半導体装置３００の
場合は、実施例１や実施例２の場合と異なり、半導体素
子３１０はバンプ３１１を持つもので、バンプ３１１を
直接インナーリード３３０に搭載固定し、半導体素子３
１０とインナーリード３１０とを電気的に結線するもの
である。また、本実施例３の場合も、実施例１や実施例
２の場合と同様に、半導体装置３００と外部回路との電
気的な接続は、端子柱３３３先端部に設けられた半球状
の半田からなる端子部３３３Ａを介してプリント基板等
へ搭載されることにより行われる。Next, the resin-sealed semiconductor device of the third embodiment will be described. FIG. 4A is a cross-sectional view of the resin-sealed semiconductor device of Example 3, and FIG. 3B is A5-A of FIG. 4A.
6 is a cross-sectional view of the inner lead portion in FIG.
3A is a cross-sectional view of the terminal pillar portion taken along line B5-B6 of FIG. In FIG. 4, 300 is a semiconductor device, 310 is a semiconductor element, 311 is a bump, 330 is a lead frame,
331 is an inner lead, 331Aa is the first surface, 331
Ab is the second surface, 331Ac is the third surface, 331Ad is the fourth surface.
A surface 333, a terminal pillar portion, 333A, a terminal portion, 333B, a side surface, 335, a die pad, 340, a sealing resin, and 36.
0 is a reinforcing tape. In the case of the semiconductor device 300 of the present embodiment, unlike the case of the first and second embodiments, the semiconductor element 310 has the bump 311. The bump 311 is directly mounted and fixed on the inner lead 330, and the semiconductor element 3
10 and the inner lead 310 are electrically connected. Also in the case of the third embodiment, as in the case of the first and second embodiments, the semiconductor device 300 and the external circuit are electrically connected to each other by using a hemispherical solder provided at the tip of the terminal column 333. It is carried out by mounting it on a printed circuit board or the like through a terminal portion 333A consisting of.

【００２１】実施例３の半導体装置に使用のリードフレ
ーム３３０も、実施例１や実施例２にて使用のリードフ
レームと同様に、４２％ニッケル−鉄合金を素材とした
もので、図６（ａ）、図６（ｂ）に示すような形状をし
ており、リードフレーム素材と同じ厚さの端子柱部３３
３他の部分より薄肉に形成されたインナーリード先端部
３３１Ａをもつ。インナーリード先端部３３１Ａの厚さ
は４０μｍ、インナーリード先端部３３１Ａ以外の厚さ
は０．１５ｍｍで、強度的には後工程に充分耐えるもの
となっている。そして、インナーリードピッチは０．１
２ｍｍと狭いピッチで、半導体装置の多端子化に対応で
きるものとしている。インナーリード先端部３３１Ａの
第２面３３１Ａｂは平坦状でワイヤボンデイィングし易
い形状となっており、第３面３３１Ａｃ、第４面３３１
Ａｄはインナーリード側へ凹んだ形状をしており、第２
ワイヤボンディング面を狭くしても強度的に強いものと
している。また、実施例３の樹脂封止型半導体装置の作
製も、実施例１の場合とほぼ同じ工程にて行うが、ダイ
パッド３３５に半導体素子を搭載し固定した後に、封止
用樹脂にて樹脂封止する。The lead frame 330 used in the semiconductor device of Example 3 is also made of 42% nickel-iron alloy as in the case of the lead frame used in Examples 1 and 2, and is shown in FIG. a) and a terminal pillar portion 33 having a shape as shown in FIG. 6B and having the same thickness as the lead frame material.
3 It has an inner lead tip portion 331A formed thinner than other portions. The inner lead tip portion 331A has a thickness of 40 μm, and the thickness other than the inner lead tip portion 331A is 0.15 mm, which is sufficient in strength to withstand the subsequent steps. And the inner lead pitch is 0.1
With a narrow pitch of 2 mm, it is possible to cope with the multi-terminal of semiconductor devices. The second surface 331Ab of the inner lead tip portion 331A is flat and has a shape that facilitates wire bonding, and includes a third surface 331Ac and a fourth surface 331.
Ad has a shape that is recessed toward the inner lead side.
Even if the wire bonding surface is narrow, the strength is strong. The resin-sealed semiconductor device of Example 3 is also manufactured in substantially the same steps as in Example 1, except that the semiconductor element is mounted and fixed on the die pad 335, and then the resin is sealed with a sealing resin. Stop.

【００２２】実施例３の樹脂封止型半導体装置の変形例
としては、図２に示す実施例１の変形例の場合と同様
に、端子柱３３３の先端部に溝３３３Ｃ（図４（ｃ）
（ロ））を設け、封止用樹脂３４０から、突出させて、
端子柱の先端部をそのまま端子３３３Ａにしたものが挙
げられる。As a modification of the resin-encapsulated semiconductor device of the third embodiment, similar to the modification of the first embodiment shown in FIG. 2, a groove 333C (FIG. 4C) is formed at the tip of the terminal pillar 333.
(B)) is provided, and is projected from the sealing resin 340,
An example is one in which the tip portion of the terminal pillar is directly used as the terminal 333A.

【００２３】[0023]

【発明の効果】本発明の樹脂封止型半導体装置は、上記
のように、リードフレームを用いた樹脂封止型半導体装
置において、多端子化に対応でき、且つ、実装性良い半
導体装置の提供を可能としている。本発明の樹脂封止型
半導体装置は、これと同時に、従来の図１１（ｂ）に示
すアウターリードを持つリードフレームを用いた場合の
ようにダムバーのカット工程や、ダムバーの曲げ工程を
必要としないため、アウターリードのスキューの問題
や、平坦性（コープラナリティー）の問題を皆無として
いる。また、ＱＦＰやＢＧＡに比べるとパッケージ内部
の配線長が短かくなるため、寄生容量が小さくなり伝搬
遅延時間を短くすることを可能にしている。As described above, the resin-encapsulated semiconductor device of the present invention is a resin-encapsulated semiconductor device using a lead frame, which is capable of coping with multi-terminals and has good mountability. Is possible. At the same time, the resin-sealed semiconductor device of the present invention requires a dam bar cutting step and a dam bar bending step as in the case of using a conventional lead frame having outer leads shown in FIG. 11 (b). Therefore, the problem of outer lead skew and the problem of flatness (coplanarity) are eliminated. Further, since the wiring length inside the package is shorter than that of QFP or BGA, the parasitic capacitance is reduced and the propagation delay time can be shortened.

【図面の簡単な説明】[Brief description of drawings]

【図１】実施例１の樹脂封止型半導体装置の断面図FIG. 1 is a cross-sectional view of a resin-encapsulated semiconductor device according to a first embodiment.

【図２】実施例１の樹脂封止型半導体装置の変形例の図FIG. 2 is a diagram of a modified example of the resin-encapsulated semiconductor device according to the first embodiment.

【図３】実施例２の樹脂封止型半導体装置の断面図FIG. 3 is a sectional view of a resin-encapsulated semiconductor device of Example 2.

【図４】実施例３の樹脂封止型半導体装置の断面図FIG. 4 is a sectional view of a resin-encapsulated semiconductor device according to a third embodiment.

【図５】実施例１の樹脂封止型半導体装置の作製工程を
説明するための図5A to 5C are views for explaining a manufacturing process of the resin-encapsulated semiconductor device of Example 1.

【図６】本発明の樹脂封止型半導体装置に用いられるリ
ードフレームの図FIG. 6 is a diagram of a lead frame used in the resin-sealed semiconductor device of the present invention.

【図７】本発明の樹脂封止型半導体装置に用いられるリ
ードフレームの図FIG. 7 is a diagram of a lead frame used in the resin-sealed semiconductor device of the present invention.

【図８】本発明の樹脂封止型半導体装置に用いられるリ
ードフレームの作製方法を説明するための図FIG. 8 is a diagram for explaining a method for manufacturing a lead frame used in the resin-encapsulated semiconductor device of the present invention.

【図９】インナーリード先端部でのワイボンデイングの
結線状態を示す図FIG. 9 is a diagram showing a wire bonding state at the tip of the inner lead.

【図１０】従来のリードフレームのエッチング製造工程
を説明するための図FIG. 10 is a view for explaining a conventional lead frame etching manufacturing process.

【図１１】樹脂封止型半導体装置及び単層リードフレー
ムの図FIG. 11 is a diagram of a resin-sealed semiconductor device and a single-layer lead frame.

【符号の説明】[Explanation of symbols]

１００、１００Ａ、２００、３００ 樹
脂封止型半導体装置 １１０、２１０、３１０ 半
導体素子 １１１、２１１、３１１ 電
極（パッド） １２０、２２０、３２０ ワ
イヤ １２０Ａ、１２０Ｂ ワ
イヤ １２１Ａ、１２１Ｂ め
っき部 １３０、２３０、３３０ リ
ードフレーム １３１、２３１、３３１ イ
ンナーリード １３１Ａａ、２３１Ａａ、３３１Ａａ 第
１面 １３１Ａｂ、２３１Ａｂ、３３１Ａｂ 第
２面 １３１Ａｃ、２３１Ａｃ、３３１Ａｃ 第
３面 １３１Ａｄ、２３１Ａｄ、３３１Ａｄ 第
４面 １３１Ｂ、２３１Ｂ 連
結部 １３３、２３３、３３３ 端
子柱 １３３Ａ 端
子部 １３３Ｂ 側
面 １３３Ｃ 溝 １３６、２３６ ダ
ムバー １３７、２３７ フ
レーム（枠）部 １４０、２４０、３４０ 封
止用樹脂 １５０ 絶
縁性接着材 １６０、２６０、３６０ 補
強用テープ ２３５ ダ
イパッド ８１０ リ
ードフレーム素材 ８２０Ａ、８２０Ｂ レ
ジストパターン ８３０ 第
一の開口部 ８４０ 第
二の開口部 ８５０ 第
一の凹部 ８６０ 第
二の凹部 ８７０ 平
坦状面 ８８０ エ
ッチング抵抗層 ９２０Ｃ、９２０Ｄ、９２０Ｅ ワ
イヤ ９２１Ｃ、９２１Ｄ、９２１Ｅ め
っき部 ９３１Ｄ、９３１Ｅ イ
ンナーリード先端部 ９３１Ａａ リ
ードフレーム素材面 ９３１Ａｃ コ
イニング面 １０１０ リ
ードフレーム素材 １０２０ フ
オトレジスト １０３０ レ
ジストパターン １０４０ イ
ンナーリード １１１０ リ
ードフレーム １１１１ ダ
イパッド １１１２ イ
ンナーリード １１１２Ａ イ
ンナーリード先端部 １１１３ ア
ウターリード １１１４ ダ
ムバー １１１５ フ
レーム部（枠部） １１２０ 半
導体素子 １１２１ 電
極部（パッド） １１３０ ワ
イヤ １１４０ 封
止用樹脂100, 100A, 200, 300 Resin-sealed semiconductor device 110, 210, 310 Semiconductor element 111, 211, 311 Electrode (pad) 120, 220, 320 Wire 120A, 120B wire 121A, 121B Plated part 130, 230, 330 Lead Frame 131, 231, 331 Inner lead 131Aa, 231Aa, 331Aa 1st surface 131Ab, 231Ab, 331Ab 2nd surface 131Ac, 231Ac, 331Ac 3rd surface 131Ad, 231Ad, 331Ad 4th surface 131B, 231B Connection part 133, 233, 333 Terminal post 133A Terminal part 133B Side surface 133C Groove 136, 236 Dam bar 137, 237 Frame part 140, 240, 340 Sealing resin 150 Insulating adhesive 160, 260, 3 0 reinforcing tape 235 die pad 810 lead frame material 820A, 820B resist pattern 830 first opening 840 second opening 850 first recess 860 second recess 870 flat surface 880 etching resistance layer 920C, 920D, 920E Wire 921C, 921D, 921E Plated part 931D, 931E Inner lead tip part 931Aa Lead frame material surface 931Ac Coining surface 1010 Lead frame material 1020 Photo resist 1030 Resist pattern 1040 Inner lead 1110 Lead frame 1111 Inner lead tip 1112 13 Inner lead tip 1112A Inner lead part 1112A Outer lead 1114 Dam bar 1115 Frame part (frame part) 1120 Semiconductor element 1121 Extreme portion (pad) 1130 wire 1140 sealing resin

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 ２段エッチング加工によりインナーリー
ドの厚さがリードフレーム素材の厚さよりも薄肉に外形
加工されたリードフレームを用い、外形寸法をほぼ半導
体素子に合わせて封止用樹脂により樹脂封止したＣＳＰ
（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）型の半導体装置
であって、前記リードフレームは、リードフレーム素材
よりも薄肉のインナーリードと、該インナーリードに一
体的に連結したリードフレーム素材と同じ厚さの外部回
路と接続するための柱状の端子柱とを有し、且つ、端子
柱はインナーリードの外部側においてインナーリードに
対して厚み方向に直交し、かつ半導体素子搭載側と反対
側に設けられており、端子柱の先端面に半田等からなる
端子部を設け、端子部を封止用樹脂部から露出させ、端
子柱の外部側の側面を封止用樹脂部から露出させてお
り、半導体素子は、半導体素子の電極部を有する面に
て、インナーリード部に絶縁接着材を介して搭載されて
おり、半導体素子の電極部はインナーリード間に設けら
れ、半導体素子搭載側とは反対側のインナーリード先端
面とワイヤにて電気的に結線されていることを特徴とす
る樹脂封止型半導体装置。1. A lead frame in which an inner lead has a thickness thinner than that of a lead frame material by a two-step etching process is used. CSP stopped
A (ChipSize Package) type semiconductor device, wherein the lead frame is connected to an inner lead thinner than a lead frame material and an external circuit having the same thickness as the lead frame material integrally connected to the inner lead. A columnar terminal column for, and the terminal column is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and provided on the side opposite to the semiconductor element mounting side. A terminal portion made of solder or the like is provided on the tip end surface, the terminal portion is exposed from the sealing resin portion, and the external side surface of the terminal pillar is exposed from the sealing resin portion. It is mounted on the inner lead part via an insulating adhesive material on the surface having the electrode part, and the electrode part of the semiconductor element is provided between the inner leads and is mounted on the semiconductor element mounting side. Is a resin-encapsulated semiconductor device, which is electrically connected to the tip end surface of the inner lead on the opposite side with a wire. 【請求項２】 ２段エッチング加工によりインナーリー
ドの厚さがリードフレーム素材の厚さよりも薄肉に外形
加工されたリードフレームを用い、外形寸法をほぼ半導
体素子に合わせて封止用樹脂により樹脂封止したＣＳＰ
（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）型の半導体装置
であって、前記リードフレームは、リードフレーム素材
よりも薄肉のインナーリードと、該インナーリードに一
体的に連結したリードフレーム素材と同じ厚さの外部回
路と接続するための柱状の端子柱とを有し、且つ、端子
柱はインナーリードの外部側においてインナーリードに
対して厚み方向に直交し、かつ半導体素子搭載側と反対
側に設けられており、端子柱の先端の一部を封止用樹脂
部から露出させて端子部とし、端子柱の外部側の側面を
封止用樹脂部から露出させており、半導体素子は、半導
体素子の電極部を有する面にて、インナーリード部に絶
縁接着材を介して搭載されており、半導体素子の電極部
はインナーリード間に設けられ、半導体素子搭載側とは
反対側のインナーリード先端面とワイヤにて電気的に結
線されていることを特徴とする樹脂封止型半導体装置。2. A lead frame in which the thickness of the inner lead is externally processed by a two-step etching process to be thinner than the thickness of the lead frame material, and the external dimensions are approximately resin-encapsulated with a sealing resin in accordance with the semiconductor element. CSP stopped
A (ChipSize Package) type semiconductor device, wherein the lead frame is connected to an inner lead thinner than a lead frame material and an external circuit having the same thickness as the lead frame material integrally connected to the inner lead. A columnar terminal column for, and the terminal column is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and provided on the side opposite to the semiconductor element mounting side. A part of the tip is exposed from the encapsulating resin part to form the terminal part, and the external side surface of the terminal pillar is exposed from the encapsulating resin part. Are mounted on the inner leads via an insulating adhesive, the electrode parts of the semiconductor element are provided between the inner leads, and the inner leads on the side opposite to the semiconductor element mounting side are mounted. A resin-encapsulated semiconductor device, characterized in that it is electrically connected to the front end surface of the card by a wire. 【請求項３】 請求項１ないし２において、リードフレ
ームはダイパッドを有しており、半導体素子はその電極
部をインナーリード部とダイパッド部との間に設けてい
ることを特徴とする樹脂封止型半導体装置。3. The resin encapsulation according to claim 1, wherein the lead frame has a die pad, and the semiconductor element has its electrode portion provided between the inner lead portion and the die pad portion. Type semiconductor device. 【請求項４】 ２段エッチング加工によりインナーリー
ドの厚さがリードフレーム素材の厚さよりも薄肉に外形
加工されたリードフレームを用い、外形寸法をほぼ半導
体素子に合わせて封止用樹脂により樹脂封止したＣＳＰ
（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）型の半導体装置
であって、前記リードフレームは、リードフレーム素材
よりも薄肉のインナーリードと、該インナーリードに一
体的に連結したリードフレーム素材と同じ厚さの外部回
路と接続するための柱状の端子柱とを有し、且つ、端子
柱はインナーリードの外部側においてインナーリードに
対して厚み方向に直交し、かつ半導体素子搭載側と反対
側に設けられており、端子柱の先端面に半田等からなる
端子部を設け、端子部を封止用樹脂部から露出させ、端
子柱の外部側の側面を封止用樹脂部から露出させてお
り、半導体素子は、半導体素子の一面に設けられたバン
プを介してインナーリード部に搭載され、半導体素子と
インナーリード部とが電気的に接続していることを特徴
とする樹脂封止型半導体装置。4. A lead frame in which the thickness of the inner lead is externally processed by a two-step etching process to be thinner than the thickness of the lead frame material, and the external dimensions are approximately resin-encapsulated with a sealing resin in accordance with the semiconductor element. CSP stopped
A (ChipSize Package) type semiconductor device, wherein the lead frame is connected to an inner lead thinner than a lead frame material and an external circuit having the same thickness as the lead frame material integrally connected to the inner lead. A columnar terminal column for, and the terminal column is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and provided on the side opposite to the semiconductor element mounting side. A terminal portion made of solder or the like is provided on the tip end surface, the terminal portion is exposed from the sealing resin portion, and the external side surface of the terminal pillar is exposed from the sealing resin portion. A resin-sealed semiconductor, which is mounted on an inner lead portion via a bump provided on one surface, and a semiconductor element and the inner lead portion are electrically connected to each other. Body device. 【請求項５】 ２段エッチング加工によりインナーリー
ドの厚さがリードフレーム素材の厚さよりも薄肉に外形
加工されたリードフレームを用い、外形寸法をほぼ半導
体素子に合わせて封止用樹脂により樹脂封止したＣＳＰ
（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）型の半導体装置
であって、前記リードフレームは、リードフレーム素材
よりも薄肉のインナーリードと、該インナーリードに一
体的に連結したリードフレーム素材と同じ厚さの外部回
路と接続するための柱状の端子柱とを有し、且つ、端子
柱はインナーリードの外部側においてインナーリードに
対して厚み方向に直交し、かつ半導体素子搭載側と反対
側に設けられており、端子柱の先端の一部を封止用樹脂
部から露出させて端子部とし、端子柱の外部側の側面を
封止用樹脂部から露出させており、半導体素子は、半導
体素子の一面に設けられたバンプを介してインナーリー
ド部に搭載され、半導体素子とインナーリード部とが電
気的に接続していることを特徴とする樹脂封止型半導体
装置。5. A lead frame in which an inner lead has a thickness thinner than that of a lead frame material by a two-step etching process is used, and the outer dimensions are substantially resin-sealed with a sealing resin in accordance with a semiconductor element. CSP stopped
A (ChipSize Package) type semiconductor device, wherein the lead frame is connected to an inner lead thinner than a lead frame material and an external circuit having the same thickness as the lead frame material integrally connected to the inner lead. A columnar terminal column for, and the terminal column is provided on the outer side of the inner lead, orthogonal to the inner lead in the thickness direction, and provided on the side opposite to the semiconductor element mounting side. A part of the tip is exposed from the encapsulating resin part to form a terminal part, and the external side surface of the terminal pillar is exposed from the encapsulating resin part. The semiconductor element is a bump provided on one surface of the semiconductor element. A resin-encapsulated semiconductor device, characterized in that the semiconductor element and the inner lead portion are mounted on the inner lead portion through the electrical connection and are electrically connected to each other. 【請求項６】 請求項１ないし５において、インナーリ
ードは、断面形状が略方形で第１面、第２面、第３面、
第４面の４面を有しており、かつ第１面はリードフレー
ム素材と同じ厚さの他の部分の一方の面と同一平面上に
あって第２面に向き合っており、第３面、第４面はイン
ナーリードの内側に向かって凹んだ形状に形成されてい
ることを特徴とする樹脂封止型半導体装置。6. The inner lead according to claim 1, wherein the inner lead has a substantially rectangular cross section, and has a first surface, a second surface, a third surface,
The fourth surface has four surfaces, and the first surface is flush with one surface of the other portion having the same thickness as the lead frame material and faces the second surface. The fourth surface is formed so as to be recessed toward the inner side of the inner lead, and the resin-encapsulated semiconductor device is characterized.
JP7176898A 1995-06-21 1995-06-21 Resin sealed semiconductor device Pending JPH098207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7176898A JPH098207A (en) 1995-06-21 1995-06-21 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7176898A JPH098207A (en) 1995-06-21 1995-06-21 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH098207A true JPH098207A (en) 1997-01-10

Family

ID=16021688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7176898A Pending JPH098207A (en) 1995-06-21 1995-06-21 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH098207A (en)

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