JPH0298173A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH0298173A JPH0298173A JP25128188A JP25128188A JPH0298173A JP H0298173 A JPH0298173 A JP H0298173A JP 25128188 A JP25128188 A JP 25128188A JP 25128188 A JP25128188 A JP 25128188A JP H0298173 A JPH0298173 A JP H0298173A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate electrode
- layer
- silicon layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000002344 surface layer Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体記憶装置の製造方法に関し、特に不揮
発性半導体記憶装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor memory device, and particularly to a method of manufacturing a nonvolatile semiconductor memory device.
従来、制御ゲート電極と浮遊ゲート電極を有する不揮発
性半導体記憶装置の製造方法は、まず半導体記憶装置表
面に形成された酸化膜（第１ゲート酸化膜）上に浮遊ゲ
ート電極となる多結晶シリコン層を形成し、電気伝導を
良くするため熱拡散により高濃度の不純物添加を行なう
。この熱拡散時に酸化によって形成された多結晶シリコ
ン層表面のガラス層を除去した後、再び多結晶シリコン
層を熱酸化する。このとき多結晶シリコン層に添加され
た高濃度不純物によって形成される酸化膜は不純物が添
加されていない多結晶シリコン層に比べ酸化膜を厚く形
成できる（増速酸化）ことを利用し、浮遊ゲート電極と
制御ゲート電極との間の絶縁膜（以下第２ゲート酸化膜
と記す）を厚く形成する。その後、制御ゲート電極とな
る多結晶シリコン層を形成していた。Conventionally, in the manufacturing method of a nonvolatile semiconductor memory device having a control gate electrode and a floating gate electrode, a polycrystalline silicon layer that will become a floating gate electrode is first deposited on an oxide film (first gate oxide film) formed on the surface of the semiconductor memory device. A high concentration of impurities is added by thermal diffusion to improve electrical conduction. After removing the glass layer on the surface of the polycrystalline silicon layer formed by oxidation during this thermal diffusion, the polycrystalline silicon layer is thermally oxidized again. At this time, the oxide film formed by the high concentration impurity added to the polycrystalline silicon layer can be formed thicker than the polycrystalline silicon layer to which no impurity is added (accelerated oxidation). An insulating film (hereinafter referred to as a second gate oxide film) between the electrode and the control gate electrode is formed to be thick. After that, a polycrystalline silicon layer that would become a control gate electrode was formed.
上述した従来の不揮発性半導体記憶装置の製造方法では
、浮遊ゲート電極となる多結晶シリコン層に電気伝導を
良くするため高濃度不純物が添加されるので、第２ゲー
ト酸化膜を形成するため熱酸化した場合、酸化膜は厚く
形成され、浮遊ゲート電極と制御ゲート電極との間の耐
圧を高くすることができた。しかし、この製造方法では
記憶装置の動作電圧が高くなってしまう欠点がある。そ
こで動作電圧を低くするために、多結晶シリコン層に形
成される酸化膜を薄くしていくと酸化膜中の高濃度不純
物によって浮遊ゲート電極と制御ゲート電極との間のリ
ーク電流が増大するという欠点があった。In the conventional manufacturing method of nonvolatile semiconductor memory devices described above, a high concentration of impurity is added to the polycrystalline silicon layer that becomes the floating gate electrode to improve electrical conduction, so thermal oxidation is performed to form the second gate oxide film. In this case, the oxide film was formed thickly, and the breakdown voltage between the floating gate electrode and the control gate electrode could be increased. However, this manufacturing method has the disadvantage that the operating voltage of the memory device becomes high. Therefore, in order to lower the operating voltage, if the oxide film formed on the polycrystalline silicon layer is made thinner, the leakage current between the floating gate electrode and the control gate electrode will increase due to the high concentration of impurities in the oxide film. There were drawbacks.
また、浮遊ゲート電極を多結晶シリコンで形成した場合
は、多結晶シリコン粒径の成長および粒界面により絶縁
膜質の劣化を生じる欠点もあった。Furthermore, when the floating gate electrode is formed of polycrystalline silicon, there is also a drawback that the quality of the insulating film deteriorates due to the growth of the polycrystalline silicon grain size and the grain interface.
本発明の不揮発性半導体基板の製造方法は、半導体基板
表面に形成された第１のゲート酸化膜上に非晶質の第１
のシリコン層を形成する工程と、該第１のシリコン層を
熱処理する工程と、該熱処理された第１のシリコン層表
層に形成された酸化膜を除去する工程と、該第１のシリ
コン層表層に所望の厚さの第２のゲート酸化膜を形成す
る工程と、該第２のゲート酸化膜上に多結晶シリコンの
第２のシリコン層を形成する工程とを有している。The method for manufacturing a nonvolatile semiconductor substrate of the present invention includes forming an amorphous first gate oxide film on a first gate oxide film formed on a surface of a semiconductor substrate.
a step of heat-treating the first silicon layer; a step of removing an oxide film formed on the surface layer of the heat-treated first silicon layer; and a step of removing the oxide film formed on the surface layer of the first silicon layer. and forming a second silicon layer of polycrystalline silicon on the second gate oxide film.
そのため第２のゲート酸化膜を薄く形成しても不純物に
よるリーク電流の発生を防ぐことができる。Therefore, even if the second gate oxide film is formed thin, leakage current due to impurities can be prevented from occurring.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を示す工
程断面図である。Ｐ型シリコン半導体基板ｌ上にシリコ
ン酸化膜（Ｓ ｉ Ｏ，膜）およびシリコン窒化膜（Ｓ
ｉｓＮｓ膜）（図示せず）の２層を選択的に形成した後
、第１図（ａ）に示すように、露出した基板表面を熱酸
化して５ｉｎ２からなるフィールド酸化膜２を形成する
。次に５ｉｘＮ＜膜と５ｉｎ２膜を除去し、例えば９０
０℃で湿式酸化を行ない厚さ４０ｎｍの第１ゲート酸化
膜３を形成する。次にしきい値電圧制御のためのポロン
イオンをエネルギー５０ＫｅＶ、ドーズ量６ Ｘ １０
”ｃｍ−”で打ち込む０次に基板を、たとえば４００
℃に加熱し５ｉｚＨａガスを高周波放電によって分解し
、プラズマ気相成長法により非晶質シリコン（以下アモ
ルファスシリコンと記す）を基板全面に２５０ｎｍの厚
さに堆積させる。こうして形成された７モルファシスシ
リコン層４を選択的にパターニングすることによって浮
遊ゲート電極形成のための第１次加工を行ない、第１図
（ａ）の図面に垂直方向のチャネル部の寸法を規定する
。次に９００℃で乾式酸化を行ない、引き続き酸素と不
活性ガスの混合雰囲気中で１０００℃１時間の熱処理を
行ない７モルファシスシリコン層４の結晶化ヲ行すう、
この時シリコン層４′表面に形成される酸化膜を除去し
た後９００℃で湿式酸化を行ない、厚さ３０ｎｍの第２
ゲート酸化膜５を結晶化されたシリコン層り′上に形成
する。その後第１図（ｂ）に示すように、全面に多結晶
シリコン６を化学気相成長により厚さ４００ｎｍ堆積さ
せリンを熱拡散により飽和濃度近くまで添加し、伝導性
を良くし多結晶シリコン層６の上にフォトレジスト膜を
塗布しバターニングを行ないフォトレジストマスク７を
形成する。次に第１図（ｃ）に示すように反応性イオン
エツチングにより多結晶シリコン層６を加工し制御ゲー
ト電極６′を形成する。続けて反応性イオンエツチング
により第２ゲート酸化膜５とシリコン層４′をエツチン
グすることにより浮遊ゲート電極４″の第２次加工を行
ない、浮遊ゲート電極４′を制御ゲート電極６′と自己
整合的に形成する。次にフォトレジストマスク７を除去
し浮遊ゲート電極４″の露出した側面部に絶縁膜を形成
するために９００℃で乾式酸化を行ない厚さ２０ｎｍの
側面酸化膜８を形成し制御ゲート電極６′をマスクにヒ
素イオンをエネルギー７０Ｋ ｅ Ｖ ｓ ドーズ量
Ｉ Ｘ Ｉ Ｏ”ａｎ−”で打ち込んだ後、酸素と不活
性ガスの混合雰囲気中で１０００℃３０分の熱処理を行
ない、ｎ＋型のソース領域９およびドレイン領域１０を
形成する。さらに第１図（ｄ）に示すようにリンガラス
からなる層間絶縁膜１１を堆積させ、ソース、ドレイン
領域９，１０にコンタクト孔１２−１．１２−２を開孔
した後制御ゲート電極配線（図示せず）、ソース電極配
線１３およびドレイン電極１４をアルミニウムで形成す
る。FIGS. 1(a) to 1(d) are process cross-sectional views showing a first embodiment of the present invention. A silicon oxide film (SiO, film) and a silicon nitride film (S
After selectively forming two layers of the isNs film (not shown), the exposed substrate surface is thermally oxidized to form a field oxide film 2 of 5 in 2 as shown in FIG. 1(a). Next, remove the 5ixN< film and the 5in2 film, e.g.
Wet oxidation is performed at 0° C. to form a first gate oxide film 3 with a thickness of 40 nm. Next, poron ions were used for threshold voltage control at an energy of 50 KeV and a dose of 6 x 10
For example, the zero-order board to be implanted with "cm-" is 400
℃, 5izHa gas is decomposed by high frequency discharge, and amorphous silicon (hereinafter referred to as amorphous silicon) is deposited to a thickness of 250 nm over the entire surface of the substrate by plasma vapor deposition. The thus formed 7-morphosis silicon layer 4 is selectively patterned to perform the first processing for forming a floating gate electrode, and the dimensions of the channel portion in the vertical direction are defined in the drawing of FIG. 1(a). do. Next, dry oxidation is performed at 900°C, followed by heat treatment at 1000°C for 1 hour in a mixed atmosphere of oxygen and inert gas to crystallize the 7-morphosis silicon layer 4.
At this time, after removing the oxide film formed on the surface of the silicon layer 4', wet oxidation was performed at 900°C to form a second layer with a thickness of 30 nm.
A gate oxide film 5 is formed on the crystallized silicon layer. Thereafter, as shown in FIG. 1(b), polycrystalline silicon 6 is deposited to a thickness of 400 nm on the entire surface by chemical vapor deposition, and phosphorus is added to near saturation concentration by thermal diffusion to improve conductivity and form a polycrystalline silicon layer. A photoresist film is applied on 6 and patterned to form a photoresist mask 7. Next, as shown in FIG. 1(c), the polycrystalline silicon layer 6 is processed by reactive ion etching to form a control gate electrode 6'. Subsequently, the second gate oxide film 5 and silicon layer 4' are etched by reactive ion etching to perform secondary processing of the floating gate electrode 4'', and the floating gate electrode 4' is self-aligned with the control gate electrode 6'. Next, the photoresist mask 7 is removed, and in order to form an insulating film on the exposed side surfaces of the floating gate electrode 4'', dry oxidation is performed at 900° C. to form a side oxide film 8 with a thickness of 20 nm. Using the control gate electrode 6' as a mask, arsenic ions are implanted at an energy of 70 K e V s and a dose of I X I O "an-", followed by heat treatment at 1000° C. for 30 minutes in a mixed atmosphere of oxygen and inert gas. An n+ type source region 9 and drain region 10 are formed. Furthermore, as shown in FIG. 1(d), an interlayer insulating film 11 made of phosphorus glass is deposited, and contact holes 12-1 and 12-2 are opened in the source and drain regions 9 and 10, and then the control gate electrode wiring ( (not shown), the source electrode wiring 13 and the drain electrode 14 are formed of aluminum.
第２図は本発明の第２の実施例を説明するための不揮発
性半導体記憶装置の断面図である。FIG. 2 is a sectional view of a nonvolatile semiconductor memory device for explaining a second embodiment of the present invention.
フィールド酸化膜２を第１の実施例と同じように形成し
た後、ドレイン領域１０を形成する。次に第１ゲート酸
化膜３を形成した後、トンネル領域を形成するために選
択的に第１ゲート酸化膜３をエツチングし、９００℃の
乾式酸化により９ｎｍのトンネル酸化膜５を形成する。After field oxide film 2 is formed in the same manner as in the first embodiment, drain region 10 is formed. Next, after forming the first gate oxide film 3, the first gate oxide film 3 is selectively etched to form a tunnel region, and a 9 nm thick tunnel oxide film 5 is formed by dry oxidation at 900°C.
それ以降は第１の実施例と同様に形成する。The subsequent steps are formed in the same manner as in the first embodiment.
以上説明したように本発明では浮遊ゲート電極をアモル
ファスシリコンで形成するため多結晶シリコンのように
絶縁膜のリーク電流を増加させるように悪影響を及ぼす
ことがなく、従って浮遊ゲート電極と制御ゲート電極と
の間の絶縁膜を薄くでき低電圧で動作する不揮発性半導
体記憶装置を実現できる効果がある。As explained above, in the present invention, since the floating gate electrode is formed of amorphous silicon, it does not have the adverse effect of increasing the leakage current of the insulating film unlike polycrystalline silicon, and therefore the floating gate electrode and the control gate electrode are This has the effect of making it possible to thin the insulating film between the layers, thereby realizing a nonvolatile semiconductor memory device that operates at low voltage.
第１図（ａ）〜（ｄ）は本発明の第１の実施例を示す断
面工程図、第２図は本発明の第２の実施例を示す断面図
である。
■・・・・・・Ｐ型シリコン半導体基板、２・・川・フ
ィールド酸化膜、３・−・・・・第１ゲート酸化膜、４
・・・・・・アモルファスシリコン層、４′・・川・結
晶化サレタシリコン層、４″・・・・・・浮遊ゲート電
極、５・・・・・・第２ゲート酸化膜、６・・・・・・
多結晶シリコンシリコン層、６′・・・・・・制御ゲー
ト電極、７・旧・・フォトレジストマスク、８・・・・
・・側面酸化膜、９・・印・ソース領域、ＩＯ・・・・
・・ドレイン領域、１１・旧・・層間絶縁膜、１２−１
．１２−２．１２−３・・団・コンタクト孔、１３・・
・・・・ソース電極配線、１４・・・・・・ドレイン電
極配線、１５・・・・・・トンネル酸化膜、１６・・団
・制御ゲート電極配線。
代理人 弁理士 内 原 晋
／ｌ１ｌ）
月Ｚ図
万１回FIGS. 1A to 1D are cross-sectional process diagrams showing a first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a second embodiment of the present invention. ■... P-type silicon semiconductor substrate, 2... River/field oxide film, 3... First gate oxide film, 4
...Amorphous silicon layer, 4'... Crystallized silicon layer, 4''... Floating gate electrode, 5... Second gate oxide film, 6...・・・・・・
Polycrystalline silicon silicon layer, 6'... Control gate electrode, 7. Old... Photoresist mask, 8...
... Side oxide film, 9... mark, source region, IO...
...Drain region, 11.Old...Interlayer insulating film, 12-1
．． 12-2.12-3...Group/contact hole, 13...
... Source electrode wiring, 14... Drain electrode wiring, 15... Tunnel oxide film, 16... Group control gate electrode wiring. Agent: Susumu Uchihara, patent attorney
Claims (1)
第１のシリコン層を形成する工程と、該第１のシリコン
層を熱処理する工程と、該熱処理された第１のシリコン
層表層の酸化膜を除去する工程と、該第１のシリコン層
表面に第２の絶縁膜を形成する工程と、該第２の絶縁膜
上に多結晶の第２のシリコン層を形成する工程と、該第
２のシリコン層と前記第２の絶縁膜と前記第１のシリコ
ン層とを所定の形状にエッチングする工程とを含むこと
を特徴とする半導体記憶装置の製造方法。a step of forming an amorphous first silicon layer on a first insulating film formed on a surface of a semiconductor substrate; a step of heat-treating the first silicon layer; and a step of heat-treating the first silicon layer. a step of removing a surface layer oxide film; a step of forming a second insulating film on the surface of the first silicon layer; and a step of forming a polycrystalline second silicon layer on the second insulating film. A method of manufacturing a semiconductor memory device, comprising: etching the second silicon layer, the second insulating film, and the first silicon layer into a predetermined shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25128188A JPH0298173A (en) | 1988-10-04 | 1988-10-04 | Manufacture of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25128188A JPH0298173A (en) | 1988-10-04 | 1988-10-04 | Manufacture of semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0298173A true JPH0298173A (en) | 1990-04-10 |
Family
ID=17220468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25128188A Pending JPH0298173A (en) | 1988-10-04 | 1988-10-04 | Manufacture of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0298173A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521943B1 (en) * | 1997-03-19 | 2003-02-18 | Hitachi, Ltd. | Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture |
-
1988
- 1988-10-04 JP JP25128188A patent/JPH0298173A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521943B1 (en) * | 1997-03-19 | 2003-02-18 | Hitachi, Ltd. | Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture |
| US6723625B2 (en) | 1997-03-19 | 2004-04-20 | Renesas Technology Corporation | Semiconductor device having thin electrode laye adjacent gate insulator and method of manufacture |
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