JPH0291940A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0291940A JPH0291940A JP24233088A JP24233088A JPH0291940A JP H0291940 A JPH0291940 A JP H0291940A JP 24233088 A JP24233088 A JP 24233088A JP 24233088 A JP24233088 A JP 24233088A JP H0291940 A JPH0291940 A JP H0291940A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- incidence angle
- copper
- titanium nitride
- incident angle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000000992 sputter etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 27
- 238000004544 sputter deposition Methods 0.000 claims description 18
- 239000010410 layer Substances 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 229910052720 vanadium Inorganic materials 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000001755 magnetron sputter deposition Methods 0.000 abstract 1
- 238000001228 spectrum Methods 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 12
- 229910052786 argon Inorganic materials 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 9
- -1 copper halides Chemical class 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 150000002366 halogen compounds Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
【発明の目的】
（産業上の利用分野）
この発明は半導体装置の製造方法に係り、特に反応性イ
オンエツチングが困難な材料を用いた配線の半導体装置
上への形成方法に関する。
（従来の技術）
近年、半導体装置の高集積化に伴い、配線幅および厚さ
の縮小化、および多層配線化が進められてきている。配
線材料としては２７５μΩ・ｌという低い比抵抗を有し
、かつ不動態被覆によって防食されるアルミニウムを主
成分とするアルミニウム合金が用いられてきた。しかし
ながら、配線断面積の縮小化に対し、信号電流は低減化
されないため、電流密度が増加しエレクトロマイグレー
ションによる配線がますます問題となってくる。
また多層配線化に伴い、配線は複雑な熱履歴を受けるた
め、配線に加わる熱ストレスによるストレスマイグレー
ションでの配線も問題となってきた。
これらのＥｆｆｉの主要因は、アルミニウムの融点が６
６０℃と低いため比較的低温度でも原子の拡散特に結晶
粒界を経路とする拡散が起こり易く、更に熱ストレスに
よる引張応力が配線に生じた場合にはこの原子各点が加
速される事である。そこで、アルミニウムと同等以上の
低い比抵抗を有しかつアルミニウムより高融点である銅
により配線が検討され始めている。
しかしながら、銅はアルミニウムのような反応性イオン
エツチング（ＲＩ Ｅ）法により配線パターン形成技術
が確立されていない。この理由は主として次の２点であ
る。第１に、アルミニウムの場合には塩素系ガスを用い
たＲＩＥにおける生成物アルミニウムクロライドの蒸気
圧が通常のＲＩＥで用いられる温度および圧力領域にお
いて比較的高いために、クロライドは容易に排気されア
ルミニウムのエツチングが進行する。一方、銅のハロゲ
ン化物はいずれも蒸気圧が低く、通常のＲＩＥで用いら
れる圧力領域であるＩＰＡ以上では昇華・排気され難い
事である。
第２に、銅においても基板を加熱する事によりＲＩＥエ
ツチングされる事が報告されている。しかし、加熱によ
ってマスクであるレジストのエツチングも加速されて銅
のエツチング形状が悪化する事、および銅とレジストと
エツチングガスとによる銅・炭素・酸素ハロゲン化合物
の堆積も混合する事にために、未だ実用化されるに至っ
ていない。
そこで、銅の配線パターン形成にはウェットエツチング
または反応性ガスを用いないスパッタエツチングが採用
されている。しかしながら、ウェットエツチングはウェ
ハー面内でのエツチング均一性が悪い事および微細パタ
ーンのエツチング制御性が悪い事の問題があり、半導体
装置の高ｍ積化には適さない。一方、スパッタエツチン
グではウェットエツチングにおける上述の２点は克服さ
れる。しかし、第２図（ａ）に示すようにエツチングさ
れるべき領域からの再スパツタ粒子が側壁に再付着して
いわゆるｄｏｇ ｅａｒを形成したり、あるいは第２図
（ｂ）に示すように側壁からの再スパツタ粒子が底部に
再付着していわゆるすそ引き残渣を形成したり、あるい
は両者が混合して第２図（ｃ）に示すように側壁のテー
パーを形成したりする問題があった。またこの問題はス
パッタエツチングにおけるエツチングマスク材料にレジ
ストよりも高温耐性があり、しかも銅よりもスパッタ速
度が小さい二酸化硅素（Ｓ１０２）あるいは窒化チタン
（Ｔｉ Ｎ）等を採用した場合に助長される。この理由
は、シリコンやチタン等のスパッタ収率の小さい元素を
含んだマスク材料がまずスパッタエツチングされるため
にレジスト側壁がスパッタエツチング速度の遅い再スパ
ツタ付着膜で覆われ、更にこの再付着膜の上に銅等の配
線主材からの再付着膜が積層付着する事により、再付着
膜の除去が困難となる事である。
（発明が解決しようとする課届ａ−＞
反応性ガスを用いないスパッタエツチング法は、ＲＩＥ
のようにエツチング材料間で高い選択性は有しないが、
逆にいかなる材料でもエツチング可能である利点をもっ
ている。スパッタエツチングは通常２二５ Ｘ １０
””Ｔｏｒｒのアルゴン（Ａ「）雰囲気において高周波
放電によりアルゴンイオン（Ａｒ ）を発生し６００Ｖ
程度に加速して披エツチング材料に入射させ、アルゴン
イオンによるスパッタリーング効果によってエツチング
を行う。比較的抵抗中でアルゴンイオンが加速され被エ
ツチング材料に入射するためエツチング形状はイオン入
射角度に保存した異方性の強い形状となる筈であるが、
前記のような再付着膜の発生によってエツチング形状の
制御は現実には困難である。特に銅を主成分とする配線
の場合には、エツチングマスク材としてのみでなく、下
地の層間絶縁酸化膜と銅との密着性を向上させることを
目的とした下敷接着層あるいは、配線形成後のプロセス
における銅の酸化を防止することを目的とした表面酸化
防止膜を有する積層構造配線となる。しかもこのような
性質を有する材料の構成元素はすべて銅と比べて数分の
１という小さいスパッタ収率を示し、厚い再付着膜が形
成される。
そこで本発明は、スパッタ収率の異なる材料かになる積
層構造配線のスパッタエツチングに際し、再付着膜によ
ってエツチング形状を悪化させる事なく、微細配線パタ
ーンを形成するための半導体装置の製造方法を提出する
事を目的とする。
［発明の構成］
（３題を解決するための手段）
本発明の骨子はスパッタ収率の異なる材料からなる積層
構造配線の各層へのスパッタリングイオンの主面法線と
なす角度で定義する入射角度を変化させてスパッタエツ
チングを行う事にある。
すなわち、スパッタ収率の小さい材料からなる層へのイ
オン入射角度を、スパッタ収率の大きい材料からなる層
へのイオン入射角度よりも大きく、つまり基板主面法線
に対してより大きな傾斜角度とし、更に配線層の全厚が
丁度エツチングされた後に、より大きなイオン入射角度
および基板主面にほぼ垂直の２方向の入射角度で交互に
エツチングを行い再付着膜を除去する事とした半導体装
置の製造方法である。
（作用）
従来のスパッタエツチングによる配線バターニングでは
、レジストマスクの後退を抑えるためにＳｉＯ２あるい
はＴＩＮのようなマスク材料を用いた場合、スパッタリ
ングラオンの入射角度が基板主面に垂直で一定であった
ため、厚い再付着膜が形成され、配線形状は大きなテー
パーを有しており、配線幅１μｍ以下の微細配線パター
ンの形成はできなかった。ところが、本発明のエツチン
グ方法によれば、スパッタ収率のイオン入射角度依存性
が金をのぞいて垂直入射から４５６傾斜入射まで次第に
増加し、更に大きな傾斜角度では急激に減少する傾向を
示すことを利用して、スパッタ収率の小さい材料からな
る層のエツチングに際しては、イオン入射角度を基板主
面法線に対して大きな傾斜角度 （θ）とする事により
、スパッタ収率を増加させエツチング速度を増加させる
と共に側壁へのイオン入射角度は側壁法線に対し微小角
度（＝０”）から９０＠−〇に増加するので側壁再付着
膜の成長が抑制される。次いでスパッタ収率の大きい材
料からなる層のエツチングに再しては、イオン入射角度
が小さくても充分なエツチング速度が得られると共に、
スパッタ収率の小さいマスク材のエツチング速度が小さ
いためマスクの後退が防止され、パターン寸法は維持さ
れる。
また、配線層の全厚が丁度エツチングされた後に、より
大きな傾斜角度θ′ （θ′〉θ）で側壁再付着膜いわ
ゆるｄｏｇ ｅａｒの除去と基板主面に垂直に近い（＝
０＠）角度でいわゆるすそ引き残渣の除去とを交互に行
う事により相隣る配線間でのショート不良がなくかっテ
ーパーのないエツチング形状を有する配線パターンを形
成する事が可能である。
（実施例）
以下、本発明の詳細を図示の実施例によって説明する。
第１図（ａ）に示すように、層間絶縁ＩＩ １０２が形
成された基板１０１上に窒化チタン１０３／銅１０４／
窒化チタン１０５なる積層膜をＤＣマグネトロンススフ
ブタ法成膜する。この時窒化チタン１０３，１０５の膜
厚はいずれも５００人、銅１０４の膜厚は４０００人で
あった。次に第１図（ｂ）に示すように、リソグラフィ
法によりレジストパターン１０６を形成する。この時レ
ジストパターン１０６の膜厚は１．２μｍ１配線幅は０
．５μｍ配線間隔は０．８μｍであった。次に第１図（
Ｃ）に示すように、アルゴン圧力２．０×１０−’Ｔｏ
ｒｒで１３．５６ＭＨｚ高周波放電により発生させたア
ルゴンプラズマ中のアルゴンイオンを５ｏｏｖで加速し
電流密度０．７ｍＡ／ｃｄの強度のアルゴンイオンシャ
ワー１０７として、基板に照射し、窒化チタン１０３を
スパッタエツチングする。この時、イオンシャワー１０
７の入射角度は基板１０１主面法線に対し３０°傾斜さ
せた。また、基板は主面平面内で回転させていた。この
条件で窒化チタン１０３は約５分でエツチングされたこ
とをＴｉからの発光スペクトル変化で確認した。次に第
１図（ｄ）に示すように、イオンシャワー１０７の入射
角度を１５°まで戻して銅１０４をスパッタエツチング
した。このとき銅１０４は約８分でエツチングされた。
次いで１１図（ｅ）に示すように、イオンシャワー１０
７の入射角度を再度３０＠まで増加させ窒化チタン１０
５をスパッタエツチングした。この時窒化チタン１０５
は約５分でエツチングされた。以上のエツチングが終了
した時点で形成された窒化チタン／銅／窒化チタン禎層
配線１０８の側壁および配線間隙にはｄｏｇ ｅａｒ
１０９およびすそ引き残渣１１０が残渣として残った。
ｄｏｇ ｅａｒ １０９の厚みは約１０００人高さは約
４０００人、すそ引き残漬１１０は厚みは約５００人、
広がりは約３０００人であった。次いで第１ＥＩＤ（ｒ
＞に示すように、イオンシャワー１０７の入射角度を４
５″として３分間スパッタエツチングした。この時点で
ｄｏｇ ｅａｒ １０９はエツチングされて消滅した。
次いで第１図（ｇ）に示すように、イオンシャワー１０
７の入射角度を０°として３分間スパッタエツチングし
た。この時点ですそ引き残渣１１０はエツチングされて
消滅した。以上のエツチング工程によりテーパーのない
断面形状を有する配線幅０．５μ■１配線間隔０．８μ
ｍの積層配線１０８が形成された。
尚、積層構造は窒化チタン／銅／窒化チタンに限定され
る事なく、窒化チタンの変わりにクロム（Ｃｒ）、ニオ
ブ（Ｎ ｂ）、 タンタル（Ｔ ａ）あるいはそれらの
窒化物やホウ化物あるいは二酸化シリコン（ＳＩＯ）、
窒化シリコン（Ｓ１３Ｎ４）でもよい。また銅に限定さ
れる事なく、銅を主成分とする合金でもよい。
さらに、本発明はその主旨を逸脱しない範囲内で種々変
形して実施する事ができる。
〔発明の効果〕
本発明によれば、反応性イオンエツチングの困難な銅の
ような配線材料でかつスパッタ収率の異なる材料からな
る積層構造配線をスパッタエツチングで形成する際に、
ｄｏｇ ｃａｒやすそ引き残渣のないテーパーのない形
状を有する微細配線パターンが形成できる。したがって
、許容電流密度が高くしかも信号遅延の小さい高信頼性
微細配線が実現できる。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and in particular, the formation of wiring on a semiconductor device using a material that is difficult to perform reactive ion etching. Regarding the method. (Prior Art) In recent years, as semiconductor devices have become highly integrated, wiring widths and thicknesses have been reduced, and multilayer wiring has been developed. As a wiring material, an aluminum alloy mainly composed of aluminum has been used, which has a low specific resistance of 275 μΩ·l and is protected against corrosion by a passive coating. However, as the cross-sectional area of the wiring is reduced, the signal current is not reduced, so the current density increases and wiring caused by electromigration becomes increasingly problematic. Furthermore, with multilayer wiring, wiring is subject to complex thermal history, and stress migration due to thermal stress applied to wiring has also become a problem. The main reason for these Effi is that the melting point of aluminum is 6
Because it is as low as 60°C, atomic diffusion, especially diffusion via grain boundaries, is likely to occur even at relatively low temperatures.Furthermore, when tensile stress due to thermal stress is generated in the wiring, each atomic point is accelerated. be. Therefore, studies have begun to consider wiring using copper, which has a resistivity as low as or higher than aluminum and has a higher melting point than aluminum. However, unlike aluminum, wiring pattern formation technology has not been established for copper using the reactive ion etching (RIE) method. This is mainly due to the following two points. First, in the case of aluminum, the vapor pressure of the product aluminum chloride in RIE using chlorine-based gas is relatively high in the temperature and pressure range used in normal RIE, so the chloride is easily exhausted and Etching progresses. On the other hand, all copper halides have low vapor pressures and are difficult to sublime and exhaust at pressures above IPA, which is the pressure range used in normal RIE. Second, it has been reported that copper can also be RIE etched by heating the substrate. However, heating also accelerates the etching of the resist that serves as a mask, deteriorating the etched shape of the copper, and also causes the deposition of copper, carbon, oxygen, and halogen compounds from the copper, resist, and etching gas to be mixed together. It has not yet been put into practical use. Therefore, wet etching or sputter etching that does not use reactive gas is used to form copper wiring patterns. However, wet etching has the problems of poor etching uniformity within the wafer surface and poor etching controllability of fine patterns, and is not suitable for increasing the thickness of semiconductor devices. On the other hand, sputter etching overcomes the two points mentioned above in wet etching. However, as shown in FIG. 2(a), re-sputter particles from the area to be etched may re-deposit on the sidewall and form a so-called dog ear, or as shown in FIG. There is a problem in that the re-spatter particles re-adhere to the bottom part and form a so-called hem-pulling residue, or the two are mixed to form a tapered side wall as shown in FIG. 2(c). This problem is further aggravated when silicon dioxide (S102) or titanium nitride (TiN), which has higher temperature resistance than resist and lower sputtering speed than copper, is used as an etching mask material in sputter etching. The reason for this is that mask materials containing elements with low sputtering yields, such as silicon and titanium, are first sputter-etched, so the resist sidewalls are covered with a re-sputtered film that has a slow sputter-etching rate. If a redeposited film from the wiring main material such as copper is layered on top of the wiring, it becomes difficult to remove the redeposited film. (Section a that the invention seeks to solve-> Sputter etching method that does not use reactive gas is RIE
Although it does not have high selectivity between etching materials like
On the contrary, it has the advantage that any material can be etched. Sputter etching is usually 225 x 10
Argon ions (Ar) are generated by high-frequency discharge in an argon (A) atmosphere of 600V at Torr.
The argon ions are accelerated to a certain degree and incident on the etching material, and etching is performed by the sputtering effect of argon ions. Since the argon ions are accelerated and incident on the material to be etched in a relatively resistive environment, the etched shape should be a strongly anisotropic shape that is maintained at the ion incidence angle.
In reality, it is difficult to control the etching shape due to the occurrence of the re-deposited film as described above. In particular, in the case of wiring whose main component is copper, it is used not only as an etching mask material, but also as an underlay adhesive layer for the purpose of improving the adhesion between the underlying interlayer insulating oxide film and the copper, or after wiring formation. This results in a laminated structure wiring having a surface oxidation prevention film for the purpose of preventing oxidation of copper during the process. Furthermore, all the constituent elements of the material having such properties exhibit a sputtering yield that is several times lower than that of copper, and a thick redeposited film is formed. Therefore, the present invention proposes a semiconductor device manufacturing method for forming a fine wiring pattern without deteriorating the etched shape due to a re-deposited film when sputter etching a laminated structure wiring made of materials with different sputtering yields. aim at something. [Structure of the Invention] (Means for Solving the Three Problems) The gist of the present invention is to reduce the incident angle defined by the angle formed with the normal to the main surface of sputtered ions to each layer of a layered structure wiring made of materials with different sputtering yields. The purpose is to perform sputter etching by changing the In other words, the angle of ion incidence on a layer made of a material with a low sputtering yield is made larger than the angle of ion incidence on a layer made of a material with a high sputtering yield, that is, the angle of inclination is made larger with respect to the normal to the main surface of the substrate. Furthermore, after the entire thickness of the wiring layer has been etched, etching is performed alternately at a larger ion incidence angle and at an incidence angle in two directions approximately perpendicular to the main surface of the substrate to remove the redeposited film. This is the manufacturing method. (Function) In conventional wiring patterning by sputter etching, when a mask material such as SiO2 or TIN is used to suppress the retreat of the resist mask, the incident angle of the sputtering ion is perpendicular to the main surface of the substrate and is constant. A thick redeposited film was formed, and the wiring shape had a large taper, making it impossible to form a fine wiring pattern with a wiring width of 1 μm or less. However, according to the etching method of the present invention, the dependence of the sputtering yield on the ion incidence angle gradually increases from normal incidence to 456 oblique incidence, except for gold, and shows a tendency to sharply decrease at larger inclination angles. When etching a layer made of a material with a low sputter yield, the ion incidence angle can be set to a large angle (θ) with respect to the normal to the main surface of the substrate to increase the sputter yield and speed up the etching rate. As the sputtering rate increases, the ion incidence angle on the sidewall increases from a small angle (=0'') to the sidewall normal to 90＠-〇, which suppresses the growth of the sidewall re-deposition film. When etching another layer, a sufficient etching rate can be obtained even if the ion incidence angle is small, and
Since the etching rate of the mask material with a low sputtering yield is low, the mask is prevented from retreating and the pattern dimensions are maintained. In addition, after the entire thickness of the wiring layer has been etched, the sidewall redeposited film, so-called dog ear, is removed at a larger inclination angle θ'(θ'〉θ) and the sidewall re-deposited film is etched close to perpendicular to the main surface of the substrate (=
By alternately removing so-called skirting residue at an angle of 0@), it is possible to form a wiring pattern that is free from short-circuit defects between adjacent wirings and has a non-tapered etched shape. (Example) Hereinafter, the details of the present invention will be explained by referring to the illustrated example. As shown in FIG. 1(a), titanium nitride 103/copper 104/
A laminated film of titanium nitride 105 is formed by a DC magnetron transfer method. At this time, the thickness of the titanium nitrides 103 and 105 was 500, and the thickness of the copper 104 was 4,000. Next, as shown in FIG. 1(b), a resist pattern 106 is formed by lithography. At this time, the film thickness of the resist pattern 106 is 1.2 μm, and the wiring width is 0.
．． The 5 μm wiring spacing was 0.8 μm. Next, Figure 1 (
As shown in C), the argon pressure is 2.0 x 10-'To
Argon ions in argon plasma generated by 13.56 MHz high-frequency discharge at rr are accelerated at 5 oov and irradiated onto the substrate as an argon ion shower 107 with a current density of 0.7 mA/cd to sputter-etch titanium nitride 103. . At this time, ion shower 10
The incident angle of No. 7 was set at an angle of 30° with respect to the normal to the principal surface of the substrate 101. Further, the substrate was rotated within the principal plane. It was confirmed by the change in the emission spectrum from Ti that the titanium nitride 103 was etched in about 5 minutes under these conditions. Next, as shown in FIG. 1(d), the incident angle of the ion shower 107 was returned to 15° to sputter-etch the copper 104. At this time, the copper 104 was etched in about 8 minutes. Next, as shown in FIG. 11(e), the ion shower 10
Increase the incident angle of 7 to 30@ again and titanium nitride 10
5 was sputter etched. At this time, titanium nitride 105
was etched in about 5 minutes. Dog ears are formed on the side walls and wiring gaps of the titanium nitride/copper/titanium nitride layer wiring 108 formed when the above etching is completed.
109 and a skirting residue 110 remained as residues. The thickness of dog ear 109 is about 1,000 people, and the height is about 4,000 people, and the thickness of dog ear 110 is about 500 people.
The spread was about 3,000 people. Then the first EID (r
As shown in >, the incident angle of the ion shower 107 is set to 4.
5'' for 3 minutes. At this point, the dog ear 109 was etched and disappeared. Next, as shown in FIG. 1(g), the ion shower 10
Sputter etching was performed for 3 minutes with the incident angle of No. 7 set at 0°. At this point, the edge removal residue 110 was etched and disappeared. Through the above etching process, the wiring width is 0.5μ, which has a cross-sectional shape without a taper, and the pitch between each wiring is 0.8μ.
m laminated interconnections 108 were formed. The laminated structure is not limited to titanium nitride/copper/titanium nitride, but instead of titanium nitride, chromium (Cr), niobium (Nb), tantalum (Ta), or their nitrides, borides, or dioxides can be used. Silicon (SIO),
Silicon nitride (S13N4) may also be used. Further, the material is not limited to copper, and may be an alloy containing copper as a main component. Furthermore, the present invention can be implemented with various modifications without departing from the spirit thereof. [Effects of the Invention] According to the present invention, when forming, by sputter etching, a laminated wiring structure made of a wiring material such as copper, which is difficult to perform reactive ion etching, and which is made of materials with different sputtering yields,
A fine wiring pattern having a non-tapered shape without dog car or skirting residue can be formed. Therefore, highly reliable fine wiring with high allowable current density and low signal delay can be realized.
第１図は本発明の・瞼ヘン黄施的に係る、半導体装置の
製造方法を示す断面図、第２図は従来例を示す断面図で
ある。
１０１・・・、基板、１０２・・・層間絶縁膜、１０３
．１０５・・・窒化チタン、１０４・・・銅、１０６・
・・レジストパターン、FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a sectional view showing a conventional example. 101..., substrate, 102... interlayer insulating film, 103
．． 105...Titanium nitride, 104...Copper, 106...
・Resist pattern,
Claims (5)
異なる材料からなる積層構造膜からスパッタエッチング
法によって配線パターニングする工程において、スパッ
タ収率の小さい材料からなる層を主面法線となす第１の
イオン入射角度でエッチングする工程と、スパッタ収率
の大きい材料からなる層を前記第１のイオン入射角度よ
り小さい主面法線となす第２のイオン入射角度でエッチ
ングする工程と、積層膜全厚のエッチングの後に前記第
１のイオン入射角度と等しいのかまたは大きい主面法線
となす第３のイオン入射角度でエッチングする工程と、
次いで前記第２のイオン入射角度と等しいかまたは小さ
い主面法線となす第４のイオン入射角度でエッチングす
る工程とを含むこ事を特徴とする半導体装置の製造方法
。(1) In the process of wiring patterning by sputter etching from a layered structure film made of materials with different sputtering yields formed on the main surface of a semiconductor substrate, a layer made of a material with a low sputtering yield is aligned with the normal to the main surface. a step of etching a layer made of a material with a high sputtering yield at a second ion incidence angle that is normal to the main surface and is smaller than the first ion incidence angle; After etching the entire thickness of the laminated film, etching at a third ion incidence angle that is equal to or greater than the first ion incidence angle and is normal to the main surface;
and then etching at a fourth ion incidence angle that is equal to or smaller than the second ion incidence angle and is equal to or smaller than the principal surface normal.
入射角度は０°〜３０°、第３の入射角度は３０°〜５
５°、第４のイオン入射角度は０°〜３０°である事を
特徴とする請求項１記載の半導体装置の製造方法。(2) The first incidence angle is 30° to 55°, the second ion incidence angle is 0° to 30°, and the third ion incidence angle is 30° to 55°.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth ion incidence angle is 0 to 30 degrees.
主成分とする合金である事を特徴とする請求項１ないし
２記載の半導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the material having a high sputtering yield is copper or an alloy containing copper as a main component.
Ｎｂ、Ｔａ、Ｖ、Ｗ、Ｍｃあるいはそれらの合金、窒化
物、ホウ化物から選ばれる事を特徴とする請求項１ない
し３記載の半導体装置の製造方法。(4) The materials with low sputtering yield include Ti, Cr,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the material is selected from Nb, Ta, V, W, Mc, or alloys thereof, nitrides, and borides.
る請求項３ないし４記載の半導体装置の製造方法。(5) The method of manufacturing a semiconductor device according to claim 3 or 4, wherein the layered structure film is a single layer alloy film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24233088A JPH0291940A (en) | 1988-09-29 | 1988-09-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24233088A JPH0291940A (en) | 1988-09-29 | 1988-09-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0291940A true JPH0291940A (en) | 1990-03-30 |
Family
ID=17087590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24233088A Pending JPH0291940A (en) | 1988-09-29 | 1988-09-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0291940A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0480383A (en) * | 1990-07-24 | 1992-03-13 | Sony Corp | Method for patterning coppery material |
| JPH0689883A (en) * | 1992-09-08 | 1994-03-29 | Sony Corp | Method of forming connecting hole |
| JPH06112213A (en) * | 1992-08-31 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | Method for etching treatment |
| WO1999003143A1 (en) * | 1997-07-09 | 1999-01-21 | Applied Materials, Inc. | Patterned copper etch for micron and submicron features, using enhanced physical bombardment |
| US6331380B1 (en) | 1997-12-12 | 2001-12-18 | Applied Materials, Inc. | Method of pattern etching a low K dielectric layer |
| JP2005157118A (en) * | 2003-11-27 | 2005-06-16 | Shimadzu Corp | Blazed holographic grating and manufacturing method therefor, and replica grating |
| WO2015097942A1 (en) * | 2013-12-25 | 2015-07-02 | キヤノンアネルバ株式会社 | Substrate processing method and method for producing semiconductor device |
| KR20170002562A (en) * | 2014-05-09 | 2017-01-06 | 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. | Apparatus and method for dynamic control of ion beam energy and angle |
-
1988
- 1988-09-29 JP JP24233088A patent/JPH0291940A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0480383A (en) * | 1990-07-24 | 1992-03-13 | Sony Corp | Method for patterning coppery material |
| JPH06112213A (en) * | 1992-08-31 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | Method for etching treatment |
| JPH0689883A (en) * | 1992-09-08 | 1994-03-29 | Sony Corp | Method of forming connecting hole |
| US6488862B1 (en) | 1997-07-09 | 2002-12-03 | Applied Materials Inc. | Etched patterned copper features free from etch process residue |
| US6010603A (en) * | 1997-07-09 | 2000-01-04 | Applied Materials, Inc. | Patterned copper etch for micron and submicron features, using enhanced physical bombardment |
| JP2002508117A (en) * | 1997-07-09 | 2002-03-12 | アプライド マテリアルズ インコーポレイテッド | Copper pattern etching for micron and sub-micron features using enhanced physical impact |
| WO1999003143A1 (en) * | 1997-07-09 | 1999-01-21 | Applied Materials, Inc. | Patterned copper etch for micron and submicron features, using enhanced physical bombardment |
| US6331380B1 (en) | 1997-12-12 | 2001-12-18 | Applied Materials, Inc. | Method of pattern etching a low K dielectric layer |
| US6458516B1 (en) | 1997-12-12 | 2002-10-01 | Applied Materials Inc. | Method of etching dielectric layers using a removable hardmask |
| JP2005157118A (en) * | 2003-11-27 | 2005-06-16 | Shimadzu Corp | Blazed holographic grating and manufacturing method therefor, and replica grating |
| WO2015097942A1 (en) * | 2013-12-25 | 2015-07-02 | キヤノンアネルバ株式会社 | Substrate processing method and method for producing semiconductor device |
| CN105849870A (en) * | 2013-12-25 | 2016-08-10 | 佳能安内华股份有限公司 | Substrate processing method and method for producing semiconductor device |
| JP6028110B2 (en) * | 2013-12-25 | 2016-11-16 | キヤノンアネルバ株式会社 | Substrate processing method and semiconductor device manufacturing method |
| TWI562304B (en) * | 2013-12-25 | 2016-12-11 | Canon Anelva Corp | |
| US9564360B2 (en) | 2013-12-25 | 2017-02-07 | Canon Anelva Corporation | Substrate processing method and method of manufacturing semiconductor device |
| KR20170002562A (en) * | 2014-05-09 | 2017-01-06 | 베리안 세미콘덕터 이큅먼트 어소시에이츠, 인크. | Apparatus and method for dynamic control of ion beam energy and angle |
| JP2017520909A (en) * | 2014-05-09 | 2017-07-27 | ヴァリアン セミコンダクター イクイップメント アソシエイツ インコーポレイテッド | Method for etching substrate, method for etching device structure and processing apparatus |
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