JPH0265140A - Method of forming electrode for semiconductor device - Google Patents
Method of forming electrode for semiconductor deviceInfo
- Publication number
- JPH0265140A JPH0265140A JP21573888A JP21573888A JPH0265140A JP H0265140 A JPH0265140 A JP H0265140A JP 21573888 A JP21573888 A JP 21573888A JP 21573888 A JP21573888 A JP 21573888A JP H0265140 A JPH0265140 A JP H0265140A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- resist
- film
- films
- openings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 238000010894 electron beam technology Methods 0.000 abstract description 12
- 230000018109 developmental process Effects 0.000 description 8
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 4
- 239000004926 polymethyl methacrylate Substances 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 241000286209 Phasianidae Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
ショットキ障壁型電界効果トランジスタ（以下ＭＥＳＦ
ＥＴと略記する）は、通常第２図に示すように半絶縁性
半導体基板１０１上に高純度のバッファ層１０２、及び
ｎ形の活性／１１０３がＩ／＆されこのｎ形活性ｐ！Ｊ
１０３上にオーム性接触のソース電極１０４ｓ、ドレイ
ン電極１０４Ｄ、及びショットキ接合から成るゲート電
極１０４Ｇで構成されている。ＭＥＳＦＥＴの高周波特
性を向上させるためにはゲート電極１０４Ｇの接合容量
、直列抵抗を共に小さくすることが必要であり、近年こ
の要求を満たすゲート電極構造として第３図に示される
丁字形の断面形状をもったＭＥＳＦ［ＥＴの開発が進め
られている。従来、丁字形の断面形状を有するゲート電
極を形成する方法として第４図（ａ）に示すように、ｎ
形活性層１０３上に順次低感度の第１のレジスト膜１０
５を例えば３０００人、高感度の第２のレジスト膜１０
６を例えば１μｍ厚さに積層し、例えば電子ビーム１０
０をレジスト膜に照射する。続いて第２のレジスト膜１
０６、及び第１のレジスト膜１０５を順次現像すると両
レジスト膜の感度差に応じて第４図（ｂ）に示される断
面形状をもったレジストパターンが形成される。次に、
第４図（ｃ）に示されるように、例えばＡＱのゲート電
極用金属膜１０７を全面に真空蒸着する。この後通常の
リフトオフ法で前記第２のレジス１−服１０６上の金属
膜１０７及び、第１．第２のレジスト膜１０５、１０６
を除去することにより、第４図（ｄ）に示される断面形
状が丁字形のゲート電極１０４Ｇが形成される。[Detailed description of the invention] [Objective of the invention] (Industrial application field) Schottky barrier field effect transistor (hereinafter referred to as MESF)
(abbreviated as ET) is usually formed by forming a high-purity buffer layer 102 on a semi-insulating semiconductor substrate 101 and an n-type active layer 1103 as shown in FIG. J
A source electrode 104s having an ohmic contact, a drain electrode 104D, and a gate electrode 104G having a Schottky junction are formed on the 103. In order to improve the high frequency characteristics of MESFET, it is necessary to reduce both the junction capacitance and series resistance of the gate electrode 104G, and in recent years, the T-shaped cross-sectional shape shown in FIG. 3 has been developed as a gate electrode structure that satisfies this requirement. Development of Motita MESF [ET is progressing. Conventionally, as a method for forming a gate electrode having a T-shaped cross section, as shown in FIG.
A first resist film 10 of low sensitivity is sequentially formed on the active layer 103.
5 for example, 3000 people, and the highly sensitive second resist film 10
6 to a thickness of, for example, 1 μm, and e.g.
0 onto the resist film. Next, the second resist film 1
06 and the first resist film 105 are sequentially developed, a resist pattern having a cross-sectional shape shown in FIG. 4(b) is formed according to the sensitivity difference between the two resist films. next,
As shown in FIG. 4(c), a gate electrode metal film 107 of, for example, AQ is vacuum-deposited over the entire surface. Thereafter, a normal lift-off method is used to remove the metal film 107 on the second resist layer 106 and the first resist layer 106. Second resist film 105, 106
By removing , a gate electrode 104G having a T-shaped cross section as shown in FIG. 4(d) is formed.
（発明が解決しようとする課題）
取上の従来の形成方法では、第１のレジスト膜＋０５と
第２のレジスト膜１０６との組合せが非常に難しい。例
えば組成の異なるレジストを組合せた場合、第１のレジ
スト膜１０５と第２のレジスト膜１０６との境界に両レ
ジスト膜の反応層が形成されることが多い。一般にこの
ような反応層は現像液による除去が難しい。従って、第
１のレジスト膜１０５の開孔寸法の再現性、安定性が低
下する。また、反応層が形成されないレジストの組合せ
で電子ビーム露光法を用いても第２のレジスト膜１０６
が厚いため、レジスト膜に入射した電子ビームがレジス
ト膜で散乱されて第１のレジス１−膜１０５の開孔を再
現性良く微細化することは極めて困難である。(Problems to be Solved by the Invention) In the conventional forming method described above, it is very difficult to combine the first resist film +05 and the second resist film 106. For example, when resists having different compositions are combined, a reaction layer of both resist films is often formed at the boundary between the first resist film 105 and the second resist film 106. Generally, such a reaction layer is difficult to remove with a developer. Therefore, the reproducibility and stability of the opening dimensions of the first resist film 105 are reduced. Furthermore, even if the electron beam exposure method is used with a combination of resists in which no reaction layer is formed, the second resist film 106
Since the resist film is thick, the electron beam incident on the resist film is scattered by the resist film, making it extremely difficult to miniaturize the openings in the first resist film 105 with good reproducibility.
本発明は上記従来の問題点に鑑みてなされたもので、微
細化に適した断面丁字形の形状を有する半導体装置用電
極の形成方法を提供することを目的とする。The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a method for forming an electrode for a semiconductor device having a T-shaped cross section suitable for miniaturization.
（課題を解決するための手段）
この発明にかかる半導体装置用電極の形成方法は、半導
体基板上に第１のレジスト膜を設けこれに露光処理およ
び現像処理を施して所定の開孔を有するパターンに形成
する工程と、前記第１のレジスト膜とその開孔の側面に
この第１のレジスト膜と組成の異なる第２のレジスト膜
を積層して被着し両レジスト膜の接触界面に両レジスト
膜の反応層を形成する工程と、前記第２のレジスト膜に
露光処理および現像処理を施し前記第１のレジスト膜の
開孔を含む開孔を設けてこの第１のレジスト膜の開孔よ
り両レジスト膜の反応層によって狭められた開孔を有す
るレジストパターンを形成する工程と、全面に金属膜を
被着した後、前記第２のレジスト膜に被着した金属膜、
前記第１．第２のレジスト膜、および前記両しジス１〜
膜の反応層を除去する工程とを具備し、半導体基板上に
断面丁字形の電極を形成するものである。(Means for Solving the Problems) A method for forming an electrode for a semiconductor device according to the present invention includes forming a first resist film on a semiconductor substrate, subjecting it to exposure treatment and development treatment, and forming a pattern having predetermined openings. a second resist film having a different composition from the first resist film is laminated and deposited on the first resist film and the side surface of the opening; a step of forming a reaction layer of the film, and performing an exposure treatment and a development treatment on the second resist film to provide an aperture including the aperture of the first resist film; forming a resist pattern having openings narrowed by reaction layers of both resist films; and after depositing a metal film on the entire surface, a metal film deposited on the second resist film;
Said 1st. a second resist film, and the resist films 1 to 1;
The method includes a step of removing a reaction layer of a film, and forms an electrode having a T-shaped cross section on a semiconductor substrate.
（作 用）
この発明は第１のレジスト膜の開孔よりも小さい開孔が
最終のレジストパターンに得られるので、第１のレジス
ト膜に開孔を設けるために照射する電子ビーム径の絞り
裕度が広く、従って再現性良く微細構造の半導体装置用
電極を形成できる。(Function) In this invention, since apertures smaller than the apertures in the first resist film are obtained in the final resist pattern, the diameter of the electron beam irradiated to form the apertures in the first resist film has a narrowing margin. Therefore, it is possible to form electrodes for semiconductor devices with a fine structure with good reproducibility.
（実施例） 以下、本発明の一実施例を図面を参照して説明する。(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
まず、第１図（ａ）に示すように、半導体基板１０１上
に高純度のバッファ層１０２ 、およびｎ形の活性７５
１０３が積層され、このｎ形活性層１０３上に第１のレ
ジスｌ〜膜１１として例えばポジタイプの電子線レジス
トＰＭＭＡ （ポリメチルメタアクリレ−１〜）を３０
００人厚さに形成し、更にこの第１のレジスト膜１１に
矢印で示す方向から所定のパターンに従って電子ビーム
１０を照射する。First, as shown in FIG. 1(a), a high-purity buffer layer 102 and an n-type active layer 75 are formed on a semiconductor substrate 101.
103 is laminated, and on this n-type active layer 103, for example, a positive type electron beam resist PMMA (polymethyl methacrylate 1-1) is deposited as a first resist 1-film 11.
The first resist film 11 is formed to have a thickness of 0.00 mm, and the first resist film 11 is irradiated with an electron beam 10 in a predetermined pattern from the direction indicated by the arrow.
次に第１図（ｂ）に示すように、第１のレジスト膜１１
を例えばＭＩＢＫ （メチルイソブチルケトン）とＩＰ
Ａ （イソプロピルアルコール）を容積比 １：２に混
合してなる現像液を用いて現像し、例えば０．５μｍの
開孔１４を形成する。電子ビーム露光法を用いた場合、
開孔寸法０．５μｍ程度のパターンは、比較的大ビーム
電流で形成できるため、描画に要する時間は短時間で済
む。Next, as shown in FIG. 1(b), a first resist film 11 is formed.
For example, MIBK (methyl isobutyl ketone) and IP
Development is performed using a developer prepared by mixing A (isopropyl alcohol) at a volume ratio of 1:2 to form openings 14 of, for example, 0.5 μm. When using electron beam exposure method,
Since a pattern with an opening size of about 0.5 μm can be formed with a relatively large beam current, the time required for drawing can be shortened.
次に第２のレジスト膜１２の例えばポジタイプのフォト
レジストＡＺ１３５０ （商品名、シブレイ社製）を０
．７μｍ厚さに塗布し、例えば９０℃１０分間の熱処理
を加え第１のレジスト膜１１と第２のレジスト膜１２と
の境界に、第１図（ｃ）に示すような第２のしシスト膜
１２の現像処理で除去されない両レジスト膜の反応層１
３を形成する。ここで第２のレジスト膜１２を塗布した
後の熱処理は、両レジスト膜の反応層１３を安定に形成
することと、第２のレジスト膜１２のプリベーキングを
兼ねている。Next, the second resist film 12, for example, a positive type photoresist AZ1350 (trade name, manufactured by Sibley), is
．． It is coated to a thickness of 7 μm, and heat-treated at 90° C. for 10 minutes to form a second cyst film as shown in FIG. 1(c) at the boundary between the first resist film 11 and the second resist film 12. Reaction layer 1 of both resist films that is not removed by the development process in step 12
form 3. Here, the heat treatment after applying the second resist film 12 serves both to stably form the reaction layer 13 of both resist films and to pre-baking the second resist film 12.
次に第１図（ｄ）に示すように、第１のレジスト膜１１
の開孔を含む第２のレジスト膜１２上に例えば電子ビー
ム露光法を用い、例えば１μｍの開孔２４を形成する。Next, as shown in FIG. 1(d), a first resist film 11 is formed.
For example, an opening 24 of 1 μm is formed on the second resist film 12 including the opening using, for example, an electron beam exposure method.
これによって半導体基板１０１上に丁字形の断面形状を
有するレジスト膜の貫通孔が形成される。As a result, a through hole in the resist film having a T-shaped cross section is formed on the semiconductor substrate 101.
上記において、未反応の第２のレジスト膜１２を現像で
除去した後の半導体基板１０１上のレジスト膜の厚さは
、現像で除去されない反応層１３の存在により、当初の
第１のレジスト膜１１の厚さよりも０．１μｍ厚くなり
、同時に開孔部の周辺が０．１μｍずつ狭くなることが
わかる。従って第１のレジスト膜の開孔１４寸法を上記
実施例のように０．５μｍに設定した場合、第２のレジ
スト膜１２を現像した後の開孔寸法は０．３μｍとなる
。In the above, the thickness of the resist film on the semiconductor substrate 101 after the unreacted second resist film 12 is removed by development is the same as that of the original first resist film 12 due to the presence of the reaction layer 13 that is not removed by development. It can be seen that the thickness becomes 0.1 μm thicker than that of the hole, and at the same time, the periphery of the opening becomes narrower by 0.1 μm. Therefore, if the size of the opening 14 in the first resist film is set to 0.5 μm as in the above embodiment, the size of the opening after developing the second resist film 12 will be 0.3 μm.
次に第１図（ｅ）に示すように、全面に金属膜１５を被
着する。更に、第１のレジスト膜１１．第２のレジスト
膜１２２両レジスト膜の反応層１３、および第２のレジ
スト膜１２上の金属膜部を除去することによって、第１
図（ｆ）に示されるような断面形状が丁字形の電極パタ
ーン１５ａが半導体基板１０１上に形成される。Next, as shown in FIG. 1(e), a metal film 15 is deposited on the entire surface. Furthermore, the first resist film 11. By removing the reaction layer 13 of both the second resist film 122 and the metal film portion on the second resist film 12, the first resist film 122 is removed.
An electrode pattern 15a having a T-shaped cross section as shown in FIG. 1F is formed on the semiconductor substrate 101.
なお上記実施例ではＰＭＭＡとしてＡＺ１３５０の組合
せについて説明したが、第２のレジスト膜１２を現像除
去した後の開孔寸法が若干異なるもののＰＭＩＰＫにＡ
Ｚ１３５０Ｊ、また、ＰＭＭＡにＨＰＲ−１１８２（商
品名、ＧＡＦ社製）等のレジストの組合せであってもよ
い。また、第１のレジスト膜１１．第２のレジスト膜１
２のパターン形成に用いる露光手段は、電子ビーム露光
のみならず、光露光、イオンビーム露光、Ｘ線露光ある
いはこれらの組合せであってもよい。更に、半導体基板
１０１上に５ｉｎ２あるいはｉ等の膜が形成されている
場合も適用可能である。In the above example, a combination of AZ1350 as PMMA was explained, but a combination of AZ1350 and PMIPK was described, although the opening size after developing and removing the second resist film 12 was slightly different.
Z1350J, or a combination of PMMA and a resist such as HPR-1182 (trade name, manufactured by GAF) may be used. Moreover, the first resist film 11. Second resist film 1
The exposure means used for pattern formation in step 2 may be not only electron beam exposure but also light exposure, ion beam exposure, X-ray exposure, or a combination thereof. Furthermore, the present invention can also be applied to a case where a 5in2 or i film is formed on the semiconductor substrate 101.
以上述べたように本発明によれば、第１のレジスト膜の
開孔を、最終的に必要な開孔寸法よりも広く設定するの
で、照射する電子ビーム径に対して十分な余裕度を以て
形成出来る。このため半導体基板と接しているレジスト
膜の開孔を容易にしかも再現性良く０．３μｍあるいは
それ以下の微細寸法に形成出来る。また、第１のレジス
ト膜１１と第２のレジスト膜１２の露光、現像処理は個
別に行なうため、第１のレジスト膜１１の開孔との第２
のレジスト膜１２の開孔との重ね合せは任意に設定可能
である。更に個々のレジストの開孔寸法も（第１のレジ
スト膜の開孔）−（反応層厚）×２〈第２のレジスト膜
の開孔
の条件を満たす範囲で任意に設定することが出来る。As described above, according to the present invention, the openings in the first resist film are set wider than the final required opening dimensions, so that the openings in the first resist film are formed with sufficient margin for the diameter of the electron beam to be irradiated. I can do it. Therefore, openings in the resist film in contact with the semiconductor substrate can be formed easily and with good reproducibility to minute dimensions of 0.3 μm or less. In addition, since the exposure and development of the first resist film 11 and the second resist film 12 are performed separately, the openings of the first resist film 11 and the second
The overlap with the openings of the resist film 12 can be set arbitrarily. Furthermore, the size of the openings in each resist can be arbitrarily set within the range that satisfies the condition of (openings in the first resist film) - (thickness of the reaction layer) x 2 (openings in the second resist film).
第１図（ａ）〜（ｄ）は本発明の電極形成方法を工程順
に示すいずれも断面図、第２図は従来のＭＥＳＦＥＴを
説明するための断面図、第３図は丁字形の断面形状を有
するＭＥＳＦＥＴの構造を示す断面図、第４図（ａ）〜
（ｄ）は従来の電極形成方法を工程順に示すいずれも断
面図である。
１０−−−−−−−−−−一電子ビーム１１−−−−−
−−−−−一第１のレジスト膜１２−−−−−−−−・
−第２のレジスト膜１３−−−−−−−−−−一反応層
１４、２４ 開孔
１５−−一−−−−−−−−金属膜
１５ａ−−−−−−−−−一電極パターン１０１−−−
−−−−−−−一半導体基板代理人 弁理士 大 胡
典 夫
（ｃＬン
１Ｏ：霊Ｊニ゛−ム
１１ ： コヘ １Φ を貞ヒへ１１
Ａ−：Ｆｅ’！１シ
第
図
（蓋Φυ
第
図
第
図
第
図
（ｄ−）
ｅｌ
ｔ！Ｓ：金属１’ｌ￥
１！５ａ： ＊ｊｐｋパターン
第
図
（ンΦ２）
７０７ ；
ケート電刺底ロ颯ル更
１０＋Ｃｖ ：
ケ゛−１−１１＆
第
図
（雉のＺ）Figures 1 (a) to (d) are cross-sectional views showing the electrode forming method of the present invention in the order of steps, Figure 2 is a cross-sectional view for explaining a conventional MESFET, and Figure 3 is a T-shaped cross-sectional shape. A cross-sectional view showing the structure of a MESFET having
(d) are cross-sectional views showing the conventional electrode forming method in the order of steps. 10---------One electron beam 11------
-------First resist film 12-----
-Second resist film 13--Reaction layer 14, 24 Opening 15--1--Metal film 15a-- Electrode pattern 101 ---
−−−−−−−1 Semiconductor substrate agent Patent attorney Ogo
Norifu (cLn 1O: Rei Jnim 11: Kohe 1Φ to Teihi 11 A-: Fe'! 1shi fig. (lid Φυ fig. Metal 1'l￥ 1!5a: *jpk pattern diagram (Φ2) 707; Kate electric needle bottom roll further 10+Cv: Key-1-11 & diagram (pheasant Z)
Claims (1)
および現像処理を施して所定の開孔を有するパターンに
形成する工程と、前記第１のレジスト膜とその開孔の側
面にこの第１のレジスト膜と組成の異なる第２のレジス
ト膜を積層して被着し両レジスト膜の接触界面に両レジ
スト膜の反応層を形成する工程と、前記第２のレジスト
膜に露光処理および現像処理を施し前記第１のレジスト
膜の開孔を含む開孔を設けてこの第１のレジスト膜の開
孔より両レジスト膜の反応層によって狭められた開孔を
有するレジストパターンを形成する工程と、全面に金属
膜を被着した後、前記第２のレジスト膜に被着した金属
膜、前記第１、第２のレジスト膜、および前記両レジス
ト膜の反応層を除去する工程とを具備し、半導体基板上
に断面Ｔ字形の電極を形成する半導体装置用電極の形成
方法。a step of providing a first resist film on a semiconductor substrate and subjecting it to exposure and development to form a pattern having predetermined openings; A step of laminating and depositing a resist film and a second resist film having a different composition and forming a reaction layer of both resist films at the contact interface of both resist films, and exposing and developing the second resist film. forming a resist pattern having openings including the openings in the first resist film and narrowing the openings from the openings in the first resist film by the reaction layers of both resist films; After depositing a metal film on the entire surface, removing the metal film deposited on the second resist film, the first and second resist films, and the reaction layers of both the resist films, A method for forming an electrode for a semiconductor device, which comprises forming an electrode having a T-shaped cross section on a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21573888A JP2664736B2 (en) | 1988-08-30 | 1988-08-30 | Method for forming electrode for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21573888A JP2664736B2 (en) | 1988-08-30 | 1988-08-30 | Method for forming electrode for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0265140A true JPH0265140A (en) | 1990-03-05 |
| JP2664736B2 JP2664736B2 (en) | 1997-10-22 |
Family
ID=16677379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21573888A Expired - Fee Related JP2664736B2 (en) | 1988-08-30 | 1988-08-30 | Method for forming electrode for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2664736B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291303A (en) * | 1992-04-08 | 1993-11-05 | Oki Electric Ind Co Ltd | Formation of negative resist pattern |
| US5418186A (en) * | 1993-07-15 | 1995-05-23 | Samsung Electronics Co., Ltd. | Method for manufacturing a bump on a semiconductor chip |
| US5658826A (en) * | 1995-08-22 | 1997-08-19 | Lg Semicon Co., Ltd. | Method for fabricating semiconductor device |
| CN115985846A (en) * | 2023-02-10 | 2023-04-18 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
-
1988
- 1988-08-30 JP JP21573888A patent/JP2664736B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291303A (en) * | 1992-04-08 | 1993-11-05 | Oki Electric Ind Co Ltd | Formation of negative resist pattern |
| US5418186A (en) * | 1993-07-15 | 1995-05-23 | Samsung Electronics Co., Ltd. | Method for manufacturing a bump on a semiconductor chip |
| US5658826A (en) * | 1995-08-22 | 1997-08-19 | Lg Semicon Co., Ltd. | Method for fabricating semiconductor device |
| CN115985846A (en) * | 2023-02-10 | 2023-04-18 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2664736B2 (en) | 1997-10-22 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |