JPH0262036A - Semiconductor device manufacturing apparatus - Google Patents
Semiconductor device manufacturing apparatusInfo
- Publication number
- JPH0262036A JPH0262036A JP21256588A JP21256588A JPH0262036A JP H0262036 A JPH0262036 A JP H0262036A JP 21256588 A JP21256588 A JP 21256588A JP 21256588 A JP21256588 A JP 21256588A JP H0262036 A JPH0262036 A JP H0262036A
- Authority
- JP
- Japan
- Prior art keywords
- growth
- reaction chamber
- semiconductor substrate
- wavelength
- heating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 239000007789 gas Substances 0.000 claims abstract description 9
- 239000012495 reaction gas Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 description 25
- 238000010586 diagram Methods 0.000 description 17
- 230000005855 radiation Effects 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000498 cooling water Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 230000003595 spectral effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体基板を加熱する機構を有する半導体デバイス製造
装置の改良に関し、
表面反応律速や初期反応の初期核形成過程が温度に依存
するような化学気相成長（ｃｈｅｍｉｃａｌ ｖａｐ
ｏｒ ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ）を行う際、下
地の如何、即ち、例えばｎ型不純物導入領域であるかｐ
型不純物導入領域であるかに拘わらず、その表面温度が
路間−となるようにし、成長させた被膜の膜厚を均一化
することを目的とし、
サセプタと反応ガス導入管とガス排出管とを有し且つ該
サセプタ上には半導体基板が配設される反応室と、該反
応室に対向して配置されて半導体基板を加熱する赤外線
発生源と、前記反応室と該赤外線発生源との間に配設さ
れ且つ該赤外線発生源が発生する赤外線のうち前記半導
体基板の何れの箇所に於いても均一に吸収される波長の
光を透過するフィルタとを備えてなるよう構成する。[Detailed Description of the Invention] [Summary] Regarding the improvement of a semiconductor device manufacturing apparatus having a mechanism for heating a semiconductor substrate, the present invention relates to the improvement of a semiconductor device manufacturing apparatus having a mechanism for heating a semiconductor substrate. vap
When performing CVD, it is important to check the type of underlayer, for example, whether it is an n-type impurity doped region or not.
Regardless of whether it is a type impurity introduction region, the surface temperature is maintained at the same level as that between the susceptor, the reaction gas introduction pipe, and the gas discharge pipe, with the aim of making the film thickness of the grown film uniform. a reaction chamber in which a semiconductor substrate is disposed on the susceptor; an infrared generation source disposed opposite to the reaction chamber to heat the semiconductor substrate; A filter is disposed between the semiconductor substrate and transmits light having a wavelength that is uniformly absorbed in any part of the semiconductor substrate among the infrared rays generated by the infrared radiation source.
本発明は、半導体基板を加熱する機構を有する半導体デ
バイス製造装置の改良に関する。The present invention relates to an improvement in a semiconductor device manufacturing apparatus having a mechanism for heating a semiconductor substrate.
半導体デバイスの大規模化に伴い、例えばＭＩＳ （ｍ
ｅｔａｌ １ｎｓｕｌａｔｏｒ ｓｅｍｉｃｏｎｄ
ｕｃｔｏｒ）電界効果トランジスタのソース領域及びド
レイン領域に於ける電極コンタクト・ホールにコンタク
ト用金属を埋め込む技術が重要になってきた。With the increase in the scale of semiconductor devices, for example, MIS (m
etal 1nsulator semicond
2. Description of the Related Art Techniques for embedding contact metal into electrode contact holes in the source and drain regions of field effect transistors have become important.
現在、深い電極コンタクト・ホール内に例えばタングス
テン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、
チタン（Ｔｉ）、白金（Ｐｔ）、金（Ａｕ）、銀（Ａｇ
）などの金属或いは当該金属のシリサイドを選択的に成
長させて埋めたり、また、その後、成長条件を変えて前
記電極コンタクト・ホール周辺の絶縁膜上にも延在する
当該金属からなる配線材料膜を一体的に形成する技術が
提供されている。Currently, deep electrode contact holes contain materials such as tungsten (W), molybdenum (Mo), tantalum (Ta), etc.
Titanium (Ti), platinum (Pt), gold (Au), silver (Ag
) or silicide of the metal is selectively grown and buried, or by changing the growth conditions thereafter, a wiring material film made of the metal extends over the insulating film around the electrode contact hole. A technology has been provided to integrally form the
前記のような選択的成長を実施する場合、下地である不
純物拡散頭載の如何、例えばｎ＋型であるかｐ４″型で
あるか、また、その他の条件が相違しても、例えば膜厚
が常に同じになるなど、同一の成長を実現できることが
望ましい。When carrying out selective growth as described above, even if the underlying impurity diffusion type, for example, n+ type or p4'' type, and other conditions are different, for example, the film thickness is different. It is desirable to be able to achieve the same growth, such as always being the same.
従来、金属或いは該金属のシリサイドを選択的に成長さ
せる場合、その選択性を維持する為、赤外（ｉｎｆｒａ
ｒｅｄ： ＩＲ）線を照射して半導体基板を加熱するこ
とができる反応装置を用いている（選択性などの現象に
関して、必要あれば、ｒＨ，Ｉｔｏｈ、Ｔ、Ｍｏｒｉｙ
ａ、Ｍ、Ｋａｓｈｉｗａｇｉ、５ｏｌｉｅｄ ５ｔａ
ｔｅ Ｔｅｃｈｎｏｌ、、ｖｏｌ、３０，８３．Ｎｏ
ｖ、１９８７」、ｒＴ、０ｈｂａ、Ｓ、Ｉｎｏｕｅ、Ｍ
。Conventionally, when selectively growing a metal or a silicide of the metal, infrared (infrared) was used to maintain the selectivity.
A reactor is used that can heat the semiconductor substrate by irradiating red: IR (IR) radiation (for phenomena such as selectivity, if necessary, rH, Itoh, T, Moriy
a, M, Kashiwagi, 5olied 5ta
te Technol,, vol, 30, 83. No
v, 1987”, rT., Ohba, S., Inoue, M.
.
Ｍａｅｄａ、Ｐｒｏｃ、ＩＥＥＥ ＩＥＤＭ Ｔｅ
ｃｈ、Ｄｉｇ、、２１３ １９８７Ｊ、「Ｉ］。Maeda, Proc, IEEE IEDM Te
ch, Dig,, 213 1987J, “I].
Ｋｏｔａｎｉ、Ｔ、Ｔｓｕｔｓｕｍｉ、Ｊ、Ｋ。Kotani, T., Tsutsumi, J.K.
ｍｏｒｉ、Ｓ、Ｎａｇａｏ、１ｂｉｄ、２１７１９８７
Ｊなどを参照）。mori, S, Nagao, 1bid, 2171987
(see J. et al.).
現在、半導体装置に於けるｎ型不純物導入領域を形成す
るにはｐ （Ｐ）或いは砒素（Ａｓ）が、そして、ｐ型
不純物導入領域を形成するには硼素（Ｂ）がそれぞれ多
用され、そして、フリー・キャリヤの濃度が異なると光
の吸収が相違し、特に、その現象は波長が１ 〔μｍ〕
〜２（μｍ）の光について顕著に現れ、半導体基板の表
面温度に差が発生することになる。尚、シリコン（Ｓｉ
）に於いては、主たる吸収は波長が１ 〔μｍ〕以下の
光に対して起きる。Currently, p (P) or arsenic (As) is often used to form n-type impurity doped regions in semiconductor devices, and boron (B) is often used to form p-type impurity doped regions. , the absorption of light differs when the concentration of free carriers differs, and in particular, this phenomenon occurs at a wavelength of 1 [μm]
This is noticeable for light of ~2 (μm), resulting in a difference in the surface temperature of the semiconductor substrate. In addition, silicon (Si
), the main absorption occurs for light with a wavelength of 1 [μm] or less.
前記従来の技術で採用されているＩＲ線のスペクトルは
１ 〔μｍ〕〜２〔μｍ〕の範囲に入る領域が存在して
いることから、下地の如何に依って表面温度に差を生じ
、従って、同じ成長工程でありながら金属或いは金属シ
リサイドが選択成長開始する時点は同一にならず、成長
膜厚が相違することになる。Since the spectrum of the IR rays used in the above-mentioned conventional technology has a region within the range of 1 [μm] to 2 [μm], there is a difference in surface temperature depending on the type of substrate. Even though the growth process is the same, the time point at which selective growth of metal or metal silicide starts is not the same, and the thickness of the grown film is different.
第８図は成る種の半導体装置の要部切断側面図を表して
いる。FIG. 8 shows a cutaway side view of the essential parts of a certain type of semiconductor device.
図に於いて、２１はｐ−型シリコン半導体基板、２２は
ｎ−型ウェル、２３は例えば二酸化シリコン（ＳｉＯｚ
）からなる絶縁膜、２３Ｎ及び２３Ｐは電極コンタクト
・ホール、２４はｎ＋型不純物導入領域、２５はｐ＋型
不純物導入領域、２６は電極コンタクト・ホール２３Ｎ
内に選択成長させたＷからなる電極、２７は電極コンタ
クト・ホール２３Ｐ内に選択成長させたＷからなる電極
をそれぞれ示している。In the figure, 21 is a p-type silicon semiconductor substrate, 22 is an n-type well, and 23 is, for example, silicon dioxide (SiOz).
), 23N and 23P are electrode contact holes, 24 is an n+ type impurity doped region, 25 is a p+ type impurity doped region, and 26 is an electrode contact hole 23N.
An electrode made of W selectively grown inside the electrode contact hole 23P, and 27 an electrode made of W selectively grown inside the electrode contact hole 23P.
第９図は第８図に見られるように電極２６及び２７を成
長させた場合に於ける成長時間と成長膜厚との関係につ
いて説明する為の線図を表していて、横軸に成長時間を
、縦軸に成長膜厚をそれぞれ採っである。FIG. 9 is a diagram for explaining the relationship between the growth time and the grown film thickness when the electrodes 26 and 27 are grown as shown in FIG. 8, and the horizontal axis represents the growth time. The vertical axis represents the grown film thickness.
図に於いて、２６Ａは第８図に見られるｎ＋型不純物導
入領域２４の表面に選択成長された電極２６に関する成
長時間対成長時間の関係を表すライン、２７Ａは第８図
に見られるｐ＋型不純物導入領域２５の表面に選択成長
された電極２７に関する成長時間対成長時間の関係を表
すラインをそれぞれ示している。In the figure, 26A is a line representing the relationship between growth time and growth time for the electrode 26 selectively grown on the surface of the n+ type impurity doped region 24 shown in FIG. 8, and 27A is the p+ type shown in FIG. Lines representing the relationship between growth time and growth time for the electrode 27 selectively grown on the surface of the impurity-introduced region 25 are shown.
図から判るように、ｐ＋型不純物導入領域２５上に電極
２７が成長開始される時点では、ｎ＋型不純物導入領域
２４上には既に０．３〔μｍ〕程度の電極２６が形成さ
れている。As can be seen from the figure, at the time when the growth of the electrode 27 is started on the p+ type impurity introduced region 25, the electrode 26 having a thickness of about 0.3 [μm] has already been formed on the n+ type impurity introduced region 24.
ところで、このような選択成長に於いては、半導体装置
の諸々の電気的特性を向上乃至維持する為、温度をでき
る限り低くして実施することが望ましい。従って、例え
ばｎ型不純物導入領域上に選択成長させるに適切な表面
温度に設定するとｎ型不純物導入領域上には成長しなか
ったり、また、ｎ型不純物導入領域にたいして適切な表
面温度に設定するとｎ型不純物導入領域では電気的な劣
化、例えば、接合が破壊されてリーク電流が流れ易くな
るなどの問題を生ずる。Incidentally, in such selective growth, in order to improve or maintain various electrical characteristics of the semiconductor device, it is desirable to carry out the process at a temperature as low as possible. Therefore, for example, if the surface temperature is set appropriate for selective growth on the n-type impurity introduced region, no growth will occur on the n-type impurity introduced region, and if the surface temperature is set appropriate for the n-type impurity introduced region, n In the type impurity-introduced region, problems arise such as electrical deterioration, for example, junctions being destroyed and leakage currents becoming more likely to flow.
一般に、半導体装置に於いては、ｎ型不純物導入領域と
ｎ型不純物導入領域は全面に混在することが多いから、
ＩＲ線の出力を不純物領域の導電型に応じて局所的に制
御し、半導体基板の表面温度を一定にすることは実際上
不可能である。Generally, in semiconductor devices, n-type impurity doped regions and n-type impurity doped regions often coexist over the entire surface.
It is practically impossible to locally control the output of the IR line according to the conductivity type of the impurity region and to keep the surface temperature of the semiconductor substrate constant.
本発明は、表面反応律速や初期反応の初期核形成過程が
温度に依存するようなＣＶＤを行う際、下地の如何、即
ち、例えばｎ型不純物導入領域であるかｎ型不純物導入
領域であるかに拘わらず、その表面温度が路間−となる
ようにし、成長させた被膜の膜厚を均一化しようとする
。In the present invention, when carrying out CVD in which the rate-determining surface reaction and the initial nucleation process of the initial reaction depend on temperature, it is important to consider whether the underlying material is an n-type impurity-introduced region or an n-type impurity-introduced region. Regardless of the temperature, the surface temperature is kept at a level between 1 to 3, and the thickness of the grown film is made uniform.
第１図は本発明の原理を解説する為の半導体デバイス製
造装置の要部説明図を表している。FIG. 1 shows an explanatory view of the main parts of a semiconductor device manufacturing apparatus for explaining the principle of the present invention.
図に於いて、１はＩＲ線発生源、２は波長が約１ 〔μ
ｍ〕を越える光を阻止するフィルタ、３は反応室、３Ａ
は反応ガス導入管、３Ｂはガス排出管、４はサセプタ、
５は半導体基板、６は波長が約１ 〔μｍ〕以下のＩＲ
線をそれぞれ示している。In the figure, 1 is the IR radiation source, 2 is the wavelength of approximately 1 [μ
m], 3 is a reaction chamber, 3A is a filter that blocks light exceeding
is a reaction gas introduction pipe, 3B is a gas discharge pipe, 4 is a susceptor,
5 is a semiconductor substrate, 6 is an IR with a wavelength of about 1 [μm] or less
Each line is shown.
図から明らかなように、図示の装置では、ＩＲ線発生源
１からのＩＲ線はフィルタ２を透過して反応室３内に入
り、その中にセットされている半導体基板５を加熱する
ようになっている。As is clear from the figure, in the illustrated apparatus, the IR radiation from the IR radiation source 1 passes through the filter 2 and enters the reaction chamber 3, heating the semiconductor substrate 5 set therein. It has become.
第２図は第１図に見られる装置に於けるＩＲ線発生源１
で発生されたＩＲ線のスペクトル強度分布を表す線図で
あり、縦軸に波長を、また、横軸に強度をそれぞれ採っ
である。Figure 2 shows the IR radiation source 1 in the device shown in Figure 1.
1 is a diagram showing the spectral intensity distribution of IR rays generated by the IR rays, with wavelength plotted on the vertical axis and intensity plotted on the horizontal axis.
図から判るように、ＩＲ線は波長１〔μｍ〕〜２〔μｍ
〕の間にピークをもって分布している。As you can see from the figure, the IR ray has a wavelength of 1 [μm] to 2 [μm].
] is distributed with a peak between.
第３図は第１図に見られる装置に於けるフィルタ２を透
過したＴＲ線のスペクトル強度分布を表す線図であり、
縦軸に波長を、また、横軸に強度をそれぞれ採っである
。FIG. 3 is a diagram showing the spectral intensity distribution of the TR line transmitted through the filter 2 in the apparatus shown in FIG.
The vertical axis represents wavelength, and the horizontal axis represents intensity.
図から判るように、ここでのＩＲ線は波長約１〔μｍ〕
以下になっていて、これが反応室３内に在る半導体基板
５を加熱することになる。As you can see from the figure, the IR ray here has a wavelength of approximately 1 [μm]
This heats the semiconductor substrate 5 in the reaction chamber 3.
前記したようなことから、本発明に依る半導体デバイス
製造装置では、サセプタ（例えばサセプタ４）と反応ガ
ス導入管（例えば反応ガス導入管３Ａ）とガス排出管（
例えばガス排出管３Ｂ）とを有し且つ該サセプタ上には
半導体基板（例えば半導体基板５）が配設される反応室
（例えば反応室３）と、該反応室に対向して配置されて
半導体基板を加熱するＩＲ線発生源（例えば■Ｒ′！ｓ
発生源１）と、前記反応室と該ＩＲ線発生源との間に配
設され且つ該ＩＲｉ発生源が発生するＩＲ線のうち前記
半導体基板の何れの箇所に於いても均一に吸収される波
長の光を透過するフィルタ（例えばフィルタ２）とを備
えている。As described above, the semiconductor device manufacturing apparatus according to the present invention includes a susceptor (for example, susceptor 4), a reaction gas introduction pipe (for example, reaction gas introduction pipe 3A), and a gas discharge pipe (for example, reaction gas introduction pipe 3A).
For example, a reaction chamber (e.g., reaction chamber 3) having a gas exhaust pipe 3B) and a semiconductor substrate (e.g., semiconductor substrate 5) disposed on the susceptor; An IR radiation source that heats the substrate (e.g. ■R'!s
source 1) disposed between the reaction chamber and the IR radiation source, and the IR radiation generated by the IRi generation source is uniformly absorbed at any location on the semiconductor substrate. It is equipped with a filter (for example, filter 2) that transmits light of the same wavelength.
前記手段を採ることに依り、半導体基板は波長が略Ｉ
Ｃａｍ）以下のＩＲ線で加熱されることから、そのＩ
Ｒ′ＩＩＡは、選択成長を行う下地の如何、即ち、ｎ型
不純物導入領域であるかｎ型不純物導入領域であるかに
拘わらず均一に吸収され、その表面温度は路間−となっ
て、何れの箇所の選択成長開始も同時であり、その結果
、選択成長させた被膜の膜厚は均一になる。By adopting the above-mentioned means, the semiconductor substrate has a wavelength of approximately I.
Cam) Since it is heated by the following IR rays, its I
R'IIA is uniformly absorbed regardless of the substrate for selective growth, that is, whether it is an n-type impurity doped region or an n-type impurity doped region, and its surface temperature becomes -, The selective growth starts at all locations at the same time, and as a result, the thickness of the selectively grown film becomes uniform.
第４図は本発明一実施例を解説する為の要部説明図を表
している。FIG. 4 shows an explanatory diagram of main parts for explaining one embodiment of the present invention.
図に於いて、１１はＩＲ，ｖ発生源、１２は波長が約１
〔μｍ〕を越える光を阻止するフィルタ、１３は冷却
水通路、１３Ａは冷却水導入管、１３Ｂは冷却水排出管
、１４は石英板、１５は反応室、１５Ａはガス排出管、
１６はシャワー １７は半導体基板をそれぞれ示してい
る。In the figure, 11 is an IR,v source, 12 is a wavelength of approximately 1
A filter that blocks light exceeding [μm], 13 is a cooling water passage, 13A is a cooling water inlet pipe, 13B is a cooling water discharge pipe, 14 is a quartz plate, 15 is a reaction chamber, 15A is a gas discharge pipe,
16 indicates a shower, and 17 indicates a semiconductor substrate.
図示例に於けるＩＲ線発生源１１はＷハロゲン・ランプ
を光源とするものであり、また、シャワー１６からは、
例えば
ＷＦ ｓ ： ２〜５ （ｃｃ／分〕
Ｓ ｉＨ４： ２〜５ （ｃｃ／分〕
Ｈ２或いはＨｅ ： １００”ｌ ＯＯＯ（ｃｃ／分〕
圧カニ Ｏ，ｌ〜０．３ ［Ｔｏ ｒ ｒ）からなるガ
スを流すようにしている。The IR radiation source 11 in the illustrated example uses a W halogen lamp as a light source, and the shower 16 emits
For example, WF s: 2-5 (cc/min) SiH4: 2-5 (cc/min) H2 or He: 100”l OOO (cc/min)
A gas consisting of a pressure crab O, l to 0.3 Torr is made to flow.
本実施例に依ると、半導体基板１７の表面温度の分布は
殆どなくなり、従って、ＷＳ ｉｘ （ｘ−〇〜０．
１）の成長は何れの箇所に於いても略同時に開始され、
成長膜厚はｎ型不純物導入領域上もｐ型不純物導入領域
上も略均−になった。According to this embodiment, the distribution of the surface temperature of the semiconductor substrate 17 is almost eliminated, so that WS ix (x-〇~0.
Growth of 1) starts at almost the same time in all locations,
The grown film thickness became approximately uniform on both the n-type impurity introduced region and the p-type impurity introduced region.
第５図は第８図に見られるように電極２６及び２７を成
長させた場合に於ける成長時間と成長膜厚との関係につ
いて説明する為の線図を表していて、横軸に成長時間を
、縦軸に成長膜厚をそれぞれ採っである。FIG. 5 is a diagram for explaining the relationship between the growth time and the grown film thickness when the electrodes 26 and 27 are grown as shown in FIG. 8, and the horizontal axis represents the growth time. The vertical axis represents the grown film thickness.
図に於いて、２６Ａは第８図に見られるｎ＋型不純物導
入領域２４の表面に選択成長された電極２６に関する成
長時間対成長時間の関係を表すライン、２７Ａは第８図
に見られるｐ＋型不純物導入領域２５の表面に選択成長
された電極２７に関する成長時間対成長時間の関係を表
すラインをそれぞれ示している。In the figure, 26A is a line representing the relationship between growth time and growth time for the electrode 26 selectively grown on the surface of the n+ type impurity doped region 24 shown in FIG. 8, and 27A is the p+ type shown in FIG. Lines representing the relationship between growth time and growth time for the electrode 27 selectively grown on the surface of the impurity-introduced region 25 are shown.
図から判るように、ライン２６Ａ並びにライン２７Ａは
一致している。従って、電極２６及び電極２７の成長開
始は同時であり、ｎ＋型不純物導入領域２４上であるか
ｐ＋型不純物導入領域２５上であるかには無関係である
。As can be seen, lines 26A and 27A coincide. Therefore, the growth of the electrode 26 and the electrode 27 starts at the same time, regardless of whether they are grown on the n+ type impurity doped region 24 or the p+ type impurity doped region 25.
前記実施例では、ＴＲ線の一部遮断にフィルタ１２を用
いているが、冷却水に硫酸銅を混合して流すとフィルタ
の役割も果し得るので、フィルタ１２を単なる石英板に
代替することが可能になる。In the above embodiment, the filter 12 is used to partially block the TR line, but if copper sulfate is mixed with the cooling water, it can also serve as a filter, so the filter 12 can be replaced with a simple quartz plate. becomes possible.
また、半導体基板１７の加熱を裏面から行っているが、
装置に若干の改変を施せば、第１図に見られるように、
表面から加熱する構成にすることは容易である。然しな
から、選択成長のみを行う場合、ＴＲ線の照射方向によ
って（１）選択性及び（２）膜ストレスなどが相違する
為、図示のように裏面から加熱する方が有効であり、こ
れについては更に詳細に説明しよう。Also, although the semiconductor substrate 17 is heated from the back side,
By making some modifications to the device, as shown in Figure 1,
It is easy to configure the heating from the surface. However, when only selective growth is performed, (1) selectivity and (2) membrane stress etc. differ depending on the irradiation direction of the TR beam, so it is more effective to heat from the back side as shown in the figure. Let me explain in more detail.
第６図は裏面加゛熱と表面加熱との関係を説明する為の
線図であり、横軸にＴＲに依る裏面加熱の場合の成長温
度を、また、縦軸に同じく表面加熱の場合の成長温度を
それぞれ採っである。Figure 6 is a diagram for explaining the relationship between backside heating and frontside heating, where the horizontal axis shows the growth temperature in the case of backside heating by TR, and the vertical axis shows the growth temperature in the case of frontside heating. The growth temperature was taken for each.
図に於いて、ＤＳは成長開始領域、ＳＥＬは選択成長領
域、ＢＬは無選択成長領域をそれぞれ示している。In the figure, DS indicates a growth start region, SEL indicates a selective growth region, and BL indicates a non-selective growth region.
図から判るように、表面加熱は裏面加熱に比較し、成長
開始温度及び選択成長温度ともに高く、且つ、温度の選
択幅も狭い。尚、理論的には、表面加熱と裏面加熱とは
１：１の関係、即ち、図示のラインＩＬに載る筈と思わ
れるが、実際には図示の通りになり、その理由は未だ不
分明である。As can be seen from the figure, both the growth start temperature and the selective growth temperature are higher in the front surface heating than in the back surface heating, and the temperature selection range is also narrower. Theoretically, it seems that the front surface heating and back surface heating should have a 1:1 relationship, that is, be on the line IL shown in the figure, but in reality, it is as shown in the figure, and the reason for this is still unclear. be.
第７図は裏面加熱或いは表面加熱を行った場合の膜スト
レスの関係を説明する為の線図であり、横軸に成長温度
を、縦軸にストレスをそれぞれ採ってあり、ストレスは
Ｏより上が引っ張り応力を、０より下が圧縮応力を表し
ている。Figure 7 is a diagram to explain the relationship between film stress when back side heating or front side heating is performed.The horizontal axis shows the growth temperature, and the vertical axis shows the stress. indicates tensile stress, and below 0 indicates compressive stress.
図に於いて、■は裏面加熱の場合、■が表面加熱の場合
をそれぞれ示している。In the figure, ■ indicates the case of back side heating, and ■ indicates the case of front side heating.
図から判るように、ストレスは成長温度に依り変化し、
裏面加熱した場合、引っ張り応力から圧縮応力まで分布
するので、成長温度を適切に選択することで低ストレス
状態の膜が得られ、剥離などの問題は少なくなる。然し
なから、表面加熱の場合には、常に圧縮応力が加わった
状態となり、しかも、その絶対値が大きく、従って、剥
離などの問題を生じ易い。As can be seen from the figure, stress changes depending on the growth temperature.
When the back side is heated, the stress is distributed from tensile stress to compressive stress, so by appropriately selecting the growth temperature, a film with low stress can be obtained and problems such as peeling can be reduced. However, in the case of surface heating, compressive stress is always applied, and its absolute value is large, so problems such as peeling are likely to occur.
このようなことから、裏面加熱の方が好ましいと考えら
れる。For these reasons, backside heating is considered preferable.
本発明に依る半導体デバイス製造装置に於いては、反応
室とＩＲ線発生源との間にＴＲ線のうちの約１ 〔μｍ
〕を越える波長の光を遮断するフィルタを設置しである
。In the semiconductor device manufacturing apparatus according to the present invention, the distance between the reaction chamber and the IR radiation source is approximately 1 [μm
] A filter is installed to block light with wavelengths exceeding .
前記構成を採ることに依り、半導体基板は波長が略１
〔μｍ〕以下のＴＲ線で加熱され、そのＴＲ線は、選択
成長を行う下地の如何、即ち、ｎ型不純物導入領域であ
るかｐ型不純物導入領域であるかに拘わらず均一に吸収
され、従って、その表面温度は路間−となるものであっ
て、何れの箇所に於いても選択成長開始は同時であると
共に成長速度も同じであり、その結果、選択成長させた
Ｗ脱酸いはＷＳｉｘ膜の膜厚は均一になるものであって
、この選択成長技術は、例えば１３ｉ −ＣＭＯ３（ｂ
ｉｐｏｌａｒ−ｃｏｍｐｌｅｍｅｎｔａｒｙ ｍｅｔ
ａｌ ｏｘｉｄｅ ｓｅｍｉｃｏｎｄｕｃｔｏｒ）
や１６Ｍ６Ｍピットル６ビットのダイナミック・ランダ
ム・アクセス・メモリ （ｄｙｎａｍｉｃ ｒａｎｄ
ｏｍ ａｃｃｅｓｓ ｍｅｍｏ ｒ ｙ ： ＤＲ
ＡＭ）等の製造には必須とされているものであるから、
これが安定に実施できることは、この種の半導体装置を
製造する上で大変好ましいことであり、半導体装置に於
ける集積度の向上や信頚性の向上に大きく寄与すること
ができる。By adopting the above configuration, the semiconductor substrate has a wavelength of approximately 1
It is heated by a TR line of [μm] or less, and the TR line is uniformly absorbed regardless of the substrate for selective growth, that is, whether it is an n-type impurity doped region or a p-type impurity doped region, Therefore, the surface temperature is -, and the selective growth starts at the same time and the growth rate is the same at any location.As a result, the selectively grown W deoxidized or The thickness of the WSix film is uniform, and this selective growth technique is suitable for example when using 13i-CMO3(b
ipolar-complementary met
al oxide semiconductor)
and 16M6M pittle 6-bit dynamic random access memory (dynamic rand
om access memory: DR
Since it is essential for the production of AM) etc.
The fact that this can be carried out stably is very desirable in manufacturing this type of semiconductor device, and can greatly contribute to improving the degree of integration and reliability of semiconductor devices.
第１図は本発明の原理を解説する為の半導体デバイス製
造装置の要部説明図、第２図は第１図に見られる装置に
於けるＩＲ線発生源ｌで発生されたＩＲ線のスペクトル
強度分布を表す線図、第３図は第１図に見られる装置に
於けるフィルタ２を透過したＩＲ線のスペクトル強度分
布を表す線図、第４図は本発明一実施例を解説する為の
要部説明図、第５図は電極を成長させた場合の成長時間
と成長膜厚との関係を説明する為の線図、第６図は裏面
加熱と表面加熱との関係を説明する為の線図、第７図は
裏面加熱或いは表面加熱を行った場合の膜ストレスの関
係を説明する為の線図、第８図は成る種の半導体装置の
要部切断側面図、第９図は第８図に見られるように電極
を成長させた場合に於ける成長時間と成長膜厚との関係
について説明する為の線図をそれぞれ表している。
図に於いて、１はＩＲ線発生源、２は波長が約１ 〔μ
ｍ〕を越える光を阻止するフィルタ、３は反応室、３Ａ
は反応ガス導入管、３Ｂはガス排出管、４はサセプタ、
５は半導体基板、６は波長が約１ 〔μｍ〕以下のＩＲ
線をそれぞれ示している。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −
波長〔μｍ〕
第２図
第１図
波長〔μｍ〕
第３図
本完明−実施例を解説する為の要部説明図第４図
成長温度（”Ｃ）
（ＩＲ裏面加熱）
裏面加熱と表面加熱との関係を説明する為の線図第６図
成長時間〔分〕
第５図
成長温度（’Ｃ）
第７図
成る種の半導体装置の要部切断側面図
第８図
成長時間〔分〕
第９図Fig. 1 is an explanatory diagram of the main parts of a semiconductor device manufacturing apparatus for explaining the principle of the present invention, and Fig. 2 is a spectrum of IR rays generated by the IR ray generation source l in the apparatus shown in Fig. 1. A diagram showing the intensity distribution; FIG. 3 is a diagram showing the spectral intensity distribution of the IR rays transmitted through the filter 2 in the apparatus shown in FIG. 1; FIG. 4 is a diagram for explaining one embodiment of the present invention. Figure 5 is a diagram to explain the relationship between growth time and growth film thickness when growing an electrode, Figure 6 is a diagram to explain the relationship between back side heating and front side heating. FIG. 7 is a diagram for explaining the relationship between film stress when back side heating or front surface heating is performed, FIG. 8 is a cutaway side view of the main part of a semiconductor device, and FIG. As shown in FIG. 8, diagrams are shown for explaining the relationship between the growth time and the thickness of the grown film when the electrode is grown. In the figure, 1 is the IR radiation source, 2 is the wavelength of approximately 1 [μ
m], 3 is a reaction chamber, 3A is a filter that blocks light exceeding
is a reaction gas introduction pipe, 3B is a gas discharge pipe, 4 is a susceptor,
5 is a semiconductor substrate, 6 is an IR with a wavelength of about 1 [μm] or less
Each line is shown. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Wavelength [μm] Figure 2 Figure 1 Wavelength [μm] Figure 3 Book Complete - To explain the Examples Main part explanatory diagram Figure 4 Growth temperature ('C) (IR back heating) Diagram to explain the relationship between back side heating and front heating Figure 6 Growth time [minutes] Figure 5 Growth temperature ('C) Figure 7: Cutaway side view of essential parts of the type of semiconductor device Figure 8: Growth time [minutes] Figure 9
Claims (1)
サセプタ上には半導体基板が配設される反応室と、 該反応室に対向して配置されて半導体基板を加熱する赤
外線発生源と、 前記反応室と該赤外線発生源との間に配設され且つ該赤
外線発生源が発生する赤外線のうち前記半導体基板の何
れの箇所に於いても均一に吸収される波長の光を透過す
るフィルタと を備えてなることを特徴とする半導体デバイス製造装置
。[Scope of Claims] A reaction chamber having a susceptor, a reaction gas inlet pipe, and a gas discharge pipe, on which a semiconductor substrate is disposed; an infrared ray generation source for heating; and a wavelength of infrared rays disposed between the reaction chamber and the infrared ray generation source and uniformly absorbed in any part of the semiconductor substrate among the infrared rays generated by the infrared ray generation source; 1. A semiconductor device manufacturing apparatus, comprising: a filter that transmits light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21256588A JPH0262036A (en) | 1988-08-29 | 1988-08-29 | Semiconductor device manufacturing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21256588A JPH0262036A (en) | 1988-08-29 | 1988-08-29 | Semiconductor device manufacturing apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262036A true JPH0262036A (en) | 1990-03-01 |
Family
ID=16624808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21256588A Pending JPH0262036A (en) | 1988-08-29 | 1988-08-29 | Semiconductor device manufacturing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262036A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100445431B1 (en) * | 1997-08-20 | 2004-11-03 | 삼성에스디아이 주식회사 | Apparatus for baking material deposited on surface of cathode ray tube panel, including infrared radiation unit and filter, and baking method thereof |
| JP2008205427A (en) * | 2007-01-24 | 2008-09-04 | Sumitomo Electric Ind Ltd | Gas phase reaction growth apparatus and gas phase reaction growth method |
| JP2010093282A (en) * | 2000-12-04 | 2010-04-22 | Mattson Technology Canada Inc | Method and system for heat treatment |
| US7781947B2 (en) | 2004-02-12 | 2010-08-24 | Mattson Technology Canada, Inc. | Apparatus and methods for producing electromagnetic radiation |
| JP2011100849A (en) * | 2009-11-06 | 2011-05-19 | Ushio Inc | Treatment method of silicon thin film and flash lamp irradiation device |
-
1988
- 1988-08-29 JP JP21256588A patent/JPH0262036A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100445431B1 (en) * | 1997-08-20 | 2004-11-03 | 삼성에스디아이 주식회사 | Apparatus for baking material deposited on surface of cathode ray tube panel, including infrared radiation unit and filter, and baking method thereof |
| JP2010093282A (en) * | 2000-12-04 | 2010-04-22 | Mattson Technology Canada Inc | Method and system for heat treatment |
| US7781947B2 (en) | 2004-02-12 | 2010-08-24 | Mattson Technology Canada, Inc. | Apparatus and methods for producing electromagnetic radiation |
| JP2008205427A (en) * | 2007-01-24 | 2008-09-04 | Sumitomo Electric Ind Ltd | Gas phase reaction growth apparatus and gas phase reaction growth method |
| JP2011100849A (en) * | 2009-11-06 | 2011-05-19 | Ushio Inc | Treatment method of silicon thin film and flash lamp irradiation device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4617087A (en) | Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits | |
| Kumagawa et al. | Epitaxial growth with light irradiation | |
| US4924807A (en) | Apparatus for chemical vapor deposition | |
| US4672740A (en) | Beam annealed silicide film on semiconductor substrate | |
| US5244501A (en) | Apparatus for chemical vapor deposition | |
| US5404046A (en) | Flat semiconductor wiring layers | |
| JPH01119029A (en) | High speed heat plasma multiple treatment reactor and its application | |
| US6506675B1 (en) | Copper film selective formation method | |
| JPH0262036A (en) | Semiconductor device manufacturing apparatus | |
| JPH0917742A (en) | Heat-treating apparatus | |
| US6656854B2 (en) | Method of forming a low dielectric constant film with tetramethylcyclotetrasiloxane (TMCTS) and LPCVD technique | |
| JP3072807B2 (en) | Method for manufacturing semiconductor device | |
| EP0203800A2 (en) | Method for producing semiconductor device | |
| JPS587864A (en) | Semicondutor device and manufacture thereof | |
| JPS5994829A (en) | Manufacture of semiconductor device | |
| JPS6037118A (en) | Plasma vapor phase reaction method | |
| JP3082934B2 (en) | Semiconductor device using single crystal aluminum and method for manufacturing the same | |
| JP3110472B2 (en) | Selective metal deposition method | |
| JP2732903B2 (en) | Method for manufacturing electrode wiring of semiconductor integrated circuit device | |
| JP3393213B2 (en) | Film formation method | |
| JPH04343418A (en) | Selective metal cvd device | |
| JPH0778785A (en) | Method of nitriding barrier metal film | |
| JPS61224364A (en) | Manufacture of thin film transistor and manufacturing equipment | |
| JPH04333223A (en) | Film forming method and device thereof | |
| KR100474190B1 (en) | Method of thermal process in a semiconductor device |