JPH0259834A - Input/output controller - Google Patents

Input/output controller

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Publication number
JPH0259834A
JPH0259834A JP63211126A JP21112688A JPH0259834A JP H0259834 A JPH0259834 A JP H0259834A JP 63211126 A JP63211126 A JP 63211126A JP 21112688 A JP21112688 A JP 21112688A JP H0259834 A JPH0259834 A JP H0259834A
Authority
JP
Japan
Prior art keywords
bus
input
time information
trace
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63211126A
Other languages
Japanese (ja)
Inventor
Tatsuo Noguchi
野口　辰生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63211126A priority Critical patent/JPH0259834A/en
Publication of JPH0259834A publication Critical patent/JPH0259834A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To add the common time information to each input/output controller and to assure the simultaneity of the trace information on these input/output controllers by detecting the halt period of a common bus, fetching the time information outputted to the common bus during the bus halt period, and adding the fetched time information to the trace information. CONSTITUTION:An action command given to an input/output controller 100 from a CPU is sent to an execution control circuit 103 via a common bus 101 and a common bus control circuit 102 to secure the working of the controller 100. A trace control circuit 106 traces the working state of the circuit 103 and stores successively the trace information to a trace memory 107. A bus halt period monitor circuit 105 monitors the halt period of the bus 101 and informs the detected bus halt period to a time monitor circuit 104. The circuit 10 fetches the time information outputted to the bus 101 to transmit it to the circuit 106 and adds the time information to the trace information to store them in the memory 107. Thus it is possible to assure the simultaneity of those trace information with addition of the common time information.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、データ処理システムの入出力制御装置に関し
、特に、自らの動作状態のトレースを行なう入出力制御
装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output control device for a data processing system, and more particularly to an input/output control device that traces its own operating state.

従来の技術 従来、この種の入出力制御装置において、自らの動作状
態のトレースを行なう際には、独自の時刻情報を付加す
るかあるいは全く時刻情報を付加していなかった。BACKGROUND OF THE INVENTION Conventionally, in this type of input/output control device, when tracing its own operating state, it has either added its own time information or added no time information at all.

発明が解決しようとする課題 上述した従来の入出力制御装置を使用したデータ処理シ
ステムにおいては、入出力制御装置のもつトレース情報
は他の人出力制御装置のもつトレース情報とは時刻の面
において無関係であり、双方のトレース情報の同時性を
保証することはできなかった。Problems to be Solved by the Invention In the data processing system using the conventional input/output control device described above, the trace information held by the input/output control device is unrelated in terms of time to the trace information held by other human output control devices. Therefore, it was not possible to guarantee the simultaneity of both trace information.

本発明は従来の技術に内在する上記実情に鑑みてなされ
たものであり、従って本発明の目的は、各人出力制御装
置に共通の時刻情報を付加することによりそれぞれのト
レース情報の同時性を保証することを可能とした新規な
入出力制御装置を提供することにある・。The present invention has been made in view of the above-mentioned circumstances inherent in the prior art, and an object of the present invention is to increase the simultaneity of each trace information by adding common time information to each individual's output control device. Our objective is to provide a new input/output control device that can guarantee

課題を解決するための手段 上記目的を達成する為に、本発明に係る入出力制御装置
は、共通バスのバス休止期間を検出する手段と、バス休
止期間中に共通バスに出力されている時刻情報を取り込
む手段と、取込まれた時刻情報をトレース情報に付加す
る手段とを備えて構成される。Means for Solving the Problems In order to achieve the above object, an input/output control device according to the present invention includes means for detecting a bus suspension period of a common bus, and means for detecting a bus suspension period of a common bus, and a means for detecting a bus suspension period of a common bus, and a means for detecting a bus suspension period of a common bus. It is configured to include means for capturing information and means for adding the captured time information to trace information.

実施例 次に本発明をその好ましい一実施例について図面を参照
して具体的に説明する。Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

第１図は本発明に係る入出力制御装置の一実施例を示す
ブロック構成図である。FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention.

第１図を参照するに１本発明の入出力制御装置１００は
共通バス１０１を介してＣＰｕ及びＳＣＰ　（システム
監視装置）と接続されている。ＣＰＵからの入出力制御
装置１００への動作指令は共通バス１０１及び共通バス
制御回路１０２を介して実行制御回路１０：３に伝達さ
れ、入出力制御装置としての動作を行なう。１−レース
制御回路１０６は、実行制御回路１０３の動作状態をト
レースし、トレースメモリ１０７にその情報を逐次格納
する。Referring to FIG. 1, an input/output control device 100 of the present invention is connected to a CPU and an SCP (system monitoring device) via a common bus 101. Operation commands from the CPU to the input/output control device 100 are transmitted to the execution control circuit 10:3 via the common bus 101 and the common bus control circuit 102, and the execution control circuit 10:3 operates as an input/output control device. 1-Race control circuit 106 traces the operating state of execution control circuit 103 and sequentially stores the information in trace memory 107.

バス休止期間監視回路１０５は、共通バス１０１のバス
休止期間を監視しており、バス休止期間であることを検
出すると９時刻監視回路１０４にその旨を通知する。時
刻監視装置１０４は共通バス１０１上に出力さ九ている
時刻情報を取り込みトレース制御回路１０６に伝達する
。トレース制御ｒＯ１路１０６は時刻情報を１〜レース
情報に付加してトレースメモリ１０７へ格納する。The bus suspension period monitoring circuit 105 monitors the bus suspension period of the common bus 101, and when it detects a bus suspension period, it notifies the 9-time monitoring circuit 104 to that effect. Time monitoring device 104 takes in time information output on common bus 101 and transmits it to trace control circuit 106 . The trace control rO1 path 106 adds time information to 1 to race information and stores them in the trace memory 107.

第２図は本発明の入出力制御装置を用いたデータ処理シ
ステムの構成例を示す図である。FIG. 2 is a diagram showing an example of the configuration of a data processing system using the input/output control device of the present invention.

第２１ｆｉを参照するに、本発明に係る入出力制御装置
＋００及びｔｏｏ’　、　ＣＰ１１２０］、ＳＣ１”２
囲は共通バス１０１を介して接続されている。Referring to the 21st fi, the input/output control device +00 and too', CP1120], SC1"2 according to the present invention
The surroundings are connected via a common bus 101.

人出力制御装置１００及びｔｏｏ’　はＣＰＵ２０１の
指令によりそれぞれ動作している。　５ＣＰ２０２は共
通バス１０１を制御しており、共通バス１０１が休止期
間の時に共通バス１０１に対して時刻情報を出力する。The human output control device 100 and too' each operate according to instructions from the CPU 201. The 5CP 202 controls the common bus 101 and outputs time information to the common bus 101 when the common bus 101 is in an idle period.

入出力制御装置１００及び１００′は、バス休止期間中
に共通バスｌｏｔに出力された時刻情報を自らの１−レ
ース情報に付加し、トレースメモリに格納する。The input/output control devices 100 and 100' add the time information output to the common bus lot during the bus suspension period to their own 1-race information, and store it in the trace memory.

発明の詳細 な説明したように５本発明の入出力制御装置を用いたデ
ータ処理システムにおいては、各々のトレース情報の同
時性は共通の時刻情報を付加することにより保証される
。As described in the detailed description of the invention, in the data processing system using the input/output control device of the present invention, the simultaneity of each piece of trace information is guaranteed by adding common time information.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係る入出力制御装置の一実施例を示す
ブロック構成図、第２図は本発明の入出力制御装置を用
いたデータ処理システムの構成例を示す図である。 【（）０、！００’　、、、本発明の入出力制御装置、
１０１．、。 共通バス、１０２．、、共通バス制御回路、１０３．、
、実行制御回路、１０４．、、時刻監視回路、　１０５
．、、バス休止期ｒｉＪｌ監視回路、１０６．、、　ｈ
　１７一ス制御回路、　１０７．、。FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention, and FIG. 2 is a diagram showing an example of the configuration of a data processing system using the input/output control device of the present invention. [()0,! 00',,,input/output control device of the present invention,
101. ,. Common bus, 102. ,, common bus control circuit, 103. ,
, execution control circuit, 104. ,,time monitoring circuit, 105
．． ,, Bus idle period riJl monitoring circuit, 106. ,,h
17 first control circuit, 107. ,.

Claims (1)

【特許請求の範囲】[Claims] 中央処理装置（以下ＣＰＵと略記する）、システム監視
装置（以下ＳＣＰと略記する）とに共通入出力バスを介
して接続されている入出力制御装置であって、自らの内
部の動作状態をトレースする入出力制御装置において、
共通バスのバス休止期間を検出する手段と、バス休止期
間中に共通バスに出力されている時刻情報を取り込む手
段と、取り込まれた時刻情報をトレース情報に付加する
手段とを有することを特徴とした入出力制御装置。An input/output control device that is connected to a central processing unit (hereinafter abbreviated as CPU) and a system monitoring device (hereinafter abbreviated as SCP) via a common input/output bus, and traces its own internal operating status. In the input/output control device that
The present invention is characterized by having means for detecting a bus idle period of the common bus, means for capturing time information output to the common bus during the bus idle period, and means for adding the captured time information to trace information. input/output controller.
JP63211126A 1988-08-25 1988-08-25 Input/output controller Pending JPH0259834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63211126A JPH0259834A (en) 1988-08-25 1988-08-25 Input/output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63211126A JPH0259834A (en) 1988-08-25 1988-08-25 Input/output controller

Publications (1)

Publication Number Publication Date
JPH0259834A true JPH0259834A (en) 1990-02-28

Family

ID=16600822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63211126A Pending JPH0259834A (en) 1988-08-25 1988-08-25 Input/output controller

Country Status (1)

Country Link
JP (1) JPH0259834A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2510948A (en) * 2013-02-19 2014-08-20 Advanced Risc Mach Ltd Data processing apparatus, trace unit and diagnostic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2510948A (en) * 2013-02-19 2014-08-20 Advanced Risc Mach Ltd Data processing apparatus, trace unit and diagnostic apparatus
US9361204B2 (en) 2013-02-19 2016-06-07 Arm Limited Generating trace data including a lockup identifier indicating occurrence of a lockup state
GB2510948B (en) * 2013-02-19 2020-11-25 Advanced Risc Mach Ltd Data processing apparatus, trace unit and diagnostic apparatus

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