JPS6049365B2 - Low power consumption crystal oscillator circuit - Google Patents
Low power consumption crystal oscillator circuitInfo
- Publication number
- JPS6049365B2 JPS6049365B2 JP53060926A JP6092678A JPS6049365B2 JP S6049365 B2 JPS6049365 B2 JP S6049365B2 JP 53060926 A JP53060926 A JP 53060926A JP 6092678 A JP6092678 A JP 6092678A JP S6049365 B2 JPS6049365 B2 JP S6049365B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- oscillation
- output
- input
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 title claims description 30
- 230000010355 oscillation Effects 0.000 claims description 64
- 230000000295 complement effect Effects 0.000 claims description 21
- 239000003990 capacitor Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000007704 transition Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
- H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Description
【発明の詳細な説明】
本発明は水晶発振回路、特に相補形ＭＯＳゲート回路て
構成した水晶発振回路を更に低消費電力て動作させる為
の発振回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a crystal oscillation circuit, and particularly to an oscillation circuit for operating a crystal oscillation circuit constituted by complementary MOS gate circuits with lower power consumption.
水晶発振回路は周波数安定度が非常に良好で、フ且つ使
用可能な発振周波数が広範囲である為、現在非常に良く
使用されている。一方相補形ＭＯＳゲート回路は低消費
電力て動作する事及び雑音余裕度が大きい等の特徴を有
する為、半導体集積回路の分野で広く用いられている。
この相補形５ＭＯＳゲート回路の特徴を利用して水晶発
振回路に応用した公知例が第１図に示す回路である。該
発振回路は直列接続された負荷容量を持つ***振点発振
回路であり、増幅器としての相補形ＭＯＳインバータ回
路１と、帰還回路２とから構成されている。帰還回路２
は帰還抵抗３と水晶発振子４と入力容量５と出力容量６
と、発振出力端子７とから成る。該相補形の水晶発振回
路は平均消費電力が約１〜１０１１１Ｗ程度であり、電
池で長時間動作を必要とする時計の発振源等にしばしば
利用される。しかし相補形ＭＯＳゲート回路が低消費電
力動作を特徴とするとは言えども、これらを多数使用し
て大きな回路装置を構成した場合の全平均消費電力は無
視できない値となるので、回路の各部に於いて総合特性
を損なう事なく消費電力を更に切詰める必要が生じる。
本発明は前述の事柄を解決する為相補形ＭＯＳゲート回
路を使用した水晶発振回路の発振出力信号を間欠的にし
かもひんぱんに使用する装置、例えばＣＰＵ（中央総括
制御回路）のクロック信号源に適する相補形ＭＯＳゲー
ト回路て構成された低消費電力水晶発振回路を提供する
ものである。本発明は水晶発振回路の発振出力信号を特
定の目的に使用したい場合、該発振回路を構成している
帰還回路の帰還抵抗を接地又は電源電位状態にして発振
必要条件からはずす事により発振回路を停止させ、発振
出力信号が必要な楊合帰還抵抗を元の発振状態にもどし
て平均消費電力を大巾に引下げようとするものである。Crystal oscillator circuits have very good frequency stability and can be used over a wide range of oscillation frequencies, so they are very commonly used today. On the other hand, complementary MOS gate circuits are widely used in the field of semiconductor integrated circuits because they operate with low power consumption and have a large noise margin.
A known example in which the characteristics of this complementary 5MOS gate circuit are applied to a crystal oscillation circuit is the circuit shown in FIG. The oscillation circuit is an anti-resonance point oscillation circuit having a load capacitance connected in series, and is composed of a complementary MOS inverter circuit 1 as an amplifier and a feedback circuit 2. Feedback circuit 2
are feedback resistor 3, crystal oscillator 4, input capacitor 5, and output capacitor 6
and an oscillation output terminal 7. The complementary crystal oscillation circuit has an average power consumption of about 1 to 10111 W, and is often used as an oscillation source for watches that require long-term battery operation. However, although complementary MOS gate circuits are characterized by low power consumption, when a large circuit device is constructed using a large number of complementary MOS gate circuits, the total average power consumption becomes a value that cannot be ignored. Therefore, it becomes necessary to further reduce power consumption without impairing overall characteristics.
In order to solve the above-mentioned problems, the present invention is suitable for a device that uses an oscillation output signal of a crystal oscillation circuit using a complementary MOS gate circuit intermittently and frequently, such as a clock signal source for a CPU (central control circuit). The present invention provides a low power consumption crystal oscillation circuit configured with complementary MOS gate circuits. According to the present invention, when it is desired to use the oscillation output signal of a crystal oscillation circuit for a specific purpose, the oscillation circuit is removed from the oscillation requirements by grounding the feedback resistor of the feedback circuit constituting the oscillation circuit or bringing it to the power supply potential state. The aim is to significantly reduce the average power consumption by stopping the feedback resistor, which requires an oscillation output signal, and returning it to its original oscillation state.
この場合発振回路は発振停止状態から安定した発振状態
になるまで２〜３０ｆ１Ｓ程度時間がかかるので、本発
明の回路構成では発振開始後、安定状態になつてから発
振出力信号を出力する様に構成されている。以下本発明
の実施例を第２図及び第３図により詳細に説明する。In this case, it takes about 2 to 30f1S for the oscillation circuit to go from the oscillation stopped state to the stable oscillation state, so the circuit configuration of the present invention is configured to output the oscillation output signal after the oscillation starts and the stable state is reached. has been done. Embodiments of the present invention will be described in detail below with reference to FIGS. 2 and 3.
第２図に於いて８は第１図に示す従来の相補形ＭＯＳイ
ンバータ回路１を使用した水晶発振回路である。In FIG. 2, 8 is a crystal oscillation circuit using the conventional complementary MOS inverter circuit 1 shown in FIG.
９はＰ型ＭＯＳトランジスタ１０，１１：，とＮ型ＭＯ
Ｓトランジスタ１２と相補形ＭＯＳインバータ回路１３
と充電用コンデンサ１４と高入力インピーダンスを有す
る相補形ＭＯＳインバータ回路１５とから構成された遅
延回路である。9 is a P-type MOS transistor 10, 11:, and an N-type MOS transistor.
S transistor 12 and complementary MOS inverter circuit 13
, a charging capacitor 14, and a complementary MOS inverter circuit 15 having high input impedance.
発振停止信号端子１７は発振停止回路手段としてのＮ４
型ＭＯＳトランジスタ１６のゲート領域及び遅延回路９
の充電用コンデンサ１４の電荷を放電させる為のＮ型Ｍ
ＯＳトランジスタ１２のゲート領域に接続され且つＮ型
ＭＯＳトランジスタ１６のドレイン領域は水晶発振回路
８の相補形ＭＯＳインバータ回路１の入力部に接続され
、ソース領域は接地される。相補形ＭＯＳインバータ回
路１の出力部は遅延回路９のＰ型ＭＯＳトランジスタ１
１７のゲート領域及び相補形ＭＯＳインバータ回路１３
を通してＰ型ＭＯＳトランジスタ１０のゲート領域に結
合される。Ｐ型ＭＯＳトランジスタ１０，１１とＮ型Ｍ
ＯＳトランジスタ１２は直列に接続され、且つＭＯＳト
ランジスタ１０のソースθ領域は電源単子１８に結合さ
れ、ＭＯＳトランジスタ１２のソース領域は接地されて
いる。充電用コンデンサ１４はＭＯＳトランジスタ１２
と並列に接続され、該接続部１９は高入力インピーダン
スを有する相補形ＭＯＳインバータ回路１５に接ク続さ
れている。該インバータ回路１５と水晶発振回路８の出
力部はそれぞれＮＯＲ論理回路２０に結合され、該出力
部は発振出力端子２１に接続されている。第２図の動作
を第３図に従つて説明する。The oscillation stop signal terminal 17 is connected to N4 as an oscillation stop circuit means.
Gate region of type MOS transistor 16 and delay circuit 9
N-type M for discharging the charge of the charging capacitor 14 of
It is connected to the gate region of the OS transistor 12, the drain region of the N-type MOS transistor 16 is connected to the input part of the complementary MOS inverter circuit 1 of the crystal oscillation circuit 8, and the source region is grounded. The output part of the complementary MOS inverter circuit 1 is the P-type MOS transistor 1 of the delay circuit 9.
17 gate regions and complementary MOS inverter circuit 13
It is coupled to the gate region of P-type MOS transistor 10 through. P-type MOS transistors 10 and 11 and N-type M
The OS transistors 12 are connected in series, and the source θ region of the MOS transistor 10 is coupled to the power supply unit 18, and the source region of the MOS transistor 12 is grounded. The charging capacitor 14 is a MOS transistor 12
The connecting portion 19 is connected to a complementary MOS inverter circuit 15 having a high input impedance. The output parts of the inverter circuit 15 and the crystal oscillation circuit 8 are each coupled to a NOR logic circuit 20, and the output parts are connected to an oscillation output terminal 21. The operation shown in FIG. 2 will be explained with reference to FIG.
ノ 発振停止信号端子１７に第３図Ａ，ａの゛゜Ｌ゛レ
ベル信号が入力されると、該信号はＭＯＳトランジスタ
１２，１６のゲート領域に印加される。When the ``L'' level signal shown in FIG.
ＭＯＳトランジスタ１６はオフ状態となり発振回路８の
ＭＯＳインバータ回路１の入力部と接地間は絶縁され第
３図Ｂ，ｂの如く発振開始状態となる。一方遅延回路９
のＭＯＳトランジスタ１２もオフ状態となり接続部１９
と接地間は絶縁状態となる。ＮＯＲ論理回路２０には発
振回路８の出力及び高入力インピーダンス・インバータ
回路１５の出力が入力されているが、発振開始時には充
電用コンデンサ１４はまだ電荷が充電されていない為、
インバータ回路１５の出力ぱ゛Ｈ゛レベル状態にある。
従つて出力端子２１には第３図Ｄ（７）ｄの如く゜゜Ｌ
゛レベル状態となり発振回路８からの信号は出力端子２
１に出力されない。第３図Ｂに示す如く発振開始時から
発振状態が安定するまでの期間Ｔｄに於いて水晶発振回
路８の出力及びインバータ回路１３を通したその反転出
力がＰ型ＭＯＳトランジスタ１０，１１のゲート領域に
印加され交互にオン・オフ状態となる。トランジスタ１
０及び１１のオン・オフ状態の遷移期間に極めて小さい
電流が流れ充電用コンデンサ１４を第３図Ｃ（７）ｃの
如く電荷を蓄積し、高入力インピーダンス回路１５の閾
値電圧まで到達するとインバータ回路１５を反転させ、
該出力は“゜Ｌ゛レベルとなる。ＮＯＲ論理回路２０は
インバータ回路１５の出力が゛Ｌ゛レベル状態である間
は、水晶発振回路８の発振出力が第３図Ｄのｅの如く出
力端子２１に出力される。次に発振停止信号端子１７に
第３図Ａ，ｆの如く゜“Ｈ゛レベル信号が入力されると
、ＭＯＳトランジスタ１６は導通状態となり、発振回路
８内のインバータ回路１の入力部は接地電位になり、発
振を停止させる。The MOS transistor 16 is turned off, and the input section of the MOS inverter circuit 1 of the oscillation circuit 8 is insulated from the ground, and oscillation starts as shown in FIGS. 3B and 3B. On the other hand, delay circuit 9
MOS transistor 12 is also turned off, and connection portion 19
and ground are insulated. The output of the oscillation circuit 8 and the output of the high input impedance inverter circuit 15 are input to the NOR logic circuit 20, but since the charging capacitor 14 is not yet charged when oscillation starts,
The output of the inverter circuit 15 is at a high level.
Therefore, the output terminal 21 has ゜゜L as shown in Fig. 3 D (7) d.
The signal from the oscillation circuit 8 is in the level state and the signal is sent to the output terminal 2.
1 is not output. As shown in FIG. 3B, during the period Td from the start of oscillation to the stabilization of the oscillation state, the output of the crystal oscillation circuit 8 and its inverted output through the inverter circuit 13 are applied to the gate regions of the P-type MOS transistors 10 and 11. is applied to the voltage and turns on and off alternately. transistor 1
An extremely small current flows during the transition period between the on and off states of 0 and 11, causing the charging capacitor 14 to accumulate charge as shown in FIG. Reverse 15,
The output is at the "L" level. While the output of the inverter circuit 15 is at the "L" level, the oscillation output of the crystal oscillation circuit 8 is output to the output terminal as shown in e of FIG. 3D. Next, when a "H" level signal is input to the oscillation stop signal terminal 17 as shown in FIG. The input section becomes ground potential, stopping oscillation.
一方Ｎ型ＭＯＳトランジスタ１２も導通状態となり充電
用コンデンサ１４に蓄えられた電荷を放電させる。従つ
てインバータ回路１５の出力にぱ゜Ｈ゛レベルが現われ
、ＮＯＲ論理回路２０の出力部は入力端子に゛Ｌ゛レベ
ル信号が入力されるまで゜゛Ｌ゛レベル状態を維持する
。なお所望の遅延時間は充電用コンデンサ１４の容量値
とＭＯＳトランジスタ１０，１１のチャンネル長を変化
させる事により得られる。以上説明した様に本発明の回
路構成では水晶発振回路が発振開始してから安定状態に
なるまでの遷移期間にこの不安定状態にある発振出力信
号が出力端子に現れない為、この発振出力を利用してい
る装置に対して誤動作を与えない事及び装置が動作して
いない期間に発振回路の動作を停止させてしまうので消
費電力の削減が計られる利点を有している。On the other hand, the N-type MOS transistor 12 also becomes conductive to discharge the charge stored in the charging capacitor 14. Therefore, the high level appears at the output of the inverter circuit 15, and the output section of the NOR logic circuit 20 maintains the low level state until the low level signal is input to the input terminal. Note that a desired delay time can be obtained by changing the capacitance value of the charging capacitor 14 and the channel lengths of the MOS transistors 10 and 11. As explained above, in the circuit configuration of the present invention, the oscillation output signal in the unstable state does not appear at the output terminal during the transition period from when the crystal oscillation circuit starts oscillating until it becomes stable. This has the advantage of not causing any malfunction to the equipment being used, and of reducing power consumption since the operation of the oscillation circuit is stopped during the period when the equipment is not operating.
本発明は水晶発振回路の発振出力信号を間欠的にしかも
使用頻度の高い装置、例えは単一の半導体基板に組込ま
れたマイクロプロセッサ装置のクロック信号源として特
に効果を発揮するものである。The present invention is particularly effective as a clock signal source for a device that uses the oscillation output signal of a crystal oscillation circuit intermittently and frequently, such as a microprocessor device built into a single semiconductor substrate.
第１図は従来の相補形ＭＯＳゲート回路で構成した水晶
発振回路である。
第２図は本発明による遅延回路付きの低消費電力水晶発
振回路てあり、第３図は該回路の動作を示すタイムチャ
ートである。１，１３，１５・・・・・相補形ＭＯＳイ
ンバータ回２路、２・・・・・・帰還回路、３・・・・
・・帰還抵抗、４・・・・・・水晶発振子、５・・・・
・・入力容量、６・・・・・・出力容量、７・・・発振
出力端子、８・・・・・・水晶発振回路、９・・・・遅
延回路、１０，１１・・・・・Ｐ型ＭＯＳトランジスタ
、１２，１６・・・・・・Ｎ型ＭＯＳトランジスタ、１
）４・・・・・・充電用コンデンサ、１７・・・・・・
発振停止信号端子、１８・・・・・・電源端子、１９・
・・・・・接続部、２０・・・ＮＯＲ論理回路、２１・
・・・・出力端子。FIG. 1 shows a crystal oscillation circuit constructed from conventional complementary MOS gate circuits. FIG. 2 shows a low power consumption crystal oscillator circuit with a delay circuit according to the present invention, and FIG. 3 is a time chart showing the operation of the circuit. 1, 13, 15...2 complementary MOS inverter circuits, 2...Feedback circuit, 3...
...Feedback resistor, 4...Crystal oscillator, 5...
...Input capacitance, 6...Output capacitance, 7...Oscillation output terminal, 8...Crystal oscillation circuit, 9...Delay circuit, 10, 11... P-type MOS transistor, 12, 16...N-type MOS transistor, 1
)4... Charging capacitor, 17...
Oscillation stop signal terminal, 18... Power supply terminal, 19.
... Connection section, 20 ... NOR logic circuit, 21.
...Output terminal.
Claims (1)
補形ＭＯＳインバータ回路を含む水晶発振回路と、ＮＯ
Ｒ論理回路と、前記水晶発振回路の発振出力を受け入れ
る入力端子及び前記発振出力が安定状態になるまで外部
出力端子への伝達を遅らせる制御端子を有する遅延回路
手段とから成り、前記発振停止入力信号端子と前記遅延
回路の制御端子が接続され、前記発振停止回路の出力部
が前記水晶発振回路内の相補形ＭＯＳゲート回路の入力
部に結合され、前記遅延回路と前記遅延回路の出力部が
それぞれ前記ＮＯＲ論理回路の入力部に接続されて成る
低消費電力水晶発振回路。 ２ 発振停止回路が前記発振停止入力信号端子に結合さ
れたゲート領域と、接地されたソース領域と、前記水晶
発振回路の相補形ＭＯＳゲート回路の入力部に結合され
たドレイン領域とを有するＭＯＳ型トランジスタである
特許請求の範囲第１項記載の低消費電力水晶発振回路。 ３ 遅延回路が第１のＭＯＳインバータ回路を通して前
記水晶発振回路の出力部に接続されたゲート領域と電源
端子に接続されたソース領域とドレイン領域とを有する
第１のＰ型ＭＯＳトランジスタと、前記水晶発振回路の
出力部に接続されたゲート領域と前記第１のＰ型ＭＯＳ
トランジスタのドレイン領域に接続されたソース領域と
ドレイン領域とを有する第２のＰ型ＭＯＳトランジスタ
と、前記制御端子に接続されたゲート領域と接地された
ソース領域と前記第２のＰ型ＭＯＳトランジスタのドレ
イン領域に接続されたドレイン領域とを有するＮ型ＭＯ
Ｓトランジスタと、該Ｎ型ＭＯＳトランジスタに並列に
接続された充電用コンデンサと、前記第２のＰ型ＭＯＳ
トランジスタと前記Ｎ型ＭＯＳトランジスタの接続部に
結合された高入力インピーダンスを有する入力部と前記
ＮＯＲ論理回路の入力部に接続された出力部とを有する
第２のＭＯＳインバータ回路から成る特許請求の範囲第
１項記載の低消費電力水晶発振回路。４ 単一の半導体
基板により構成された特許請求の範囲第１項記載の低消
費電力水晶発振回路。[Claims] 1. An oscillation stop circuit having an oscillation stop input signal terminal, a crystal oscillation circuit including a complementary MOS inverter circuit, and a NO.
R logic circuit; delay circuit means having an input terminal for receiving the oscillation output of the crystal oscillation circuit; and a control terminal for delaying transmission to an external output terminal until the oscillation output reaches a stable state; A terminal is connected to a control terminal of the delay circuit, an output part of the oscillation stop circuit is coupled to an input part of a complementary MOS gate circuit in the crystal oscillation circuit, and the delay circuit and the output part of the delay circuit are connected to each other. A low power consumption crystal oscillator circuit connected to an input section of the NOR logic circuit. 2. A MOS type in which the oscillation stop circuit has a gate region coupled to the oscillation stop input signal terminal, a grounded source region, and a drain region coupled to the input portion of a complementary MOS gate circuit of the crystal oscillation circuit. The low power consumption crystal oscillator circuit according to claim 1, which is a transistor. 3. A first P-type MOS transistor whose delay circuit has a gate region connected to the output part of the crystal oscillator circuit through a first MOS inverter circuit, and a source region and a drain region connected to a power supply terminal; a gate region connected to the output section of the oscillation circuit and the first P-type MOS;
a second P-type MOS transistor having a source region and a drain region connected to the drain region of the transistor; a gate region connected to the control terminal; a grounded source region; an N-type MO having a drain region connected to a drain region;
an S transistor, a charging capacitor connected in parallel to the N-type MOS transistor, and the second P-type MOS
Claims consisting of a second MOS inverter circuit having an input having a high input impedance coupled to a junction of a transistor and said N-type MOS transistor, and an output connected to an input of said NOR logic circuit. The low power consumption crystal oscillator circuit according to item 1. 4. The low power consumption crystal oscillator circuit according to claim 1, which is constructed from a single semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53060926A JPS6049365B2 (en) | 1978-05-24 | 1978-05-24 | Low power consumption crystal oscillator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53060926A JPS6049365B2 (en) | 1978-05-24 | 1978-05-24 | Low power consumption crystal oscillator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54152848A JPS54152848A (en) | 1979-12-01 |
| JPS6049365B2 true JPS6049365B2 (en) | 1985-11-01 |
Family
ID=13156471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53060926A Expired JPS6049365B2 (en) | 1978-05-24 | 1978-05-24 | Low power consumption crystal oscillator circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6049365B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139774A (en) * | 1984-12-12 | 1986-06-27 | Tokyo Keiki Co Ltd | Transmission circuit of ultrasonic length measuring machine |
| JPS6367822A (en) * | 1986-09-09 | 1988-03-26 | Nec Corp | Oscillator |
| CN102664608B (en) * | 2010-12-28 | 2015-03-11 | 博通集成电路（上海）有限公司 | Frequency multiplier and frequency multiplication method |
| US8958550B2 (en) * | 2011-09-13 | 2015-02-17 | Combined Conditional Access Development & Support. LLC (CCAD) | Encryption operation with real data rounds, dummy data rounds, and delay periods |
-
1978
- 1978-05-24 JP JP53060926A patent/JPS6049365B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54152848A (en) | 1979-12-01 |
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