JPH02294037A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH02294037A
JPH02294037A JP11427789A JP11427789A JPH02294037A JP H02294037 A JPH02294037 A JP H02294037A JP 11427789 A JP11427789 A JP 11427789A JP 11427789 A JP11427789 A JP 11427789A JP H02294037 A JPH02294037 A JP H02294037A
Authority
JP
Japan
Prior art keywords
semiconductor device
protective film
film
silicon oxide
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11427789A
Other languages
English (en)
Inventor
Koji Furuta
古田　孝司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP11427789A priority Critical patent/JPH02294037A/ja
Publication of JPH02294037A publication Critical patent/JPH02294037A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、金属配線上に、ワイヤボンディング用の開口
部を除いて２層構造の保護膜を形成した半導体装置に関
するものである。
（従来の技術） この種の従来の半導体装置について、第２図により説明
するａｎ図は，従来の半導体装置の要部拡大断面図で，
シリコン基板ｌの表面に形成されたアルミニウム配線２
は、ワイヤボンディング用の開口部を除いて，上記のシ
リコン基板１とともに、例えば、リンを重量比で数パー
セント含んだ酸化ケイ素膜３および窒化ケイ素暎４から
なる２層構造の保護膜で覆われている． なお，上記の酸化ケイ素膜３は，アルミニウム配線２に
加わる応力を緩和し、且つ外部から侵入する不純物やイ
オンを防ぎ，窒化ケイ素膜４は、低い水分透゛ｊ率を利
用して外部からの湿気の侵入を防止し，半導体装置を保
護するものである。
（発明，が解決しようとする課題） しかしながら，上記の構成では、不純物，イオンを含む
水分によって，酸化ケイｌ７４膜３のリンが溶出し，電
・解作用によって、アルミニウム配線２が溶解し，甚し
い場合には半導体装置が故障するという問題があった。
本発明は上記の問題を解決するもので、アルミニウム配
線の溶解が発生しない，信頼性のある半導体装置を提供
するものである。
（課題を解決するための手段） 上記の課題を解決するため，本発明は，窒化ケイ素膜の
開口面積を小さくシ，酸化ケイ素膜を完全に覆うもので
ある． （作　用） 上記の構成によれば、不純物，イオン等を含む水分は窒
化ケイ素膜で妨げられて、酸化ケイ素膜に到達しないの
で、リン等の不純物の溶出もなく、また、これを含む水
の電解作用によるアルミニウム配線の溶解もなくなる。
（実施例） 本発明の一実施例を第１図に示す要部拡大断面図により
説明する。同図において、本実施例が第２図に示した従
来例と異なる点は，２層構造の保護膜を具体的に、厚さ
が共に５００ｒｖ＋の酸化ケイ崇膜３と，窒化ケイ素膜
４で形成した点と，窒化ケイ素１漠４の開口部を狭くシ
，酸化ケイ素膜３の端而を完全に被覆した点である。そ
の他は変わらないので、同じ構成部品には同一符号を付
して、その説明を省略する。
本発明の実施例と従来の半導体装置を比較した結果，温
度１２５℃，湿度８５％，電源電圧５．５Ｖの環境下で
、従来構造は、５００時間で４５分の１　．　１０００
時間で４５分の３のワイヤボンディング部が溶解したの
に対し、本実施例は、１０００時間で４５分のＯであっ
た。
（発明の効果） 以上説明したように、本発明によれば、高温高湿の環境
下でも、金属配線のワイヤボンデイング部が，溶解する
ことがないので、市場故障率を大幅に低減させる信頼性
の高い半導体装置が得られる。
【図面の簡単な説明】
第１図は本発明による半導体装置の要部拡大断面図，第
２図は従来の半導体装置の要部拡大断面図である。 １　・・・シリコン基板，　２　・・・アルミニウム配
線，　３　・・・酸化ケイ素膜，　４　・・・窒化ケイ
素膜。 特許出願人　松下電子工業株式会社

Claims (1)

    【特許請求の範囲】
  1. 　金属配線のワイヤボンディング部を開口する、２層以
    上の保護膜で覆われた半導体装置において、最上層の保
    護膜の開口部を、下層の保護膜の開口部より狭くし、下
    層の保護膜の端面を被覆したことを特徴とする半導体装
    置。
JP11427789A 1989-05-09 1989-05-09 半導体装置 Pending JPH02294037A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11427789A JPH02294037A (ja) 1989-05-09 1989-05-09 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11427789A JPH02294037A (ja) 1989-05-09 1989-05-09 半導体装置

Publications (1)

Publication Number Publication Date
JPH02294037A true JPH02294037A (ja) 1990-12-05

Family

ID=14633800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11427789A Pending JPH02294037A (ja) 1989-05-09 1989-05-09 半導体装置

Country Status (1)

Country Link
JP (1) JPH02294037A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4201792A1 (de) * 1991-01-29 1992-08-06 Mitsubishi Electric Corp Halbleitereinrichtung und verfahren zu deren herstellung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5891651A (ja) * 1981-11-26 1983-05-31 Seiko Epson Corp 半導体装置
JPS58116746A (ja) * 1982-10-13 1983-07-12 Toshiba Corp 半導体装置
JPS62224037A (ja) * 1986-03-26 1987-10-02 Nippon Denso Co Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5891651A (ja) * 1981-11-26 1983-05-31 Seiko Epson Corp 半導体装置
JPS58116746A (ja) * 1982-10-13 1983-07-12 Toshiba Corp 半導体装置
JPS62224037A (ja) * 1986-03-26 1987-10-02 Nippon Denso Co Ltd 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4201792A1 (de) * 1991-01-29 1992-08-06 Mitsubishi Electric Corp Halbleitereinrichtung und verfahren zu deren herstellung
DE4201792C2 (de) * 1991-01-29 1996-05-15 Mitsubishi Electric Corp Anschlußelektrodenstruktur und Verfahren zu deren Herstellung
US5525546A (en) * 1991-01-29 1996-06-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof

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