JPH02280316A - Pattern formation of integrated circuit - Google Patents
Pattern formation of integrated circuitInfo
- Publication number
- JPH02280316A JPH02280316A JP10222389A JP10222389A JPH02280316A JP H02280316 A JPH02280316 A JP H02280316A JP 10222389 A JP10222389 A JP 10222389A JP 10222389 A JP10222389 A JP 10222389A JP H02280316 A JPH02280316 A JP H02280316A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resist layer
- intermediate layer
- patterning
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007261 regionalization Effects 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000000059 patterning Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010985 leather Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
3産業上の利用分野]
この発明は、VLS Iのような集積回路のパターン形
成方法に関する。DETAILED DESCRIPTION OF THE INVENTION 3. INDUSTRIAL APPLICATION FIELD This invention relates to a method for patterning integrated circuits such as VLSI.
近年、集積回路の微細化が進むに連れてより細幅の配線
パターンを形成することが要望されるようになっており
、このような要望に応えうるパターン形成方法の1つと
して3層レジスト・プロセスといわれる方法が知られて
いる。In recent years, as the miniaturization of integrated circuits has progressed, there has been a demand for forming narrower wiring patterns, and three-layer resist is one of the pattern forming methods that can meet these demands. A method called process is known.
この3層レジスト・プロセスにおいては、まず、第2図
(a)で示すように、半導体基板1)f:覆うアルミニ
ウム(A1)などからなる被加工膜2上に下側レジスト
層3を塗布形成し、かつ、この下側レジスト層3上にス
ピンオングラス(SOG)などからなる中間層4を形成
したのち、この中間層4上に上側レジスト層5を塗布形
成する。そして、第2図(b)で示すように、電子ビー
ムや光、X線などを用いたりソグラフィによって上側レ
ジスト層5をパターニングしたうえ、第2図(c)で示
すように、上側レジストN5の残存部5aをマスクとす
る反応性イオンエツチング(以下、RYEという)など
によって中間層4をパターニングする。In this three-layer resist process, first, as shown in FIG. 2(a), a lower resist layer 3 is applied and formed on a processed film 2 made of aluminum (A1) or the like that covers the semiconductor substrate 1). Then, after forming an intermediate layer 4 made of spin-on glass (SOG) or the like on this lower resist layer 3, an upper resist layer 5 is formed by coating on this intermediate layer 4. Then, as shown in FIG. 2(b), the upper resist layer 5 is patterned using an electron beam, light, X-rays, etc. or by lithography, and as shown in FIG. 2(c), the upper resist layer 5 is patterned. The intermediate layer 4 is patterned by reactive ion etching (hereinafter referred to as RYE) using the remaining portion 5a as a mask.
つぎに、第2図(d)で示すように、中間層4の残存部
4aをマスクとして酸素(Ot )プラズマを用いるR
IF、などによって下側レジストN3をパターニングす
ると同時に、上側レジスト層5の残存部5aを除去する
。さらに、第2図(e)で示すように、下側レジスト層
3の残存部3a上に堆積した中間層4の残存部4aをR
TEなどによって除去したのち、第2図(f)で示すよ
うに、下側レジスト層3の残存部3aをマスクとするR
JEによって被加工膜2をパターニングする。Next, as shown in FIG. 2(d), using the remaining portion 4a of the intermediate layer 4 as a mask, an R
At the same time as patterning the lower resist N3 by IF or the like, the remaining portion 5a of the upper resist layer 5 is removed. Furthermore, as shown in FIG. 2(e), the remaining portion 4a of the intermediate layer 4 deposited on the remaining portion 3a of the lower resist layer 3 is
After removing by TE etc., as shown in FIG. 2(f), R is applied using the remaining portion 3a of the lower resist layer 3 as a mask.
The film to be processed 2 is patterned by JE.
ところで、前記従来のパターン形成方法においては、パ
ターニング工程が多いため、手間がかかるとともに、コ
ストアップを招いてしまうという不都合があった。However, in the conventional pattern forming method, since there are many patterning steps, there are disadvantages in that it is time-consuming and increases costs.
この発明は、このような不都合に鑑みて創案されたもの
であって、パターニング工程の省略を図ることが可能な
集積回路のパターン形成方法を提供することを目的とし
ている。The present invention was devised in view of the above-mentioned disadvantages, and an object of the present invention is to provide a method for forming a pattern for an integrated circuit, which allows the patterning process to be omitted.
この発明方法は、3Nレジスト・プロセスを用いる集積
回路のパターン形成方法であって、半導体基板もしくは
これを覆う被加工膜上に下側レジスト層を塗布形成し、
かつ、この下側レジスト層上に前記半導体基板もしくは
被加工膜と同一材料からなる中間層を堆積したのち、こ
の中間層上に上側レジスト層を塗布形成する工程と、前
記上側レジスト層をパターニングし、その残存部をマス
クとして前記中間層をパターニングしたのち、その残存
部をマスクとして下側レジスト層をパターニングすると
同時に、前記上側レジスト層の残存部を除去する工程と
、前記下側レジスト層の残存部をマスクとして前記半導
体基板もしくは被加工膜をパターニングすると同時に、
前記中間層の残存部を除去する工程とを含むことを特徴
とするものである。The method of the present invention is a method for patterning an integrated circuit using a 3N resist process, in which a lower resist layer is coated on a semiconductor substrate or a film to be processed covering the semiconductor substrate, and
Further, after depositing an intermediate layer made of the same material as the semiconductor substrate or the film to be processed on the lower resist layer, coating and forming an upper resist layer on the intermediate layer, and patterning the upper resist layer. , patterning the intermediate layer using the remaining portion as a mask, patterning the lower resist layer using the remaining portion as a mask, and simultaneously removing the remaining portion of the upper resist layer; At the same time, patterning the semiconductor substrate or the film to be processed using the mask as a mask,
The method is characterized in that it includes a step of removing a remaining portion of the intermediate layer.
上記方法によれば、あらかじめ半導体基板もしくは被加
工膜と同一材料からなる中間層を堆積しているので、半
4体基板もしくは被加工膜のパタニングと先にパターニ
ングされた中間層の残存部の除去とが同時に行われるこ
とになる。According to the above method, since the intermediate layer made of the same material as the semiconductor substrate or the film to be processed is deposited in advance, the half-quad substrate or the film to be processed is patterned and the remaining portion of the previously patterned intermediate layer is removed. will be done at the same time.
以下、この発明方法の一実施例を図面に基づいて説明す
る。An embodiment of the method of this invention will be described below with reference to the drawings.
第1図(a)〜(e)は、本発明方法による4J#1回
路のパターン形成手順を示す工程断面図である。FIGS. 1(a) to 1(e) are process cross-sectional views showing the pattern forming procedure of the 4J#1 circuit according to the method of the present invention.
なお、本実施例における手順は、その被加工膜と中間層
とが同一材料からなるものである点を除き、前述した従
来例と異ならないので、第1図(a)〜(e)において
第2[(a)〜(f)と互いに同一もしくは相当する部
分については同一符号を付している。The procedure in this example is the same as the conventional example described above, except that the film to be processed and the intermediate layer are made of the same material. 2 [The same or corresponding parts as in (a) to (f) are given the same reference numerals.
本実施例にかかる3Nレジスト・プロセスにおいては、
まず、第1図(a)で示すように、半導体基板1を覆う
アルミニウム(A1)などからなる被加工膜2上に下側
レジスト層3を塗布形成し、かつ、この下側レジスト層
3上に前記被加工膜と同一材料、すなわち、アルミニウ
ム(Afi)などからなる中間N4をスパッタリングや
革着などによって堆積したのち、この中間層4上に上側
レジスト層5を塗布形成する。In the 3N resist process according to this example,
First, as shown in FIG. 1(a), a lower resist layer 3 is coated and formed on a film to be processed 2 made of aluminum (A1) or the like that covers a semiconductor substrate 1, and a lower resist layer 3 is formed on the lower resist layer 3. After depositing an intermediate N4 made of the same material as the film to be processed, ie, aluminum (Afi) or the like by sputtering or leather coating, an upper resist layer 5 is formed on the intermediate layer 4 by coating.
そして、第1図(b)で示すように、電子ビームや光な
どを用いたりソグラフィによって上側レジスト層5をパ
ターニングしたのち、第1[1J(c)で示すように、
上側レジストWI5の残存部5aをマスクとするRIE
などによって中間層4をパターニングする。つぎに、第
1図(d)で示すように、中間層4の残存部4aをマス
クとして酸素(02)プラズマを用いるRTEなどによ
って下側レジスト層3をパターニングすると同時に、上
側レジスト層5の残存部5aを除去する。なお、ここま
での工程は、前述した従来例と同様である。Then, as shown in FIG. 1(b), after patterning the upper resist layer 5 using an electron beam, light, etc. or by lithography, the first resist layer 5 is patterned as shown in FIG. 1(c).
RIE using the remaining portion 5a of the upper resist WI5 as a mask
The intermediate layer 4 is patterned by et al. Next, as shown in FIG. 1(d), the lower resist layer 3 is patterned by RTE using oxygen (02) plasma using the remaining portion 4a of the intermediate layer 4 as a mask, and at the same time, the remaining portion 4a of the upper resist layer 5 is patterned. Remove portion 5a. Note that the steps up to this point are similar to those of the conventional example described above.
さらに、続いて、第1図(c)で示すように、下側レジ
スト層3の残存部3aをマスクとするRIEによって被
加工膜2をパターニングする。ところが、このとき、中
間層4が被加工膜2と同一材料、すなわち、アルミニウ
ム(AN)によって形成されていることから、先にパタ
ーニングされた中間層4の残存部4aが被加工膜2のパ
ターニングと同時に除去されることになる。したがって
、従来例における第2図(e)で示したように、下側レ
ジスト層3の残存部3a上に堆積した中間N4の残存部
4aをわざわざRIEなどによって除去しておく必要が
なくなる。Furthermore, as shown in FIG. 1(c), the film to be processed 2 is patterned by RIE using the remaining portion 3a of the lower resist layer 3 as a mask. However, at this time, since the intermediate layer 4 is made of the same material as the film to be processed 2, that is, aluminum (AN), the remaining portion 4a of the intermediate layer 4 that has been patterned earlier is not included in the patterning of the film to be processed 2. It will be removed at the same time. Therefore, as shown in FIG. 2(e) in the conventional example, there is no need to remove the remaining portion 4a of the intermediate N4 deposited on the remaining portion 3a of the lower resist layer 3 by RIE or the like.
なお、以上の説明においては、被加工膜2及び中間層4
がアルミニウム(Ajりであるものとしているが、これ
らの形成材料は1Mに限定されず、例えば、被加工11
92が酸化膜などである場合は中間層4も酸化膜などに
よって構成されることになる。また、本実施例では、半
導体基板lの被加工膜2をパターニングするものとして
説明したが、これに限定されるものではなく、例えば、
半導体基板lに素子分離用の溝、いわゆるトレンチを形
成する場合などにも本発明方法を適用することが可能で
あることはいうまでもない。In addition, in the above explanation, the processed film 2 and the intermediate layer 4
is assumed to be aluminum (Aj), but the material for forming these is not limited to 1M, for example, the material to be processed 11
When 92 is an oxide film or the like, the intermediate layer 4 is also formed of an oxide film or the like. Further, although this embodiment has been described as patterning the film to be processed 2 of the semiconductor substrate l, the invention is not limited to this, and for example,
It goes without saying that the method of the present invention can also be applied to cases where grooves for element isolation, so-called trenches, are formed in the semiconductor substrate l.
以上説明したように、この発明方法によれば、あらかじ
め半導体基板もしくはこれを覆う被加工膜と同一材料か
らなる中間層を堆積したうえ、半導体基板もしくは被加
工膜のパターニングと先にパターニングされた中間層の
残存部の除去とを同時に行うことになるので、従来例の
ように、中間層の残存部だけをわざわざ除去する必要が
なくなる結果、パターニング工程を省略することができ
る。したがって、これに要する手間を削減するとともに
、コストダウンを図ることができるという効果が得られ
る。As explained above, according to the method of the present invention, an intermediate layer made of the same material as the semiconductor substrate or the film to be processed covering it is deposited in advance, and then the semiconductor substrate or the film to be processed is patterned. Since the remaining portion of the layer is removed at the same time, there is no need to remove only the remaining portion of the intermediate layer as in the conventional example, and as a result, the patterning step can be omitted. Therefore, it is possible to reduce the time and effort required for this and also to reduce costs.
第1図(a)〜(e)は本発明方法による集積回路のパ
ターン形成手順を示す工程断面図であり、第2図(a)
〜(f)は従来方法による集積回路のパターン形成手順
を示す工程断面図である。
図における符号1は半導体基板、2は被加工膜、3は下
側レジスト層、3aはその残存部、4は中間層、4aは
その残存部、5は上側レジス1−Fl、5aはその残存
部である。
なお、図中の同一符号は、互いに同一もしくは相当する
部品、部分を示している。
第2図
(a)
(b)FIGS. 1(a) to 1(e) are process cross-sectional views showing the steps of patterning an integrated circuit according to the method of the present invention, and FIG. 2(a)
-(f) are process cross-sectional views showing the steps for forming a pattern of an integrated circuit according to a conventional method. In the figure, 1 is a semiconductor substrate, 2 is a film to be processed, 3 is a lower resist layer, 3a is its remaining part, 4 is an intermediate layer, 4a is its remaining part, 5 is an upper resist 1-Fl, 5a is its remaining part Department. Note that the same reference numerals in the drawings indicate parts and portions that are the same or correspond to each other. Figure 2 (a) (b)
Claims (1)
ーン形成方法であって、 半導体基板もしくはこれを覆う被加工膜上に下側レジス
ト層を塗布形成し、かつ、この下側レジスト層上に前記
半導体基板もしくは被加工膜と同一材料からなる中間層
を堆積したのち、この中間層上に上側レジスト層を塗布
形成する工程と、前記上側レジスト層をパターニングし
、その残存部をマスクとして前記中間層をパターニング
したのち、その残存部をマスクとして下側レジスト層を
パターニングすると同時に、前記上側レジスト層の残存
部を除去する工程と、 前記下側レジスト層の残存部をマスクとして前記半導体
基板もしくは被加工膜をパターニングすると同時に、前
記中間層の残存部を除去する工程とを含むことを特徴と
する集積回路のパターン形成方法。(1) A method for forming an integrated circuit pattern using a three-layer resist process, in which a lower resist layer is coated on a semiconductor substrate or a processed film covering the semiconductor substrate, and the above-mentioned After depositing an intermediate layer made of the same material as the semiconductor substrate or the film to be processed, a step of coating and forming an upper resist layer on the intermediate layer, and patterning the upper resist layer and using the remaining portion as a mask to form the intermediate layer. patterning, and then patterning the lower resist layer using the remaining portion as a mask, and simultaneously removing the remaining portion of the upper resist layer; and using the remaining portion of the lower resist layer as a mask, patterning the semiconductor substrate or the workpiece. A method for patterning an integrated circuit, comprising the step of patterning a film and simultaneously removing a remaining portion of the intermediate layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10222389A JPH02280316A (en) | 1989-04-20 | 1989-04-20 | Pattern formation of integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10222389A JPH02280316A (en) | 1989-04-20 | 1989-04-20 | Pattern formation of integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02280316A true JPH02280316A (en) | 1990-11-16 |
Family
ID=14321665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10222389A Pending JPH02280316A (en) | 1989-04-20 | 1989-04-20 | Pattern formation of integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02280316A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0792688A (en) * | 1990-02-26 | 1995-04-07 | Applied Materials Inc | Method of multilayer photoresist etching |
-
1989
- 1989-04-20 JP JP10222389A patent/JPH02280316A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0792688A (en) * | 1990-02-26 | 1995-04-07 | Applied Materials Inc | Method of multilayer photoresist etching |
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