JPH01295427A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01295427A JPH01295427A JP12616388A JP12616388A JPH01295427A JP H01295427 A JPH01295427 A JP H01295427A JP 12616388 A JP12616388 A JP 12616388A JP 12616388 A JP12616388 A JP 12616388A JP H01295427 A JPH01295427 A JP H01295427A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- thin film
- forming
- temperature
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010409 thin film Substances 0.000 claims abstract description 39
- 238000010438 heat treatment Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 12
- 238000010030 laminating Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 49
- 239000010410 layer Substances 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造技術に関し、特に半導体基
板上に積層された薄膜の熱処理技術に適用して有効な技
術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor devices, and in particular to a technology that is effective when applied to a heat treatment technology for thin films laminated on a semiconductor substrate.
半導体装置の製造工程では、熱酸化、CVD (che
mical vapor deposition)、P
V D (physicalvapor depos
ition) などの各種成膜技術や、不純物イオン
打ち込み/拡散などの技術を用いて半導体基板上に絶縁
膜、半導体膜、金属膜などの各種薄膜を形成し、これら
の薄膜を所定の形状にパターニングすることによって所
望する半導体集積回路が製造される。In the manufacturing process of semiconductor devices, thermal oxidation, CVD (che
vapor deposition), P
V D (physical vapor depos.
Forming various thin films such as insulating films, semiconductor films, and metal films on semiconductor substrates using various film formation technologies such as By doing so, a desired semiconductor integrated circuit is manufactured.
上記成膜技術ならびに不純物イオン打ち込み/拡散技術
については、例えば株式会社サイエンスフォーラム、昭
和58年11月28日発行、「超LSIハンドブックJ
P106〜P121に記載がある。Regarding the above-mentioned film formation technology and impurity ion implantation/diffusion technology, see, for example, Science Forum Co., Ltd., published November 28, 1980, "Very LSI Handbook J.
There is a description on pages P106 to P121.
半導体基板上に薄膜を形成する工程では、膜種や用途に
応じて異なった温度の熱処理が施され、また、その温度
範囲も常温から1000℃以上までの広範囲にわたって
いる。In the process of forming a thin film on a semiconductor substrate, heat treatment is performed at different temperatures depending on the film type and application, and the temperature range is wide ranging from room temperature to 1000° C. or higher.
ところが、薄膜を形成する工程毎に異なる温度の熱処理
が施されると、特に下層の薄膜の膜特性が熱処理の繰り
返しによっ〔変質し、デバイス特性が変動してしまうこ
とが体発明者によって見出された。However, the inventors have found that if heat treatment is performed at different temperatures in each step of forming a thin film, the film characteristics of the underlying thin film will change due to repeated heat treatments, causing device characteristics to fluctuate. Served.
とりわけ、各種薄膜の加工線幅が1μmあるいはそれ以
下の高密度高集積の半導体装置においては、熱処理の繰
り返しによって生ずる薄膜のストレス、薄膜中の不純物
プロファイルや結晶の変化などがデバイス特性に顕著な
影響を及ぼし、半導体装置の信頼性を低下させてしまう
ことになる。In particular, in high-density, highly integrated semiconductor devices where the processing line width of various thin films is 1 μm or less, stress in the thin film caused by repeated heat treatments, changes in impurity profiles and crystals in the thin film, etc. have a significant effect on device characteristics. This results in a decrease in the reliability of the semiconductor device.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、上層の薄膜形成時の熱処理に起因する
下層の薄膜の変質を有効に防止することができる技術を
提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can effectively prevent deterioration of the lower layer thin film due to heat treatment during the formation of the upper layer thin film. It is in.
本発明の前記並びにその他の目的と新規な特徴は、本明
細書の記述および添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基板上に複数の薄膜を順次積層して所
定の集積回路を形成する際、上層の薄膜を形成する工程
の最終熱処理を下層の薄膜を形成する工程の最終熱処理
よりも順次低い温度条件で行うものである。That is, when a predetermined integrated circuit is formed by sequentially stacking a plurality of thin films on a semiconductor substrate, the final heat treatment in the step of forming the upper thin film is performed at a lower temperature than the final heat treatment in the step of forming the lower thin film. This is done in
所定の温度で熱処理が施された薄膜の膜特性は、その後
、その温度以下で熱処理を行ってもほとんど変化するこ
とがない。The film characteristics of a thin film that has been heat-treated at a predetermined temperature will hardly change even if it is subsequently heat-treated at a temperature below that temperature.
そこで、半導体基板上に各種薄膜を順次積層する際、各
薄膜形成工程の最終熱処理温度を、その薄膜より下層の
薄膜の最終熱処理温度よりも低くすることにより、各薄
膜の変質が有効に防止される。Therefore, when various thin films are sequentially laminated on a semiconductor substrate, deterioration of each thin film can be effectively prevented by setting the final heat treatment temperature of each thin film forming process lower than the final heat treatment temperature of the thin film below the thin film. Ru.
第1図(a)〜(e)は、本発明の一実施例である半導
体装置の製造方法を示す半導体基板の要部断面図である
。FIGS. 1(a) to 1(e) are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
本実施例は、MOS−FETの製造方法に適用されたも
のであり、以下、その製造方法を工程順に説明する。This example is applied to a method of manufacturing a MOS-FET, and the manufacturing method will be explained below in order of steps.
まず、p形シリコン単結晶からなる基板1の主面に5i
ns膜2とSI3N4膜3とを被着した後、ホトレジス
トをマスクに用いてエツチングを行い、後にトランジス
タが形成される領域にS+aNa膜3を残す。First, 5i
After depositing the ns film 2 and the SI3N4 film 3, etching is performed using a photoresist as a mask, leaving the S+aNa film 3 in a region where a transistor will be formed later.
次いで、基板10表面からホウ素(B)イオンを打ち込
んでチャネルストッパ領域4を形成した後、基板1を湿
式酸化して素子分離用のフィールド酸化膜5を形成する
(第1図(a))。Next, boron (B) ions are implanted from the surface of the substrate 10 to form a channel stopper region 4, and then the substrate 1 is wet-oxidized to form a field oxide film 5 for element isolation (FIG. 1(a)).
次に、基板1の表面のShow膜2と513N4膜3と
をエツチングで除去した後、フィールド酸化膜5で囲ま
れたトランジスタ形成領域の表面に乾式法、またはHC
I酸化法を用いてゲート酸化膜6を形成する。Next, after removing the show film 2 and 513N4 film 3 on the surface of the substrate 1 by etching, the surface of the transistor formation region surrounded by the field oxide film 5 is etched using a dry method or HC.
A gate oxide film 6 is formed using the I oxidation method.
ここで、上記ゲート酸化膜6を形成する際の熱処理温度
T1 は、1000℃前後である。Here, the heat treatment temperature T1 when forming the gate oxide film 6 is approximately 1000°C.
次に、S+Ha などの反応ガスを用いた熱CVD法で
基板1の表面にポリシリコン膜7を被着する(第1図ら
))。なお、この熱CVD工程の温度条件は、例えば5
50〜650℃である。Next, a polysilicon film 7 is deposited on the surface of the substrate 1 by a thermal CVD method using a reactive gas such as S+Ha (FIGS. 1 and 7). Note that the temperature conditions for this thermal CVD step are, for example, 5.
The temperature is 50-650°C.
次に、上記ポリシリコン膜7に導電性を付与するため、
例えば102I10ffl程度のリン(P)を添加する
。Next, in order to impart conductivity to the polysilicon film 7,
For example, about 10 ffl of phosphorus (P) is added.
このときの熱処理温度T2 は、1000℃前後である
が、下層に形成されたゲート酸化膜6の変質を抑制する
ため、ゲート酸化膜6を形成した際の熱処理温度TI
よりも低温にする。The heat treatment temperature T2 at this time is around 1000°C, but in order to suppress the deterioration of the gate oxide film 6 formed in the lower layer, the heat treatment temperature T2 when forming the gate oxide film 6 is
lower temperature than
次に、CVD法を用いて基板1の表面にMo51、ある
いはW S i 2などのシリサイド膜8を被着する。Next, a silicide film 8 such as Mo51 or W Si 2 is deposited on the surface of the substrate 1 using the CVD method.
このCVD工程の温度条件は、例えば300〜500℃
である。The temperature conditions for this CVD process are, for example, 300 to 500°C.
It is.
次に、上記シリサイド膜8の膜質を安定化するため、熱
処理を行う。このときの熱処理温度T。Next, heat treatment is performed to stabilize the quality of the silicide film 8. The heat treatment temperature T at this time.
は、下層のゲート酸化膜6やポリシリコン膜7の変質を
抑制する必要上、前記リン処理の際の熱処理温度T2
よりも低温(例えば、950℃前後)にする。In order to suppress deterioration of the underlying gate oxide film 6 and polysilicon film 7, the heat treatment temperature T2 during the phosphorus treatment is
(for example, around 950°C).
次に、ホトレジストをマスクに用いて上記ポリシリコン
膜7とシリサイド膜8とをエツチングし、ポリシリコン
膜7とシリサイド膜8との二層からなるポリサイド構造
のゲート電極9を形成する(第1図(C))。Next, the polysilicon film 7 and the silicide film 8 are etched using a photoresist as a mask to form a gate electrode 9 having a polycide structure consisting of two layers of the polysilicon film 7 and the silicide film 8 (see FIG. 1). (C)).
次に、ゲート電極9をマスクに用いて基板lの表面から
リンイオンなどを打ち込み、ゲート電極90両側の基板
1に低濃度拡散領域10を形成した後、CVD法を用い
て基板1の表面にSiO2膜を被着する。このCVD工
程の温度条件は、例えば700〜750℃である。Next, using the gate electrode 9 as a mask, phosphorus ions or the like are implanted from the surface of the substrate 1 to form low concentration diffusion regions 10 in the substrate 1 on both sides of the gate electrode 90. Deposit the membrane. The temperature conditions for this CVD step are, for example, 700 to 750°C.
次に、上記SiO2膜を、例えば反応性イオンエツチン
グ(RIE)などの異方性エツチングを利用したエッチ
バック法で加工することによってゲート電極9の側壁に
スペーサ11を形成し、次いで、このスペーサ11の膜
質を安定化するため、熱処理を行う。Next, the SiO2 film is processed by an etch-back method using anisotropic etching such as reactive ion etching (RIE) to form a spacer 11 on the side wall of the gate electrode 9. Heat treatment is performed to stabilize the film quality.
このときの熱処理温度T4は、ゲート酸化膜6やゲート
電極9の変質を抑制する必要上、前記シリサイド膜8の
熱処理温度T、よりも低温(例えば、920〜930℃
程度)にする。The heat treatment temperature T4 at this time is lower than the heat treatment temperature T of the silicide film 8 (for example, 920 to 930°C
degree).
次に、ゲート電極9とその側壁のスペーサ11とをマス
クに用いて基板10表面にヒ素(As)イオンなどを打
ち込み、ゲート電極9の両側に高濃度拡散領域12を形
成した後、CVD法を用いて基板lの表面にリンケイ酸
ガラス(PSG)などからなる層間絶縁膜13を被着す
る(第1図(d))。このCVD工程の温度条件は、例
えば350〜450℃である。Next, using the gate electrode 9 and the spacer 11 on its side wall as a mask, arsenic (As) ions or the like are implanted into the surface of the substrate 10 to form high concentration diffusion regions 12 on both sides of the gate electrode 9, and then a CVD method is performed. An interlayer insulating film 13 made of phosphosilicate glass (PSG) or the like is deposited on the surface of the substrate 1 using a method (FIG. 1(d)). The temperature conditions for this CVD step are, for example, 350 to 450°C.
次に、基板1をリフロー炉内で加熱して上記層間絶縁膜
13を平坦化する。このときの熱処理温度T、は、下層
のゲート酸化WX6、ゲート電極9およびスペーサ11
の変質を抑制する必要上、スペーサ11の熱処理温度T
4よりも低温(例えば、900℃前後)にする。Next, the substrate 1 is heated in a reflow oven to planarize the interlayer insulating film 13. The heat treatment temperature T at this time is the lower layer gate oxidation WX6, the gate electrode 9 and the spacer 11.
Due to the need to suppress the deterioration of the spacer 11, the heat treatment temperature T of the spacer 11 is
4 (for example, around 900°C).
次に、平坦化された層間絶縁膜13の所定箇所を孔開け
してコンタクトホール14を形成した後、基板1の表面
にスパッタ法を用いてAIl膜を被着する。このスバツ
タ工程の温度条件は、例えば350℃前後である。Next, contact holes 14 are formed by drilling at predetermined locations in the planarized interlayer insulating film 13, and then an Al film is deposited on the surface of the substrate 1 by sputtering. The temperature conditions for this sputtering process are, for example, around 350°C.
次に、上記Al膜をエツチングで加工してAl配線15
を形成した後、還元性雰囲気中において熱処理温度TI
=400〜500℃で熱処理を行い、コンタクトホール
14を介して接続されたAl配線15と高濃度拡散領域
12との接合安定化を図る。Next, the Al film is etched to form the Al wiring 15.
After forming, heat treatment temperature TI is applied in a reducing atmosphere.
A heat treatment is performed at a temperature of 400 to 500° C. to stabilize the bond between the Al wiring 15 and the high concentration diffusion region 12 connected through the contact hole 14.
最後に、CVD法を用いて基板1の表面に3102から
なるパッシベーション膜16を被着した後、所定箇所を
孔開けして電極パッド(図示せず)を形成することによ
り、MOS−FETが完成する(第1図(e))。Finally, after depositing a passivation film 16 made of 3102 on the surface of the substrate 1 using the CVD method, holes are formed at predetermined locations to form electrode pads (not shown), thereby completing the MOS-FET. (Figure 1(e)).
以上の工程からなる本実施例においては、基板1の表面
に下層から順次、ゲート酸化膜6、ゲート電極9、スペ
ーサ11、層間絶縁膜13およびAl配線15を積層し
てMOS−FETを形成する際、各薄膜形成工程の最終
熱処理温度(T、〜Ts)を次第に低くしたので、熱処
理の繰り返しによる各薄膜の変質が有効に防止され、信
頼性の高いMOS−FETが得られる。In this embodiment, which consists of the above steps, a MOS-FET is formed by sequentially stacking a gate oxide film 6, a gate electrode 9, a spacer 11, an interlayer insulating film 13, and an Al wiring 15 on the surface of the substrate 1 from the bottom layer. In this case, since the final heat treatment temperature (T, ~Ts) of each thin film forming step was gradually lowered, deterioration of each thin film due to repeated heat treatments is effectively prevented, and a highly reliable MOS-FET can be obtained.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は、前記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
例えば、前記実施例では、MOS−FETの製造方法に
適用した場合について説明したが、これに限定されるも
のではなく、バイポーラ形半導体装置など、各種半導体
装置の製造方法に適用することができる。For example, in the embodiment described above, the case where the present invention is applied to a method of manufacturing a MOS-FET has been described, but the present invention is not limited to this, and can be applied to a method of manufacturing various semiconductor devices such as a bipolar type semiconductor device.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、半導体基板上に複数の薄膜を順次積層して所
定の集積回路を形成する際、上層の薄膜を形成する工程
の最終熱処理温度を下層の薄膜を形成する工程の最終熱
処理温度よりも順次低くすることにより、上層の薄膜を
形成する際の熱処理に起因する下層の薄膜の変質が有効
に防止され、信頼性の高い半導体装置が得られる。That is, when forming a predetermined integrated circuit by sequentially stacking a plurality of thin films on a semiconductor substrate, the final heat treatment temperature in the step of forming the upper layer thin film is successively lower than the final heat treatment temperature in the step of forming the lower layer thin film. By doing so, deterioration of the lower thin film due to heat treatment during formation of the upper thin film can be effectively prevented, and a highly reliable semiconductor device can be obtained.
第1図(a)〜(e)は本発明の一実施例である半導体
装置の製造方法を示す半導体基板の要部断面図である。
1・・・半導体基板、2・・・SiO2膜、3・・・5
13N4膜、4・・・チャネルストッパ領域、5・・・
フィールド酸化膜、6・・・ゲート酸化膜、7・・・ポ
リンリコン膜、8・・・ンIJサイド膜、9・・・ゲー
ト電極、10・・・低濃度拡散領域、11・・・スペー
サ、12・・・高濃度拡散領域、13・・・層間絶縁膜
、14・・・コンタクトホール、15・・・Al配線、
16・・・パッシベーション膜。
代理人 弁理士 筒 井 大 和
第1図FIGS. 1(a) to 1(e) are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1... Semiconductor substrate, 2... SiO2 film, 3...5
13N4 film, 4... channel stopper region, 5...
Field oxide film, 6... Gate oxide film, 7... Polyrecon film, 8... N-IJ side film, 9... Gate electrode, 10... Low concentration diffusion region, 11... Spacer, 12...High concentration diffusion region, 13...Interlayer insulating film, 14...Contact hole, 15...Al wiring,
16... Passivation film. Agent Patent Attorney Daiwa Tsutsui Figure 1
Claims (1)
積回路を形成する際、上層の薄膜を形成する工程の最終
熱処理温度を、下層の薄膜を形成する工程の最終熱処理
温度よりも順次低くすることを特徴とする半導体装置の
製造方法。1. When forming a predetermined integrated circuit by sequentially laminating multiple thin films on a semiconductor substrate, the final heat treatment temperature in the process of forming the upper layer thin film is set to be lower than the final heat treatment temperature in the process of forming the lower layer thin film. A method of manufacturing a semiconductor device, characterized in that the manufacturing method of the semiconductor device is made low.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12616388A JPH01295427A (en) | 1988-05-24 | 1988-05-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12616388A JPH01295427A (en) | 1988-05-24 | 1988-05-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01295427A true JPH01295427A (en) | 1989-11-29 |
Family
ID=14928237
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12616388A Pending JPH01295427A (en) | 1988-05-24 | 1988-05-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01295427A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094392A (en) * | 2007-10-11 | 2009-04-30 | Mitsubishi Electric Corp | Method for manufacturing silicon carbide semiconductor device |
JP2010068008A (en) * | 2009-12-24 | 2010-03-25 | Mitsubishi Electric Corp | Method of manufacturing silicon carbide schottky barrier diode |
-
1988
- 1988-05-24 JP JP12616388A patent/JPH01295427A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009094392A (en) * | 2007-10-11 | 2009-04-30 | Mitsubishi Electric Corp | Method for manufacturing silicon carbide semiconductor device |
US8377811B2 (en) | 2007-10-11 | 2013-02-19 | Mitsubishi Electric Corporation | Method for manufacturing silicon carbide semiconductor device |
JP2010068008A (en) * | 2009-12-24 | 2010-03-25 | Mitsubishi Electric Corp | Method of manufacturing silicon carbide schottky barrier diode |
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