JPH02237026A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02237026A JPH02237026A JP5757189A JP5757189A JPH02237026A JP H02237026 A JPH02237026 A JP H02237026A JP 5757189 A JP5757189 A JP 5757189A JP 5757189 A JP5757189 A JP 5757189A JP H02237026 A JPH02237026 A JP H02237026A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- high melting
- films
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 230000008018 melting Effects 0.000 claims abstract description 29
- 238000002844 melting Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 230000001678 irradiating effect Effects 0.000 claims description 6
- 230000006866 deterioration Effects 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 7
- 229910008479 TiSi2 Inorganic materials 0.000 abstract 3
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 11
- 239000010936 titanium Substances 0.000 description 11
- 229910008484 TiSi Inorganic materials 0.000 description 10
- 239000012535 impurity Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置の製造方法に関し、更に詳し《は
、配線のコンタクト部に高融点金属シリサイド膜と高融
点金属窒化物膜との二層構造の膜を有する半導体装置の
製造方法に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device. The present invention relates to a method of manufacturing a semiconductor device having a layered film.
［発明の概要］
本発明は、高融点金属シリサイド膜と、該高融点金属シ
リサイド膜上に形成された高融点金属窒化物膜とを有す
る半導体装置の製造方法において、Ｎ（窒素）を含む雰
囲気中で前記高融点金属シリサイド膜に、エネルギー密
度１４００〜２２０Ｑ ｍ Ｊ ／ ｃ ｍ ’のレー
ザビームを選択的に照射することにより前記高融点金属
窒化物膜を形成するようにしたことにより、
接合リーク電流，コンタクト抵抗及びシート抵抗を低く
するようにしたのもである。[Summary of the Invention] The present invention provides a method for manufacturing a semiconductor device having a high melting point metal silicide film and a high melting point metal nitride film formed on the high melting point metal silicide film. In this method, the high melting point metal nitride film is formed by selectively irradiating the high melting point metal silicide film with a laser beam having an energy density of 1400 to 220 Q m J/cm', thereby reducing junction leakage. It is designed to reduce current, contact resistance, and sheet resistance.
［従来の技術］
半導体装置においては、半導体基板中に形成された拡散
層に、層間絶縁膜に形成されたコンタクトホールを通じ
てアルミニウム（Ａ１）の配線がコンタクトしている。[Prior Art] In a semiconductor device, aluminum (A1) wiring contacts a diffusion layer formed in a semiconductor substrate through a contact hole formed in an interlayer insulating film.
従来、この拡散層のシート抵抗の低減及びＡＩ配線とこ
の拡散層との反応防止、（図るために、例えばチタンシ
リサイド（ＴｉＳｔ，）膜とその上に形成された窒化チ
タン（ＴｉＮ）ＷＪとの二層構造の膜を介してＡＩ配線
を拡散層にコンタクトさせる技術が知られている。Conventionally, in order to reduce the sheet resistance of this diffusion layer and prevent the reaction between AI wiring and this diffusion layer, for example, a titanium silicide (TiSt) film and a titanium nitride (TiN) WJ formed thereon have been used. A technique is known in which an AI wiring is brought into contact with a diffusion layer through a two-layered film.
特開昭６２−１６９４１２号公報には、このＴｉｓｉｚ
膜上にＴｉＮ膜を形成する方法として、拡散層上にＴｉ
Ｓｉ＊膜を形成した後に、窒素（Ｎ）を含む雰囲気中に
おいて９００℃以上の高温でアニールを行ってこのＴｉ
Ｓｉ，膜の表面を窒化することによりＴｉＮ膜を形成す
る方法が開示されている。JP-A-62-169412 describes this Tisiz
As a method of forming a TiN film on a film, TiN film is formed on a diffusion layer.
After forming the Si* film, annealing is performed at a high temperature of 900°C or higher in an atmosphere containing nitrogen (N) to remove this Ti film.
A method of forming a TiN film by nitriding the surface of the Si film is disclosed.
［発明が解決しようとする課題］
しかしながら、上述の特開昭６２−１６９４ １２号公
報に開示された方法は、半導体基板全体が９００℃以上
の高温に加熱されることに起因して、窒化されない部分
におけるＴｉＳｉ，膜の表面のモフォロジ−（ｍｏｒｐ
ｈｏｌｏｇｙ）が劣化し、その結果、電気的特性の劣化
が生じてしまうという問題点があった。また、特に、近
年素子の微細化に伴ってソース・ドレイン領域の深さ寸
法（Ｘ，）が浅くなっているため、このように半導体基
板全体が高温に加熱されることにより、拡散層中の不純
物の再拡散が生じて拡散層が広がってしまうという問題
もあった。[Problems to be Solved by the Invention] However, in the method disclosed in the above-mentioned Japanese Patent Application Laid-open No. 1694-12-1983, the entire semiconductor substrate is heated to a high temperature of 900° C. or higher, and therefore, it is not nitrided. The morphology of the surface of the TiSi film in the part
There was a problem in that the electrical characteristics deteriorated as a result of the deterioration of the electrical characteristics. In addition, in particular, as the depth dimension (X,) of the source/drain region has become shallower with the miniaturization of devices in recent years, the entire semiconductor substrate is heated to high temperatures, causing There was also the problem that impurity re-diffusion occurred and the diffusion layer expanded.
本発明は、このような従来の問題点に着目して創案され
たものであって、高融点金属シリサイド膜のモフォロジ
ーの劣化や不純物の再拡散を生じることなく高融点金属
窒化物膜を高融点金属シリサイド膜上に形成可能とする
と共に、接合リーク電流，コンタクト抵抗及びシート抵
抗を低減化させることを可能にする半導体装置の製造方
法を得んとするものである。The present invention was devised by focusing on such conventional problems, and it is possible to convert a high melting point metal nitride film to a high melting point without causing deterioration of the morphology of the high melting point metal silicide film or re-diffusion of impurities. The present invention aims to provide a method for manufacturing a semiconductor device that can be formed on a metal silicide film and that can reduce junction leakage current, contact resistance, and sheet resistance.
［課題を解決するための手段］
そこで、本発明は、高融点金属シリサイド膜と、該高融
点金属シリサイド膜上に形成された高融点金属窒化物膜
とを有する半導体装置の製造方法において、Ｎ（窒素）
を含む雰囲気中で前記高融点金属シリサイド膜に、エネ
ルギー密度１４００〜２ ２ ０ ０ ｍ Ｊ ／ ｃ
ｍ冨のレーザビームを選択的に照射することにより前
記高融点金属窒化物膜を形成するようにしたことを、そ
の解決手段としている。[Means for Solving the Problems] Therefore, the present invention provides a method for manufacturing a semiconductor device having a high melting point metal silicide film and a high melting point metal nitride film formed on the high melting point metal silicide film. (nitrogen)
The high melting point metal silicide film has an energy density of 1400 to 2200 mJ/c in an atmosphere containing
The solution is to form the high melting point metal nitride film by selectively irradiating the laser beam with m-thickness.
［作用］
Ｎを含む雰囲気中で、レーザピームを選択的に照射する
ことにより、高融点金属シリサイド膜の窒化を行うべき
部分のみが局所的に高温に加熱されてこの部分に高融点
金属窒化物膜が形成されるが、その他の部分は高温に加
熱されない。このため、この窒化が行われない部分にお
ける高融点金属シリサイド膜の表面のモフォロジーの劣
化や不純物の再拡散が生じるのを防止することが可能と
なる。また、レーザビームのエネルギー密度を１４００
〜２ ２ ０ ０ ｍ Ｊ ／ ｃ ｍ倉とすることに
より、コンタクト抵抗，シート抵抗及びリーク電流を低
く保つことが可能となる。[Operation] By selectively irradiating the laser beam in an atmosphere containing N, only the part of the high melting point metal silicide film to be nitrided is locally heated to a high temperature, and the high melting point metal nitride film is formed in this part. is formed, but other parts are not heated to high temperatures. Therefore, it is possible to prevent deterioration of the morphology of the surface of the high melting point metal silicide film and re-diffusion of impurities in the portions where this nitridation is not performed. In addition, the energy density of the laser beam was increased to 1400
By setting the resistance to ~2200 mJ/cm, it is possible to keep contact resistance, sheet resistance, and leakage current low.
［実施例］
以下、本発明に係る半導体装置の製造方法の詳細を図面
に示す実施例に基づいて説明する。この実施例は、本発
明をＭＯＳトランジスタの製造に適用した実施例である
。[Example] Hereinafter, details of a method for manufacturing a semiconductor device according to the present invention will be described based on an example shown in the drawings. This example is an example in which the present invention is applied to manufacturing a MOS transistor.
第ｌ図Ａ〜第１図トＩは、本実施例の製造方法の工程を
示す断面図である。FIGS. 1A to 1I are cross-sectional views showing the steps of the manufacturing method of this embodiment.
本実施例においては、第ｌ図Ａに示すように、例えばｐ
型のシリコン基板である半導体基板１の表面に例えばＳ
ｉＯ，膜のようなフィールド絶縁膜２を選択的に形成し
て素子間分離を行った後、このフィールド絶縁膜２で囲
まれた活性領域の表面に例えば熱酸化により例えばＳｉ
Ｏ！膜のようなゲート絶縁ＭＪ３を形成する。次に、こ
のゲート絶縁膜３上に例えば不純物をドープした多結晶
Ｓｉ膜を形成した後、これらの多結晶Ｓｉ膜及びゲート
絶縁膜３をエッチングにより所定形状にパターンニング
する。これによって、ゲート電極４が形成される。この
後、このゲート電極４をマスクとして半導体基板１中に
例えばリン（Ｐ）のようなｎ型不純物を低濃度にイオン
注入する。次に、例えばＣＶＤにより全面に例えばＳｉ
Ｏ，膜を形成した後、例えば反応性イオンエッチング（
ＲｌＥ）によりこのＳｉｎ．膜を基板表面と垂直方向に
異方性エッチングしてＳｉｎ，から成る側壁（サイドウ
ォールスペーサ）５を形成する。次に、この側壁５をマ
スクとして半導体甚板１中に例えばヒ素（Ａｓ）のよう
なｎ型不純物を比較的高濃度にイオン注入する。これに
よって、例えばｎ０型のソース領域６及びドレイン領域
７がゲート電極４に対して自己整合的に形成される。こ
れらのゲート電極４、ソース領域６及びドレイン領域７
により、ｎチャンネルＭＯＳＦＥＴが構成される。In this embodiment, as shown in FIG.
For example, S is applied to the surface of the semiconductor substrate 1, which is a type of silicon substrate.
After selectively forming a field insulating film 2 such as an iO, film to perform element isolation, the surface of the active region surrounded by this field insulating film 2 is coated with, for example, Si by thermal oxidation.
O! A film-like gate insulator MJ3 is formed. Next, a polycrystalline Si film doped with impurities, for example, is formed on the gate insulating film 3, and then the polycrystalline Si film and the gate insulating film 3 are patterned into a predetermined shape by etching. As a result, gate electrode 4 is formed. Thereafter, using the gate electrode 4 as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 at a low concentration. Next, the entire surface is coated with, for example, Si by, for example, CVD.
O, after forming the film, for example, reactive ion etching (
RlE), this Sin. The film is anisotropically etched in a direction perpendicular to the substrate surface to form sidewalls (sidewall spacers) 5 made of Sin. Next, using this side wall 5 as a mask, an n-type impurity such as arsenic (As) is ion-implanted into the semiconductor substrate 1 at a relatively high concentration. As a result, for example, an n0 type source region 6 and drain region 7 are formed in a self-aligned manner with respect to the gate electrode 4. These gate electrode 4, source region 6 and drain region 7
Thus, an n-channel MOSFET is configured.
これらのソース領域６及びドレイン領域７は、側壁５の
下方の部分に例えばｎ一型の低不純物濃度部６ａ，７ａ
を有しており、従ってこのｎチャンネルＭＯＳＦＥＴは
この低不純物濃度部７ａによりドレイン領域７の近傍の
電界を緩和した、いわゆるＬ Ｄ Ｄ （Ｌｉｇｈｔｌ
ｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造を有する。なお、こ
のｎチャンネルＭＯＳＦＥＴは必ずしもＬＤＤ構造を有
する必要はない。この後、アニールを行うζとにより、
イオン注入された不純物の電気的活性化を行う。These source regions 6 and drain regions 7 are provided with low impurity concentration regions 6a, 7a of n-type, for example, in the lower part of the sidewall 5.
Therefore, this n-channel MOSFET has a so-called LDD (Lightl
y Doped Drain) structure. Note that this n-channel MOSFET does not necessarily have to have an LDD structure. After this, by annealing ζ,
The ion-implanted impurities are electrically activated.
次に第１図Ｂに示すように、例えばスパッタや蒸着によ
り全面チタン（Ｔｉ）膜８を形成する。Next, as shown in FIG. 1B, a titanium (Ti) film 8 is formed on the entire surface by, for example, sputtering or vapor deposition.
次に、例えば８００℃程度の温度でアニールを行うこと
により、Ｔｉ膜８とこのＴｉ膜８が直接接しているゲー
ト電極４、ソース領域６及びドレイン領域７とを反応さ
せる。これによって、これらのゲート電極４、ソース領
域６及びドレイン領域７の表面がシリサイド化される。Next, by performing annealing at a temperature of about 800° C., for example, the Ti film 8 is reacted with the gate electrode 4, source region 6, and drain region 7 with which the Ti film 8 is in direct contact. As a result, the surfaces of gate electrode 4, source region 6, and drain region 7 are silicided.
この後、未反応のＴｉ膜８をエッチング除去する。この
ようにして、第１図Ｃに示すように、ゲート電極４、ソ
ース領域６及びドレイン領域７の表面にそれぞれＴｉＳ
ｉ．膜９ａ〜９Ｃが形成される。これらのＴｉＳｉ．膜
９ａ〜９Ｃの膜厚は例えば１０００人程度である。これ
らのＴｉＳｉ．膜９ａ〜９Ｃにより、ゲート電極４、ソ
ース領域６及びドレイン領域７のシート抵抗の低減を図
ることができる。Thereafter, the unreacted Ti film 8 is removed by etching. In this way, as shown in FIG.
i. Films 9a-9C are formed. These TiSi. The thickness of the films 9a to 9C is, for example, about 1000. These TiSi. The films 9a to 9C can reduce the sheet resistance of the gate electrode 4, source region 6, and drain region 7.
なお、上述のアニールは例えば赤外線（ＩＲ）アニール
により行うことも可能である。Note that the above-mentioned annealing can also be performed by, for example, infrared (IR) annealing.
次に第１図Ｄに示すように、例えばＣＶＤにより全面に
例えばリンシリケートガラス（ＰＳＧ）膜のような層間
絶縁膜１０を形成し、さらにこの層間絶縁膜１０の上に
例えばスパッタや蒸膜により例えばＡＩ膜のような後述
のレーザビームＢに対する反射膜ｌ１を形成した後、リ
ソグラフィーによりこの反射膜１１の上に所定形状のレ
ジストパターンｌ２を形成する。Next, as shown in FIG. 1D, an interlayer insulating film 10 such as a phosphosilicate glass (PSG) film is formed on the entire surface by, for example, CVD, and then an interlayer insulating film 10 such as a phosphosilicate glass (PSG) film is formed on the interlayer insulating film 10 by, for example, sputtering or vapor deposition. After forming a reflective film l1 such as an AI film for the laser beam B, which will be described later, a resist pattern l2 of a predetermined shape is formed on the reflective film 11 by lithography.
次に、このレジストパターンｌ２をマスクとして反射膜
】１及び層間絶縁膜１０の所定部分を例えばＲＩＥによ
りエッチングして、第１図Ｅに示すようにコンタクトホ
ールＣ，−Ｃ．を形成する。Next, using the resist pattern 12 as a mask, predetermined portions of the reflective film 1 and the interlayer insulating film 10 are etched by, for example, RIE to form contact holes C, -C and the like, as shown in FIG. 1E. form.
この後、レジストパターン１２を除去する。After this, the resist pattern 12 is removed.
次に第１図Ｆに示すように、Ｎを含む雰囲気、例えばＮ
，ガスやアンモニア（Ｎ Ｈ ｓ）ガス中（７０ＱｍＴ
ｏｒｒ）で全面にレーザビームＢを照射する。このレー
ザビームＢとしては、例えばＸｅＣｌエキシマーレーザ
のようなエキシマーレーザによるパルスレーザビーム（
波＆３ ０ ８ ｎ ｍ） ヲ用いることができる。こ
の場合、レーザビームＢの照射エネルギー密度は１４０
０〜２２００ｍＪ／ ｃ ｍ ”に設定する。そして、
反射膜ｌ１に入射したレーザビームＢは反射されるため
、結果的に反射膜１１で覆われていないコンタクトホー
ルＣ，−Ｃ．内部のＴ ＋ Ｓ ｒ ＊膜９ａ〜９ｃに
のみレ−ｆビ−ＡＢが照射される一このレーザビームＢ
の照射によってコンタクトホールＣＩ〜Ｃ３内部のＴｉ
Ｓｉ，膜９ａ〜９ｃのみが局所的に高温に加熱され、こ
の部分がレーザビームＢの照射により分解された雰囲気
ガス中のＮによって所定深さまで窒化される。これによ
って、ＴｉＮ膜１３ａ〜１３ｃがコンタクトホールＣ１
〜Ｃ３に対して自己整合的に形成される。これらのＴｉ
Ｎ膜１３ａ〜１３ｃによって、後述の配線１４ａ−１４
ｃとゲート電極４、ソース領域６及びドレイン領域７と
の反応を防止することができる。なお、この反応を効果
的に防止するためには、これらのＴｉＮ膜１３ａ〜１３
ｃの厚さは例えば５００人程度以上であるのが好ましい
。Next, as shown in FIG. 1F, an atmosphere containing N, for example, N
, gas or ammonia (NHs) gas (70QmT
orr) to irradiate the entire surface with laser beam B. As this laser beam B, for example, a pulsed laser beam (
Waves & 308 nm) can be used. In this case, the irradiation energy density of laser beam B is 140
Set to 0~2200mJ/cm''.And,
Since the laser beam B incident on the reflective film l1 is reflected, the contact holes C, -C. Only the internal T + S r * films 9a to 9c are irradiated with laser beam B.
By irradiating Ti inside contact holes CI to C3,
Only the Si films 9a to 9c are locally heated to a high temperature, and this portion is nitrided to a predetermined depth by N in the atmospheric gas decomposed by the laser beam B irradiation. As a result, the TiN films 13a to 13c are connected to the contact hole C1.
~C3 is formed in a self-aligned manner. These Ti
By the N films 13a to 13c, wirings 14a to 14, which will be described later, are connected.
Reactions between C and the gate electrode 4, source region 6, and drain region 7 can be prevented. Note that in order to effectively prevent this reaction, these TiN films 13a to 13
The thickness of c is preferably about 500 or more, for example.
次に、例えばスパッタや蒸着により全面に例えば．Ａ
Ｊ膜を形成した後、このＡＩ膜をエッチングにより所定
形状にパターンニングして第１１！！ａＨに示すように
配線１４８〜１４ｃを形成し、これによって目的とする
ＭＯＳＬＳＩを完成させる。Next, for example, the entire surface is coated by sputtering or vapor deposition. A
After forming the J film, this AI film is patterned into a predetermined shape by etching to form the 11th! ! Wires 148 to 14c are formed as shown in aH, thereby completing the desired MOSLSI.
以上のように、この実施例によれば、コンタクトホール
Ｃ，〜Ｃ３の部分を除いた層間絶縁膜１０の表面を反射
膜１１で覆い、この状態でＮを含む雰囲気中においてレ
ーザビームＢを照射することによりこれらのコンタクト
ホールＣ．〜Ｃ，の内部におけるＴｉＳｉ．膜９ａ〜９
Ｃのみを局所的に高温に加熱しているので、これらのコ
ンタクトホールＣ．〜Ｃ．の内部におけるＴｉＳｉｔ膜
９ａ〜９ｃの上にこれらのコンタクトホールＣ１〜Ｃ３
に対して自己整合的にＴｉＮ膜１３ａ〜１３Ｃを形成す
ることができる。この場合、レーザビームＢが照射され
ない部分は高温に加熱されないので、窒化が行われない
部分におけるＴｉＳｉ，膜９ａ〜９ｃの表面にヒロック
（ｈｉｌｌｏｃｋ）が形成されたりしてモフォロジーの
劣化が生じることがなく、従って電気的特性の劣化は生
じない。さらにまた、ソース領域６及びドレイン領域７
中の不純物の再拡散が生じることのないので、これらの
ソース領域６及びドレイン領域７が広がることもない。As described above, according to this embodiment, the surface of the interlayer insulating film 10 except for the contact holes C and C3 is covered with the reflective film 11, and in this state, the laser beam B is irradiated in an atmosphere containing N. These contact holes C. ~C, TiSi. Membranes 9a-9
Since only C.C is locally heated to a high temperature, these contact holes C. ~C. These contact holes C1 to C3 are formed on the TiSit films 9a to 9c inside the
The TiN films 13a to 13C can be formed in a self-aligned manner. In this case, since the portions that are not irradiated with the laser beam B are not heated to a high temperature, hillocks may be formed on the surfaces of the TiSi films 9a to 9c in the portions where nitridation is not performed, resulting in deterioration of morphology. Therefore, no deterioration of electrical characteristics occurs. Furthermore, source region 6 and drain region 7
Since re-diffusion of impurities therein does not occur, these source regions 6 and drain regions 7 do not spread.
なお、第２図及び第３図は、上記実施例における方法に
より６００〜７００人の厚さのＴｉＳｉ＊膜に照射する
エキシマレーザのエネルギー密度を変化させた場合のコ
ンタクト抵抗及びシート抵抗を測定した結果を示すグラ
フである。なお、両図において示す矢印はエキシマレー
ザを照射しない場合の値を示している。また、第４図は
、ｐ型ＭＯＳトランジスタにおけるリーク電流を、上記
実施例ニよるエキシマレーザのエネルギー密度を変えて
測定した結果を示すグラフである。なお、同図中矢印は
、エキシマレーザを照射しない場合の値を示している。In addition, FIGS. 2 and 3 show the contact resistance and sheet resistance measured when the energy density of the excimer laser irradiated to a TiSi* film with a thickness of 600 to 700 people was varied by the method in the above example. It is a graph showing the results. Note that the arrows shown in both figures indicate values when the excimer laser is not irradiated. Moreover, FIG. 4 is a graph showing the results of measuring leakage current in a p-type MOS transistor by changing the energy density of the excimer laser according to the above embodiment. Note that the arrows in the figure indicate values when the excimer laser is not irradiated.
これらグラフが示すように、コンタクト抵抗，シート抵
抗及びリーク電流に対して、レーザ照射条件が大きく影
響を及ぼすことが判る。例えばエキシマレーザのエネル
ギー密度が３０００ｍＪ以上になると抵抗値が非常に高
《なると共に、８０ＱｍＪではリークレベルが、エキシ
マレーザを照射しない場合と同程度となる（〜１０００
ｎＡ）。As these graphs show, it can be seen that the laser irradiation conditions have a large effect on the contact resistance, sheet resistance, and leakage current. For example, when the energy density of the excimer laser exceeds 3000 mJ, the resistance value becomes extremely high, and at 80 QmJ, the leakage level becomes the same as when no excimer laser is used (~1000 mJ).
nA).
また、１４００ｍＪ〜２２００ｍＪにおいて、コンタク
ト抵抗，シート抵抗及びリーク電流が低く保たれている
ことが判る。Furthermore, it can be seen that the contact resistance, sheet resistance, and leakage current are kept low in the range of 1400 mJ to 2200 mJ.
次に、第５図は、本発明に係る他の実施例を示している
。Next, FIG. 5 shows another embodiment according to the present invention.
本実施例においては、上記した実施例の第ｌ図Ｅに示す
工程の後に、ＴｉＳｉｔ９ａ， ９ｂ，９Ｃ表面上にＳ
ｉ゛を例えば、出力２ ０ Ｋ ｅ Ｖ， ド人を行
ないＴｉＳｉ，の表面をアモルファス層（図中Ｘ印で示
す）を形成する。In this example, after the step shown in FIG. 1E of the above-mentioned example, S
For example, an amorphous layer (indicated by an X mark in the figure) is formed on the surface of TiSi by performing an amorphous process at an output of 20 K e V, for example.
次に、上記した実施例の第１図Ｆに相当する工程を行な
いＴｉＳｉ．表面の前記アモルファス層をＴｉＮ膜に変
化させる。なお、本工程においては、エキシマレーザの
照射は、パルスショット処理を行なってもよい。また、
注入するイオンはＳｉ゜の他、Ｔｉ゜やＮ゜．等を用い
てもよい。Next, a step corresponding to FIG. 1F of the above-described embodiment is performed to form a TiSi. The amorphous layer on the surface is changed to a TiN film. Note that in this step, the excimer laser irradiation may be performed by pulse shot processing. Also,
In addition to Si°, the ions to be implanted include Ti° and N°. etc. may also be used.
本実施例においては、形成されたアモルファス層の融点
が低いため、エネルギー効率を向上することが可能とな
る。また、ＴｉＳｉ．表面にイオン注入するのではなく
、Ｓｉ基板上にイオン注入を行なってもよい。本実施例
は、特に径寸法の小さいコンタクトホール（０．３５μ
以下のプロセス）に適用した場合に効果的である。さら
に、アモルファス層の融点が低くなるため、レーザピー
ムの大面積化及びレーザ装置の小型化を可能にする利点
がある。In this example, since the formed amorphous layer has a low melting point, it is possible to improve energy efficiency. Moreover, TiSi. Ion implantation may be performed on the Si substrate instead of ion implantation on the surface. In this example, a contact hole with a particularly small diameter (0.35μ
It is effective when applied to the following processes. Furthermore, since the melting point of the amorphous layer is lowered, there is an advantage that the area of the laser beam can be increased and the size of the laser device can be reduced.
以上、本発明の実施例につき具体的に説明したが、本発
明は、上述の実施例に限定されるものではなく、本発明
の技術的思想に基づく各種の変形が可能である。Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.
例えば、上記両実施例においては、高融点金属としてＴ
ｉを用いたが、タングステン（Ｗ），モリブデン（ＭＯ
）等を適用しても同様である。For example, in both of the above embodiments, T is used as the high melting point metal.
i was used, but tungsten (W), molybdenum (MO
) etc. are applied.
また、上記実施例においては、最終構造に反射膜ｌ１を
残しているが、この反射膜１ｌは例えば配線１４〜１４
ｃを形成する前に例えばリン酸によりエッチング除去す
ることも可能である。また、この反射膜ｌ１としては、
例えばＴｉ膜のようなバリアメタル膜を用いることも可
能である。さらに、この反射膜ｌ１の代わりにレーザピ
ームＢに対して吸収性のある他の金属膜を用いても、コ
ンタクトホールＣ，−Ｃ３の内部におけるＴｉＳｉ，１
１Ｑ９ａ〜９ＣにのみレーザビームＢを選択的に照射す
ることが可能である。Further, in the above embodiment, the reflective film l1 is left in the final structure, but this reflective film l1 is, for example, the wiring 14 to 14.
It is also possible to perform etching removal using, for example, phosphoric acid before forming c. Moreover, as this reflective film l1,
For example, it is also possible to use a barrier metal film such as a Ti film. Furthermore, even if another metal film that absorbs the laser beam B is used instead of the reflective film l1, the TiSi,1
It is possible to selectively irradiate only 1Q9a to 9C with the laser beam B.
また、上述の実施例においては、本発明をＭＯＳトラン
ジスタに適用した場合について説明したが、本発明は、
例えばバイポーラＬＳＩやバイポーラＣＭＯＳＬＳＩの
ようなＭＯＳＬＳＩ以外の半導体集積回路装置の製造に
適用することも可能である。Furthermore, in the above-mentioned embodiments, the case where the present invention is applied to a MOS transistor was explained, but the present invention
For example, it is also possible to apply the present invention to the manufacture of semiconductor integrated circuit devices other than MOSLSI, such as bipolar LSI and bipolar CMOS LSI.
［発明の効果］
以上述べたように、本発明によれば、窒素を含む雰囲気
中で高融点金属シリサイド膜にレーザビームを選択的に
照射することにより高融点金属窒化物膜を形成するよう
にしているので、レーザビームが照射されない部分は高
温に加熱されず、従って、高融点金属シリサイド膜の表
面のモフォロジーの劣化や不純物の再拡散が生じるのを
防止することかできる。[Effects of the Invention] As described above, according to the present invention, a high melting point metal nitride film is formed by selectively irradiating a high melting point metal silicide film with a laser beam in an atmosphere containing nitrogen. Therefore, the portions that are not irradiated with the laser beam are not heated to a high temperature, and therefore, it is possible to prevent deterioration of the morphology of the surface of the high melting point metal silicide film and re-diffusion of impurities.
また、本発明によれば、コンタクト抵抗，シート抵抗及
びリーク電流を低《保てる効果がある。Further, according to the present invention, there is an effect that contact resistance, sheet resistance, and leakage current can be kept low.
第ｌ図Ａ〜第ｌ図Ｈは本発明の実施例によるＭｏＳトラ
ンジスタの製造方法を工程順に示す断面図、第２図はエ
キシマレーザのエネルギー密度とコンタクト抵抗との関
係を示すグラフ、第３図はエキシマレーザのエネルギー
密度とシート抵抗との関係を示すグラフ、第４図はエキ
シマレーザのエネルギー密度とリーク電流の関係を示す
グラフ、第５図は本発明の他の実施例を示す断面図であ
る。
ｌ・・・半導体基板、２・・・フィールド絶縁膜、４・
・・ゲート電極、６・・・ソース領域、７・・・ドレイ
ン領域、８・ Ｔｉ膜、９ ａ〜９ ｃ−・−Ｔ ｉ
Ｓ ｉ ，膜、１１・・・反射膜、１３ａ−ｌ３ｃ−Ｔ
ｉ Ｎ膜、１４〜１４Ｃ・・・配線、０１〜Ｃ，・・
・コンタクトホール。
実施例
第１図Ａ
実施例
第１図Ｂ
第１図Ｄ
実１例
Ｂレーザーと一二
＄
−実施例
第１図Ｆ
第１
図Ｇ
一実施例
第１図Ｈ
エネルギー（ｍｊ）
エキシマレーザのエネルギー密度とリーク電流を示すグ
ラフ第４図
他の１ｊ施例
第５図Figures 1A to 1H are cross-sectional views showing step-by-step a method for manufacturing a MoS transistor according to an embodiment of the present invention, Figure 2 is a graph showing the relationship between excimer laser energy density and contact resistance, and Figure 3 is a graph showing the relationship between excimer laser energy density and contact resistance. 4 is a graph showing the relationship between the energy density and sheet resistance of the excimer laser, FIG. 4 is a graph showing the relationship between the energy density of the excimer laser and leakage current, and FIG. 5 is a cross-sectional view showing another embodiment of the present invention. be. l...Semiconductor substrate, 2...Field insulating film, 4...
. . . Gate electrode, 6. Source region, 7. Drain region, 8. Ti film, 9 a to 9 c-.-Ti
S i , film, 11... reflective film, 13a-l3c-T
i N film, 14~14C... wiring, 01~C,...
・Contact hole. Example Fig. 1 A Example Fig. 1 B Fig. 1 D Actual Example B Laser and $12 - Example Fig. 1 F Fig. 1 G Example Fig. 1 H Energy (mj) of excimer laser Graph showing energy density and leakage current Figure 4 Other 1j examples Figure 5
Claims (1)
イド膜上に形成された高融点金属窒化物膜とを有する半
導体装置の製造方法において、Ｎ（窒素）を含む雰囲気
中で前記高融点金属シリサイド膜に、エネルギー密度１
４００〜２２００ｍＪ／ｃｍ＾２のレーザビームを選択
的に照射することにより前記高融点金属窒化物膜を形成
するようにしたことを特徴とする半導体装置の製造方法
。(1) In a method for manufacturing a semiconductor device having a high melting point metal silicide film and a high melting point metal nitride film formed on the high melting point metal silicide film, the high melting point metal is In the silicide film, the energy density is 1
A method for manufacturing a semiconductor device, characterized in that the high melting point metal nitride film is formed by selectively irradiating a laser beam of 400 to 2200 mJ/cm^2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057571A JP2864518B2 (en) | 1989-03-09 | 1989-03-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057571A JP2864518B2 (en) | 1989-03-09 | 1989-03-09 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02237026A true JPH02237026A (en) | 1990-09-19 |
| JP2864518B2 JP2864518B2 (en) | 1999-03-03 |
Family
ID=13059532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1057571A Expired - Fee Related JP2864518B2 (en) | 1989-03-09 | 1989-03-09 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2864518B2 (en) |
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| US6583052B2 (en) | 2001-09-05 | 2003-06-24 | Hynix Semiconductor Inc. | Method of fabricating a semiconductor device having reduced contact resistance |
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| US10374109B2 (en) | 2001-05-25 | 2019-08-06 | President And Fellows Of Harvard College | Silicon-based visible and near-infrared optoelectric devices |
| US6583052B2 (en) | 2001-09-05 | 2003-06-24 | Hynix Semiconductor Inc. | Method of fabricating a semiconductor device having reduced contact resistance |
| US10741399B2 (en) | 2004-09-24 | 2020-08-11 | President And Fellows Of Harvard College | Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate |
| US10361083B2 (en) | 2004-09-24 | 2019-07-23 | President And Fellows Of Harvard College | Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate |
| WO2010042121A1 (en) * | 2008-10-09 | 2010-04-15 | Sionyx Inc. | Method for contact formation in semiconductor device |
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| US9673243B2 (en) | 2009-09-17 | 2017-06-06 | Sionyx, Llc | Photosensitive imaging devices and associated methods |
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| US9761739B2 (en) | 2010-06-18 | 2017-09-12 | Sionyx, Llc | High speed photosensitive devices and associated methods |
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| US9496308B2 (en) | 2011-06-09 | 2016-11-15 | Sionyx, Llc | Process module for increasing the response of backside illuminated photosensitive imagers and associated methods |
| US9666636B2 (en) | 2011-06-09 | 2017-05-30 | Sionyx, Llc | Process module for increasing the response of backside illuminated photosensitive imagers and associated methods |
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| US10224359B2 (en) | 2012-03-22 | 2019-03-05 | Sionyx, Llc | Pixel isolation elements, devices and associated methods |
| FR2992957A1 (en) * | 2012-07-09 | 2014-01-10 | Saint Gobain | THIN FILM DEPOSITION METHOD WITH CONTROLLED ATMOSPHERE TREATMENT STEP AND PRODUCT OBTAINED |
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| US9673250B2 (en) | 2013-06-29 | 2017-06-06 | Sionyx, Llc | Shallow trench textured regions and associated methods |
| US11069737B2 (en) | 2013-06-29 | 2021-07-20 | Sionyx, Llc | Shallow trench textured regions and associated methods |
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| JP2864518B2 (en) | 1999-03-03 |
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