JPH0221750U - - Google Patents
Info
- Publication number
- JPH0221750U JPH0221750U JP10050588U JP10050588U JPH0221750U JP H0221750 U JPH0221750 U JP H0221750U JP 10050588 U JP10050588 U JP 10050588U JP 10050588 U JP10050588 U JP 10050588U JP H0221750 U JPH0221750 U JP H0221750U
- Authority
- JP
- Japan
- Prior art keywords
- lead
- percolation
- resin
- connects
- adjacent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005325 percolation Methods 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案の一実施例を示す正面図、第２
図は従来例を示す正面図である。 １……樹脂モールド型トランジスタ用ペレツト
、２……第１のリード片、３……ボンデイングワ
イヤ、４……第２のリード片、５……第１のパー
コレーシヨン、７……第２のパーコレーシヨン。
図は従来例を示す正面図である。 １……樹脂モールド型トランジスタ用ペレツト
、２……第１のリード片、３……ボンデイングワ
イヤ、４……第２のリード片、５……第１のパー
コレーシヨン、７……第２のパーコレーシヨン。
Claims (1)
- 樹脂モールド型トランジスタ用ペレツトを搭載
する第１のリード片と、前記ペレツトにボンデイ
ングワイヤを介して電気的に接続される第２のリ
ード片との組を縦列に配列してなるリードフレー
ムにおいて、隣接する組の第１及び第２のリード
片の先端相互間を一定ピツチで結合する第１のパ
ーコレーシヨンと、隣接する組の第１のリード片
の頭部相互間を結合する第２のパーコレーシヨン
とを有することを特徴とする樹脂モールド型トラ
ンジスタのリードフレーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10050588U JPH0221750U (ja) | 1988-07-28 | 1988-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10050588U JPH0221750U (ja) | 1988-07-28 | 1988-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221750U true JPH0221750U (ja) | 1990-02-14 |
Family
ID=31328639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10050588U Pending JPH0221750U (ja) | 1988-07-28 | 1988-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221750U (ja) |
-
1988
- 1988-07-28 JP JP10050588U patent/JPH0221750U/ja active Pending