JPH02158857A - Control system for input/output controller - Google Patents

Control system for input/output controller

Info

Publication number
JPH02158857A
JPH02158857A JP31303888A JP31303888A JPH02158857A JP H02158857 A JPH02158857 A JP H02158857A JP 31303888 A JP31303888 A JP 31303888A JP 31303888 A JP31303888 A JP 31303888A JP H02158857 A JPH02158857 A JP H02158857A
Authority
JP
Japan
Prior art keywords
cmb
instruction
address
input
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31303888A
Other languages
Japanese (ja)
Other versions
JP2734581B2 (en
Inventor
Isao Nozaki
野崎 功
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63313038A priority Critical patent/JP2734581B2/en
Publication of JPH02158857A publication Critical patent/JPH02158857A/en
Application granted granted Critical
Publication of JP2734581B2 publication Critical patent/JP2734581B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To allow an IOCU to immediately execute an instruction at the time of outputting an instruction from a CPU by storing a written CMB address in an FIFO when the CPU writes the instruction in a CMB and outputting an instruction execution request to the IOCU. CONSTITUTION:When the central processing unit(CPU) 1 writes an instruction in a command mail box(CMB) 3 based upon a CMB address, the CMB address is stored in the first-in first-out (FIFO) 4. At the time of storing the CMB address, the FIFO 4 informs the writing of the instruction from the CPU 1 in the CMB 3 to an input/output control unit(IOCU) 2 by a command execution requesting signal 6. The IOCU 2 reads out the CMB address from the FIFO by a CMB address reading signal 7 and reads out the address of the CMB 3 in which the instruction inputted from the CPU 1 is written. Consequently, the IOCU 2 can refer to the CMB address and read out the instruction from the CMB 3 to execute it.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 との発明は入出力制御装置の制御方式に関し、特に命令
の実行要求を直接性なう入出力制御装置の制御方式に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The invention relates to a control method for an input/output control device, and particularly to a control method for an input/output control device that directly requests execution of instructions.

〔従来の技術〕[Conventional technology]

従来、この種の入出力制御装置の制御方式は、中央処理
装置が命令をコマンドメールボックスに書き込む。そし
て、インプットアワトプットコントロールユニットは中
央処理装置がコマンドメールボックスにいつ命令を書き
込んでもいいように周期的にこのコマンドメールボック
スカラデータを読み出し、データの内容をチエツクして
中央処理装置からの命令があるか否かを判断していた。
Conventionally, in the control method of this type of input/output control device, a central processing unit writes commands to a command mailbox. Then, the input-after-put control unit periodically reads out this command mailbox color data so that the central processing unit can write commands to the command mailbox at any time, checks the contents of the data, and checks the contents of the data so that the central processing unit can write commands to the command mailbox at any time. I was deciding whether it was there or not.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の入出力制御装置の制御方式は、中央処理
装置が命令をコマンドメールボックスに書き込んでも、
インプットアワトプットコントロールユニットが一定周
期ごとに中央処理装置からの命令があるか否かの判断を
するまで命令は受は付けられない。しかも、このインプ
ットアワトプットコントロールユエットは中央処理装置
からの命令がなくても一定周期ごとに働かなければなら
ないという欠点がある。
In the conventional input/output control device control method described above, even if the central processing unit writes an instruction to the command mailbox,
No command will be accepted until the input/output control unit determines whether or not there is a command from the central processing unit at regular intervals. In addition, this input/output control unit has the disadvantage that it must operate at regular intervals even without instructions from the central processing unit.

〔課題を解決するための手段〕[Means to solve the problem]

との発明に係る入出力制御装置の制御方式は、中央処理
装置から入出力制御装置へ命令を引渡すため入出力装置
に対応した複数の番地からなるコマンドメールボックス
と、中央処理装置が命令をコマンドメールボックスに書
き込んだときのCMBアドレスを書き込んだ順に記憶し
、CMBアドレスを記憶している間は入出力装置に命令
の実行要求を割込みとして出力し、入出力制御装置が命
令の実行をするときどのCMBアドレスに命令が書かれ
ているかを中央処理装置が命令をCMBアドレスに書き
込んだ項に読み出すメモリ手段とを有している。
The control method for the input/output control device according to the invention of The CMB addresses written in the mailbox are stored in the order in which they were written, and while the CMB addresses are stored, an instruction execution request is output to the input/output device as an interrupt, and when the input/output control device executes the instruction. and memory means for reading out to which CMB address the instruction is written to the CMB address in which the central processing unit writes the instruction.

〔作 用〕[For production]

この発明は中央処理装置からの命令があれば入出力制御
装置は直ちに命令を実行することができる。
According to the present invention, if there is an instruction from the central processing unit, the input/output control device can immediately execute the instruction.

〔実施例〕 図はこの発明に係る入出力制御装置の制御方式の一実施
例を示すブロック図である。同図において、1は中央処
理装置(以下CPUと言う)、2はこのCPU1からの
命令によシ複数の入出力装置の制御を行なう単一のイン
プットアヮトプットコントロールユニット(以下単K 
IoCU とtう)、3は入出力装置に対応した複数の
番地から構成されCPU1からl0CU2 へ命令を引
き渡すコマンドメールボックス(以下単にCMBと言う
)、4は複数の入出力装置に対応したそれぞれのQ$ボ
アドレス書き込んだ順に記憶し、そしてとのCMBアド
レスを書き込まれた順に読み出すファーストインファー
ストアヮト(以下単にFIFOと言う)、5はコマンド
ライト信号、6はコマンド実行要求信号、7はCMBア
ドレスリード信号である。
[Embodiment] The figure is a block diagram showing an embodiment of a control method for an input/output control device according to the present invention. In the figure, 1 is a central processing unit (hereinafter referred to as CPU), and 2 is a single input/output control unit (hereinafter simply referred to as K) that controls multiple input/output devices according to instructions from CPU 1.
3 is a command mailbox (hereinafter simply referred to as CMB) that is composed of multiple addresses corresponding to input/output devices and transfers instructions from CPU1 to 10CU2, and 4 is a command mailbox (hereinafter simply referred to as CMB) that is composed of multiple addresses corresponding to input/output devices. First-in-first address (hereinafter simply referred to as FIFO) that stores Q$BOARD addresses in the order in which they are written and reads CMB addresses in the order in which they are written. 5 is a command write signal, 6 is a command execution request signal, and 7 is a command execution request signal. This is a CMB address read signal.

次に上記構成による入出力制御装置の制御方式の動作に
ついて説明する。まず、CPU1 が命令をCMBアド
レスによficMB3に書き込むとき、とのCMBアド
レスはFIFO4に記憶させる。
Next, the operation of the control method of the input/output control device having the above configuration will be explained. First, when CPU1 writes an instruction to ficMB3 using a CMB address, the CMB address is stored in FIFO4.

このFIFO4はとのCMBアドレスを記憶すると、コ
マンド実行要求信号6によ!1)IOCU2 に対して
CPU 1  から命令がCMB3  に書き込まれた
ことを知らせる。このl0CU2はCMBアドレスリー
ド信号7によfi FIFO4からCMBアドレスを読
み出してCPU1  からの命令がCMB3のどこに命
令が書き込まれたかを読み出す。
When this FIFO 4 stores the CMB address, it receives the command execution request signal 6! 1) Notify IOCU2 that an instruction has been written to CMB3 from CPU1. This l0CU2 reads the CMB address from the fi FIFO 4 in response to the CMB address read signal 7, and reads out where in the CMB3 the command from the CPU1 is written.

したがって、l0CU2  はこのCMBアドレスを参
照し、CMB3 から命令を読み出し実行することがで
きる。
Therefore, l0CU2 can refer to this CMB address and read and execute instructions from CMB3.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように1この発明に係る入出力制御
装置の制御方式によれば、CPUがCMHに命令を書き
込むと、書き込んだCMBアドレスをPIFOK記憶し
、l0CUに対して命令の実行要求を行なうととKより
、CPUからの命令がなければl0CUは停止したまま
でCPUからの命令があればl0CUは直ちに命令を実
行することができるなどの効果がある。
As explained in detail above, 1. According to the control method of the input/output control device according to the present invention, when the CPU writes an instruction to the CMH, the written CMB address is stored in the PIFOK, and a request to execute the instruction is sent to the CU. This has the effect that if there is no instruction from the CPU, the 10CU remains stopped, but if there is an instruction from the CPU, the 10CU can immediately execute the instruction.

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの発明に係る入出力制御装置の制御方式の一実施
例を示すブロック図である。 1・・・・中央処理装置(CPU)、2 、・・・イン
プットアワトプットコントロールユニット(I OCU
 )、3−+1・・コマンドメールボックス(CMB)
、 4・・・・ファーストインファーストアワト(FI
FO)、5・m−・コマンドライト信号、6・・・・コ
マンド実行要求信号、T争φΦ・CMBアドレスリード
信号。
FIG. 1 is a block diagram showing an embodiment of a control method for an input/output control device according to the present invention. 1... Central processing unit (CPU), 2... Input output control unit (I OCU)
), 3-+1...Command mailbox (CMB)
, 4... First in First Awato (FI
FO), 5.m-.command write signal, 6..command execution request signal, T conflict φΦ.CMB address read signal.

Claims (1)

【特許請求の範囲】[Claims] 中央処理装置からの命令により複数の入出力装置を制御
する入出力制御装置の制御方式において、中央処理装置
から入出力制御装置へ命令を引渡すため入出力装置に対
応した複数の番地からなるコマンドメールボックスと、
中央処理装置が命令をコマンドメールボックスに書き込
んだときのCMBアドレスを書き込んだ順に記憶し、C
MBアドレスを記憶している間は入出力装置に命令の実
行要求を割込みとして出力し、入出力制御装置が命令の
実行をするときどのCMBアドレスに命令が書かれてい
るかを中央処理装置が命令をCMBアドレスに書き込ん
だ順に読み出すメモリ手段とを備えたことを特徴とする
入出力制御装置の制御方式。
In a control method for an input/output control device that controls multiple input/output devices using commands from the central processing unit, a command mail consisting of multiple addresses corresponding to the input/output devices is used to transfer commands from the central processing unit to the input/output control device. box and
When the central processing unit writes instructions to the command mailbox, the CMB addresses are stored in the order in which they were written, and the CMB addresses are
While the MB address is being memorized, an instruction execution request is output to the input/output device as an interrupt, and when the input/output control device executes the instruction, the central processing unit determines which CMB address the instruction is written to. 1. A control method for an input/output control device, comprising: memory means for reading out the CMB addresses in the order in which they are written to the CMB address.
JP63313038A 1988-12-13 1988-12-13 Control method of input / output control unit Expired - Lifetime JP2734581B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63313038A JP2734581B2 (en) 1988-12-13 1988-12-13 Control method of input / output control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63313038A JP2734581B2 (en) 1988-12-13 1988-12-13 Control method of input / output control unit

Publications (2)

Publication Number Publication Date
JPH02158857A true JPH02158857A (en) 1990-06-19
JP2734581B2 JP2734581B2 (en) 1998-03-30

Family

ID=18036459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63313038A Expired - Lifetime JP2734581B2 (en) 1988-12-13 1988-12-13 Control method of input / output control unit

Country Status (1)

Country Link
JP (1) JP2734581B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8473649B2 (en) 2010-07-23 2013-06-25 Kabushiki Kaisha Toshiba Command management device configured to store and manage received commands and storage apparatus with the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375955A (en) * 1986-09-19 1988-04-06 Fujitsu Ltd Program mode access control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375955A (en) * 1986-09-19 1988-04-06 Fujitsu Ltd Program mode access control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8473649B2 (en) 2010-07-23 2013-06-25 Kabushiki Kaisha Toshiba Command management device configured to store and manage received commands and storage apparatus with the same

Also Published As

Publication number Publication date
JP2734581B2 (en) 1998-03-30

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