JPH02133961A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH02133961A
JPH02133961A JP28743888A JP28743888A JPH02133961A JP H02133961 A JPH02133961 A JP H02133961A JP 28743888 A JP28743888 A JP 28743888A JP 28743888 A JP28743888 A JP 28743888A JP H02133961 A JPH02133961 A JP H02133961A
Authority
JP
Japan
Prior art keywords
elements
internal cell
complementary mos
logic circuit
bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28743888A
Other languages
Japanese (ja)
Inventor
Naoko Sugaya
菅谷　直子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP28743888A priority Critical patent/JPH02133961A/en
Publication of JPH02133961A publication Critical patent/JPH02133961A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a high-speed logic circuit by a method wherein a plurality of internal cell rows constituted of only complementary MOS elements and a plurality of internal cell rows constituted of only bipolar elements are arranged alternately inside an internal cell region. CONSTITUTION:A plurality of internal cell rows 3 constituted of only bipolar elements and a plurality of internal cell rows 4 constituted of only complementary MOS elements are arranged alternately in an internal cell region of an IC chip. Accordingly, the transfer delay time tpd can be made smaller that of an IC chip using a gate array type semiconductor integrated circuit device where a two-stage constitution of a complementary MOS element and a bipolar element is arranged in a matrix manner as one cell; a logic circuit can be constituted of only the complementary MOS element with reference to a low load capacity; the logic circuit can be constituted of the two-stage constitution of the complementary MOS element and the bipolar element with reference to a high load capacity; as a result, a high-speed logic circuit can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特に相補型ＭＯＳ
素子とバイポーラ素子で論理回路を構成したゲートアレ
イ方式で設計される半導体集積回路装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary MOS
The present invention relates to a semiconductor integrated circuit device designed using a gate array method in which a logic circuit is constructed using elements and bipolar elements.

〔従来の技術〕[Conventional technology]

従来の相補型ＭＯＳ素子とバイポーラ素子で論理回路を
構成したゲートアレイ方式による半導体集積回路装置に
おいて、内部セル領域の構成は入力段の相補型ＭＯＳ素
子と、出力段のバイポーラ素子との２段構成となってお
り、それを内部１セルとして行列配置されていた。In a conventional semiconductor integrated circuit device using a gate array method in which a logic circuit is configured with complementary MOS elements and bipolar elements, the internal cell area has a two-stage configuration of complementary MOS elements in the input stage and bipolar elements in the output stage. , which was arranged in rows and columns as one internal cell.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の相補型ＭＯＳ素子とバイポーラ素子で論
理回路を構成したゲートアレイ方式による半導体集積回
路装置では、入力段の相補型ＭＯＳ素子と、出力段のバ
イポーラ素子との２段構成となっており、それを内部１
セルとして行列配置され。The above-mentioned conventional semiconductor integrated circuit device using a gate array method in which a logic circuit is constructed using complementary MOS elements and bipolar elements has a two-stage configuration of a complementary MOS element at the input stage and a bipolar element at the output stage. , put it inside 1
Arranged as cells in rows and columns.

その負荷容量ＣＬに対する伝達遅延時間ｔＰｄの増加分
は出力段のバイポーラ素子の高い駆動能力により、相補
型ＭＯＳ素子のみで構成されたゲートアレイのそれより
も少ない、つまり１重い負荷容量ＣＬに対する伝達遅延
時間ｔＰｄの増加を低くでき、高速動作をする。ところ
が、相補型ＭＯＳ素子とバイポーラ素子の２段構成とな
っているため、小さな負荷容量Ｃしに対しては相補型Ｍ
ＯＳ素子のみで論理回路を構成したゲートアレイよりも
、伝達遅延時間ｔＰｄは大きいという欠点がある。Due to the high driving ability of the bipolar elements in the output stage, the increase in the transmission delay time tPd with respect to the load capacitance CL is smaller than that of a gate array composed of only complementary MOS elements, that is, the transmission delay with respect to the load capacitance CL, which is 1 heavier. The increase in time tPd can be reduced and high-speed operation can be achieved. However, since it has a two-stage configuration of a complementary MOS element and a bipolar element, the complementary type M
It has a disadvantage that the transmission delay time tPd is larger than that of a gate array in which a logic circuit is formed only from OS elements.

本発明の目的は前記課題を解決した半導体集積回路装置
を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device that solves the above problems.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため１本発明は相補型ＭＯＳ素子と
バイポーラ素子で論理回路を構成するゲートアレイ方式
の半導体集積回路装置において、相補型ＭＯＳ素子のみ
で構成された複数個の内部セル行と、バイポーラ素子の
みで構成された複数個の内部セル行とを内部セル領域内
に交互に配置したものである。In order to achieve the above object, the present invention provides a gate array type semiconductor integrated circuit device in which a logic circuit is configured with complementary MOS elements and bipolar elements, including a plurality of internal cell rows composed only of complementary MOS elements; A plurality of internal cell rows consisting only of bipolar elements are alternately arranged within the internal cell region.

〔実施例〕〔Example〕

以下１本発明の一実施例を図により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図は本発明の一実施例を示す構成図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

図において、１，２はＩＣチップ周辺に配設したそれぞ
れパッド、入出力セルである。In the figure, numerals 1 and 2 are pads and input/output cells arranged around the IC chip, respectively.

本発明はＩＣチップの内部セル領域に、バイポーラ素子
のみで構成された複数個の内部セル行３と、相補型ＭＯ
Ｓ素子のみで構成された複数個の内部セル行４とを交互
に配設したものである。尚、内部セル行３と４との配置
関係は図示のものと逆のものでもよい。The present invention provides a plurality of internal cell rows 3 composed of only bipolar elements and complementary MOSFETs in the internal cell area of an IC chip.
A plurality of internal cell rows 4 made up only of S elements are arranged alternately. Note that the arrangement relationship between the internal cell rows 3 and 4 may be reversed from that shown.

ところで、従来の相補型ＤＯ８素子とバイポーラ素子混
在のゲートアレイでは重い負荷容量Ｃしに対する伝達遅
延時間ｔＰｄの増加を低くでき、高速動作をする。とこ
ろが、内部セルが相補型ＭＯＳ素子とバイポーラ素子と
の２段構成となっているため、小さな負荷容量Ｃしに対
しては相補型ＭＯＳ素子のみで論理回路を構成されたゲ
ートアレイより伝達遅延時間ｔＰｄは大きい。By the way, in the conventional gate array in which complementary DO8 elements and bipolar elements are mixed, the increase in the transmission delay time tPd due to heavy load capacitance C can be reduced, and the gate array can operate at high speed. However, since the internal cell has a two-stage configuration of complementary MOS elements and bipolar elements, for a small load capacitance C, the transmission delay time is shorter than that of a gate array whose logic circuit is composed of only complementary MOS elements. tPd is large.

これに対し、本発明の構成のように、低負荷容量に対し
ては相補型ＭＯＳ素子のみで論理回路を構成し、高負荷
容量Ｃしに対しては相補型ＭＯＳ素子とバイポーラ素子
の２段構成の論理回路を構成すれば、双方の利点を生か
した高速の論理回路を実現できる。On the other hand, as in the configuration of the present invention, a logic circuit is configured with only complementary MOS elements for low load capacitance, and two stages of complementary MOS elements and bipolar elements are configured for high load capacitance C. By configuring a logic circuit with this configuration, it is possible to realize a high-speed logic circuit that takes advantage of both advantages.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は相補型ＭＯＳ素子のみで構
成した複数個の内部セル行とバイポーラ素子のみで構成
した複数個の内部セル行を交互に配置することにより、
相補型ＭＯＳ素子とバイポーラ素子の２段構成を１つの
セルとして行列配置されたゲートアレイ方式半導体集積
回路装置を使用したＩＣチップよりも伝達遅延時間ｔＰ
ｄを小さくでき、低負荷容量に対しては相補型ＭＯＳ素
子のみで論理回路を構成でき、高負荷容量に対しては相
補型肛Ｓ素子とバイポーラ素子の２段構成の論理回路が
でき、その結果高速の論理回路の実現が可能となるとい
う効果を有する。As explained above, the present invention alternately arranges a plurality of internal cell rows composed only of complementary MOS elements and a plurality of internal cell rows composed only of bipolar elements.
The transmission delay time tP is longer than that of an IC chip using a gate array type semiconductor integrated circuit device in which a two-stage configuration of complementary MOS elements and bipolar elements is arranged in rows and columns as one cell.
d can be made small, and for low load capacitances, a logic circuit can be constructed with only complementary MOS elements, and for high load capacitances, a logic circuit with a two-stage configuration of complementary type S elements and bipolar elements can be constructed. As a result, it is possible to realize a high-speed logic circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す構成図である。 FIG. 1 is a block diagram showing an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] （１）相補型ＭＯＳ素子とバイポーラ素子で論理回路を
構成するゲートアレイ方式の半導体集積回路装置におい
て、相補型ＭＯＳ素子のみで構成された複数個の内部セ
ル行と、バイポーラ素子のみで構成された複数個の内部
セル行とを内部セル領域内に交互に配置したことを特徴
とする半導体集積回路装置。(1) In a gate array type semiconductor integrated circuit device in which a logic circuit is constructed with complementary MOS elements and bipolar elements, there are multiple internal cell rows composed only of complementary MOS elements and bipolar elements. A semiconductor integrated circuit device characterized in that a plurality of internal cell rows are alternately arranged within an internal cell region.
JP28743888A 1988-11-14 1988-11-14 Semiconductor integrated circuit device Pending JPH02133961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28743888A JPH02133961A (en) 1988-11-14 1988-11-14 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28743888A JPH02133961A (en) 1988-11-14 1988-11-14 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH02133961A true JPH02133961A (en) 1990-05-23

Family

ID=17717321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28743888A Pending JPH02133961A (en) 1988-11-14 1988-11-14 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH02133961A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100299738B1 (en) * 1996-09-09 2001-09-22 니시무로 타이죠 Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100299738B1 (en) * 1996-09-09 2001-09-22 니시무로 타이죠 Semiconductor integrated circuit

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