JPH02123826A - Cmos inverter circuit - Google Patents

Cmos inverter circuit

Info

Publication number
JPH02123826A
JPH02123826A JP63277858A JP27785888A JPH02123826A JP H02123826 A JPH02123826 A JP H02123826A JP 63277858 A JP63277858 A JP 63277858A JP 27785888 A JP27785888 A JP 27785888A JP H02123826 A JPH02123826 A JP H02123826A
Authority
JP
Japan
Prior art keywords
level
input
channel mos
node
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63277858A
Other languages
Japanese (ja)
Inventor
Kenji Matsue
松江　賢二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP63277858A priority Critical patent/JPH02123826A/en
Publication of JPH02123826A publication Critical patent/JPH02123826A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To block a through-current between a power potential and a ground potential by providing a delay element retarding an input for a prescribed period and a transmission gate used as a switch throwing to the input to a gate through the delay element or throwing the input directly to the gate. CONSTITUTION:With an input IN changed from a high to a low level, since the level of the node N1 changes from a low to a high level, a P-channel MOS transistor(TR) T4 and an N-channel MOS TR 3 are nonconductive and the level of a node N2 goes to a low level with a delay of a prescribed time by a delay element D1. The level of the node N3 has no delay due to a delay element D2 because a P-channel MOS TR T6 and an N-channel MOS TR T5 are conductive and is varied toward the low level as the input IN changes to the low level. Since the level of the node N3 goes to a low level earlier than the level of the node N2, the P-channel MOS TR T1 is conductive after the N-channel MOS TR T2 is nonconductive. Thus, a through-current flowing from the power potential to the ground potential is blocked.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＣＭＯＳインバータ回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a CMOS inverter circuit.

〔従来の技術〕[Conventional technology]

従来のＣＭＯＳインバータ回路は、接地電位と電源電位
ＶＤＤの間にＮチャネル型ＭＯＳトランジスタとＰチャ
ネル型ＭＯ９トランジスタが直列接続されている。In a conventional CMOS inverter circuit, an N-channel MOS transistor and a P-channel MO9 transistor are connected in series between a ground potential and a power supply potential VDD.

以下、第３図を用いてこの動作を説明する。This operation will be explained below using FIG. 3.

入力信号ＩＮがＬＯＷ（接地電位）である場合、Ｎチャ
ネル型ＭＯＳトランジスタＴ１８は非導通、Ｐチャネル
型ＭＯＳトランジスタＴ１７は導通しており、出力ＯＵ
ＴはＨＩＧＨ（電源電位）となっている。When the input signal IN is LOW (ground potential), the N-channel MOS transistor T18 is non-conductive, the P-channel MOS transistor T17 is conductive, and the output OU
T is HIGH (power supply potential).

入力ＩＮがＬＯＷからＨＩＧＨへと変化する場合、その
遷移期間においてＮチャネル型ＭＯＳトランジスタＴ１
８とＰチャネル型ＭＯＳトランジスタＴ１７が同時に導
通する期間が存在し、電源から接地電位側へ貫通電流が
流れる。When the input IN changes from LOW to HIGH, the N-channel MOS transistor T1 changes during the transition period.
There is a period in which both P-channel type MOS transistor T8 and P-channel type MOS transistor T17 are conductive at the same time, and a through current flows from the power supply to the ground potential side.

この貫通電流はＭＯＳトランジスタのチャネル幅が大き
い場合には多くなり、消費電流を増加させる。又、電源
及び接地電位のノイズの原因となる。This through current increases when the channel width of the MOS transistor is large, increasing current consumption. It also causes noise in the power supply and ground potential.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のＣＭＯＳインバータ回路は、出力バッフ
ァ等電流駆動能力を必要とする様なチャネル幅の大きな
トランジスタの場合、スイッチング時の貫通電流により
消費電流を増加させ、又電源電位及び接地電位にインダ
クタンス成分によりノイズが発生するという欠点が生じ
る。In the conventional CMOS inverter circuit described above, in the case of a transistor with a large channel width such as an output buffer that requires current drive capability, current consumption increases due to through current during switching, and inductance components are added to the power supply potential and ground potential. This has the disadvantage of generating noise.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のＣＭＯＳインバータ回路は、入力をある一定期
間遅らせる遅延素子と、入力を遅延素子を通してゲート
につなげるか、入力を直接ゲートにつなげるかのスイッ
チの為のトランスミッションゲートを有している。The CMOS inverter circuit of the present invention includes a delay element that delays an input for a certain period of time, and a transmission gate for switching between connecting the input to the gate through the delay element or directly connecting the input to the gate.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

入力ＩＮとＰチャネル型ＭＯＳトランジスタＴ１のゲー
ト電極との間に、遅延素子Ｄ１とＮチャネル型ＭＯＳト
ランジスタＴ３及びＰチャネル型ＭＯＳトランジスタＴ
４とで構成されるトランスミッションゲートを並列に接
続している。同様に入力ＩＮとＮチャネル型ＭＯ３トラ
ンジスタＴ２のゲート電極との間に遅延素子Ｄ２とＮチ
ャネル型ＭＯ８）−ランジスタＴ５及びＰチャネル型Ｍ
ＯＳトランジスタＴ６とで構成されるトランスミッショ
ンゲートを並列に接続している。A delay element D1, an N-channel MOS transistor T3, and a P-channel MOS transistor T are connected between the input IN and the gate electrode of the P-channel MOS transistor T1.
4 transmission gates are connected in parallel. Similarly, between the input IN and the gate electrode of the N-channel type MO3 transistor T2, there is a delay element D2, an N-channel type MO8)-transistor T5, and a P-channel type M
A transmission gate composed of an OS transistor T6 is connected in parallel.

今、入力ＩＮがＨＩＧＨからＬＯＷへ変化する時ノード
Ｎ１はＬＯＷからＨＩＧＨへ変化する為、Ｐチャネル型
ＭＯ８トランジスタＴ４、Ｎチャネル型ＭＯＳトランジ
スタＴ３は非導通となり、ノードＮ２は遅延素子Ｄ１に
より一定時間遅れてＬＯＷとなる。Now, when the input IN changes from HIGH to LOW, the node N1 changes from LOW to HIGH, so the P-channel type MO8 transistor T4 and the N-channel type MOS transistor T3 become non-conductive, and the node N2 is controlled by the delay element D1 for a certain period of time. It becomes LOW after a delay.

逆に、ノードＮ３はＰチャネル型ＭＯＳトランジスタＴ
６、Ｎチャネル型ＭＯＳトランジスタＴ５は導通する為
に遅延素子Ｄ２による遅れはなく、入力ＩＮがＬＯＷへ
変化するにつれてＬＯＷへと変化していく。Conversely, node N3 is a P-channel MOS transistor T.
6. Since the N-channel type MOS transistor T5 is conductive, there is no delay due to the delay element D2, and as the input IN changes to LOW, it changes to LOW.

従って、ノードＮ３はノードＮ２より先にＬＯＷになる
為、Ｎチャネル型ＭＯ３トランジスタＴ２が非導通とな
った後にＰチャネル型ＭＯＳトランジスタＴ１が導通す
る。これにより出力ＯＵＴがＬＯＷからＨＩＧＨへ変化
するスイッチング時においてＰチャネル型ＭＯ３トラン
ジスタＴ１とＮチャネル型ＭｏＳトランジスタＴ２が同
時に導通する期間が存在しない為、電源電位から接地電
位へと流れる貫通電流はなくなる。Therefore, since node N3 becomes LOW before node N2, P-channel MOS transistor T1 becomes conductive after N-channel MO3 transistor T2 becomes non-conductive. As a result, during switching when the output OUT changes from LOW to HIGH, there is no period during which the P-channel type MO3 transistor T1 and the N-channel type MoS transistor T2 are simultaneously conductive, so there is no through current flowing from the power supply potential to the ground potential.

次に、入力ＩＮがＬＯＷからＨＩＧＨへと変化する時、
上記の説明と同様に考えるとノードＮ２はノードＮ３よ
り先にＨＩＧＨになる為、Ｐチャネル型ＭＯ８トランジ
スタＴ１とＮチャネル型トランジスタＴ２が同時に導通
する期間が存在しない為に電源電位から接地電位へと流
れる貫通電流はなくなる。Next, when the input IN changes from LOW to HIGH,
Thinking in the same way as the above explanation, since node N2 becomes HIGH before node N3, there is no period in which P-channel type MO8 transistor T1 and N-channel type transistor T2 are conductive at the same time, so the power supply potential changes from the power supply potential to the ground potential. No through current flows.

第２図は本発明の第２の実施例の回路図である。FIG. 2 is a circuit diagram of a second embodiment of the invention.

本実施例では遅延素子を１つと４つのトランスミッショ
ンゲートで構成している。第１の実施例と同様に入力Ｉ
ＮとＰチャネル型ＭｏＳトランジスタＴ１５、及びＮチ
ャネル型ＭＯＳトランジスタＴ１６のゲート電極との間
を遅延素子を通して接続するかトランスミッションゲー
トを通して接続するかを入力ＩＮの電圧レベルによって
選択している０本実施例においても実施例１と同様の効
果が得られる。しかし、遅延素子は通常そのレイアウト
面積が大きい為、遅延素子の数を１つにする事は占有面
積が小さくてすむという集積回路に有利な点がある。In this embodiment, one delay element and four transmission gates are used. As in the first embodiment, the input I
This embodiment selects whether to connect between the N and the gate electrodes of the P-channel type MoS transistor T15 and the N-channel type MOS transistor T16 through a delay element or through a transmission gate, depending on the voltage level of the input IN. The same effect as in Example 1 can also be obtained. However, since delay elements usually have a large layout area, reducing the number of delay elements to one is advantageous for integrated circuits in that the area occupied is small.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はＣＭＯＳインバータ回路が
スイッチングする時に電源電位と接地電位との間に直列
に接続されたＰチャネル型ＭＯＳトランジスタと、Ｎチ
ャネル型ＭＯＳトランジスタを遅延素子とトランスミッ
ションゲートを用いる事により同時に導通しない様にし
て電源電位と接地電位との間の貫通電流を阻止し、消費
電流を減少せしめる効果があるとともに電源電位及び接
地電位に発生するノイズをも除去できるという効果があ
る。As explained above, the present invention uses a P-channel MOS transistor and an N-channel MOS transistor connected in series between a power supply potential and a ground potential, a delay element, and a transmission gate when a CMOS inverter circuit switches. This has the effect of preventing conduction at the same time, thereby blocking a through current between the power supply potential and the ground potential, reducing current consumption, and also eliminating noise generated at the power supply potential and the ground potential.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例を示す回路図、第２図は
本発明の第２の実施例を示す回路図、第３図は従来の一
例を示す回路図である。 ＩＮ・・・入力、ＯＵＴ・・・出力、Ｔ、、Ｔ４．Ｔ６
・Ｔフ・Ｔ９・Ｔ目・Ｔ１４・Ｔ１５・Ｔ　、、−Ｐチ
ャネル型ＭＯＳトランジスタ、Ｔ２．Ｔ、、Ｔ、。 Ｔ８・ＴｌＯ・Ｔ１２・Ｔ１３・Ｔ１６・Ｔ１８°−Ｎ
チャネル型ＭＯＳトランジスタ、Ｄ１〜Ｄ３・・・遅延
素子、Ｎ１〜Ｎ７・・・ノード、Ｇｌ、Ｇ２・・・イン
バータ。FIG. 1 is a circuit diagram showing a first embodiment of the invention, FIG. 2 is a circuit diagram showing a second embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional example. IN...Input, OUT...Output, T,, T4. T6
・Tf・T9・Tth・T14・T15・T ,, -P channel type MOS transistor, T2. T,,T,. T8・TlO・T12・T13・T16・T18°-N
Channel type MOS transistor, D1-D3...delay element, N1-N7...node, Gl, G2...inverter.

Claims (1)

【特許請求の範囲】[Claims] 第１の電圧源と第２の電圧源との間にＰチャネル型ＭＯ
ＳトランジスタとＮチャネル型ＭＯＳトランジスタを直
列に接続してなるＣＭＯＳインバータ回路の、前記Ｐチ
ャネル型及び前記Ｎチャネル型ＭＯＳトランジスタをス
イッチング時に同時に導通させない様に前記Ｐチャネル
型及び前記Ｎチャネル型ＭＯＳトランジスタのゲートを
制御せしめる回路を含むことを特徴とするＣＭＯＳイン
バータ回路。A P-channel type MO is connected between the first voltage source and the second voltage source.
In a CMOS inverter circuit formed by connecting an S transistor and an N channel MOS transistor in series, the P channel type and the N channel type MOS transistor are arranged so that the P channel type and the N channel type MOS transistor are not rendered conductive at the same time during switching. A CMOS inverter circuit comprising a circuit for controlling a gate of a CMOS inverter circuit.
JP63277858A 1988-11-01 1988-11-01 Cmos inverter circuit Pending JPH02123826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63277858A JPH02123826A (en) 1988-11-01 1988-11-01 Cmos inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63277858A JPH02123826A (en) 1988-11-01 1988-11-01 Cmos inverter circuit

Publications (1)

Publication Number Publication Date
JPH02123826A true JPH02123826A (en) 1990-05-11

Family

ID=17589264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63277858A Pending JPH02123826A (en) 1988-11-01 1988-11-01 Cmos inverter circuit

Country Status (1)

Country Link
JP (1) JPH02123826A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0514170A (en) * 1991-06-28 1993-01-22 Kawasaki Steel Corp Output buffer circuit
US5670899A (en) * 1994-11-21 1997-09-23 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
US6046607A (en) * 1994-11-21 2000-04-04 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
US7302791B2 (en) 2004-09-02 2007-12-04 Honda Motor Co., Ltd. Lawn mower

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0514170A (en) * 1991-06-28 1993-01-22 Kawasaki Steel Corp Output buffer circuit
US5670899A (en) * 1994-11-21 1997-09-23 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
US6046607A (en) * 1994-11-21 2000-04-04 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
US7302791B2 (en) 2004-09-02 2007-12-04 Honda Motor Co., Ltd. Lawn mower

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