JPH0194657A - Electrode and wiring for semiconductor device - Google Patents

Electrode and wiring for semiconductor device

Info

Publication number
JPH0194657A
JPH0194657A JP25148887A JP25148887A JPH0194657A JP H0194657 A JPH0194657 A JP H0194657A JP 25148887 A JP25148887 A JP 25148887A JP 25148887 A JP25148887 A JP 25148887A JP H0194657 A JPH0194657 A JP H0194657A
Authority
JP
Japan
Prior art keywords
layer
tungsten
wiring
electrode
metals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25148887A
Other languages
Japanese (ja)
Inventor
Naoki Yamamoto
直樹 山本
Yoshio Honma
喜夫 本間
Takashi Nishida
西田 高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP25148887A priority Critical patent/JPH0194657A/en
Publication of JPH0194657A publication Critical patent/JPH0194657A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent peeling off of W or Mo and to further prevent increase in contact resistance between an electrode and a diffusion layer by depositing W or Mo on a layer in which metals of groups IVa, Va and VIa, or metals such as Co, Ni or the silicides thereof are nitrided. CONSTITUTION:Tungsten or molybdenum layer 8 is deposited by a chemical vapor deposition (CVD) method on a layer 7 in which metals belonging to groups IVa, Va and VIa in the periodic table, metals such as cobalt or nickel or the silicides thereof are nitrided, and these layers are provided with desired profiles. For example, a p<+>-diffusion layer 3 and n<+>-diffusion layer 4 are formed within an n-well 1 and a p-well 2 which have been arranged on a silicon substrate, and then a silicon oxide containing boron and phosphorus is deposited as an interlayer insulating film 6. Then after forming a contact hole in the insulating film 6, titanium nitride 7 is deposited on the diffusion layers and insulating film 6 within the contact hole. Then after depositing tungsten 8 by the CVD method, a tungsten layer 8 and a titanium nitride layer 7 are formed to provide an electrode and wiring.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用電極配線に係り、特に化学気相成
長法により形成するタングステンおよびモリブデンに好
適な電極配線に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to electrode wiring for semiconductor devices, and particularly to electrode wiring suitable for tungsten and molybdenum formed by chemical vapor deposition.

[従来の技術〕 超高集積回路用微細電極、配線として、広く用いられて
きたAfl系配線にかわり、微細加工性、耐久耐ストレ
スマイグレーションおよび耐エレクトロマイグレーショ
ン性に優れたタングステンおよびモリブデン電極、配線
が注目されている。従来、素子段差上での被覆性の良い
特長に着目し、化学気相成長法によりシリコンおよび絶
縁物層上に直接該金属を堆積し電極・配線を形成する方
法が試みられている。それらについてはイクステンデイ
ド アブストラクト オン ザ 18 (1986イン
ターナシヨナル)コンファレンス オン ソリッド ス
テート デバイシイズ アンド マテリアルズ A−1
0−3,(1986年)第499頁から502頁(Ex
tended AbStracts of thel 
8th (1986International) C
onferenceon 5olid 5tate D
evices and Materials Toky
o 。
[Prior art] Tungsten and molybdenum electrodes and wiring, which have excellent microfabriability, durable stress migration resistance, and electromigration resistance, have been developed to replace Afl-based wiring, which has been widely used as fine electrodes and wiring for ultra-highly integrated circuits. Attention has been paid. Conventionally, focusing on the feature of good coverage over device steps, attempts have been made to deposit the metal directly on silicon and insulating layers by chemical vapor deposition to form electrodes and wiring. About them, see Extended Abstracts on the 18th (1986 International) Conference on Solid State Devices and Materials A-1.
0-3, (1986) pp. 499-502 (Ex
tended AbStracts of thel
8th (1986 International) C
onference 5olid 5tate D
evices and Materials Tokyo
o.

1986、A−10−3,PP499−502゜198
6に詳しく述べられている。
1986, A-10-3, PP499-502゜198
6 is described in detail.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術はシリコン半導体装置に設けられているシ
リコン酸化物、りん硅酸ガラスあるいはボロン−りん硅
酸ガラスなど絶縁物上へのタングステンあるいはモリブ
デンの堆積が難しく、また堆積した場合においても、該
金属は上記絶縁物に対する接着力が弱く、半導体製造工
程で剥離するという問題があった。また該金属からなる
電極、配線においては、800〜1000℃の高温熱処
理工程で、りんあるいはボロンを含有した絶縁層からこ
れら元素が容易に該金属層内を拡散し、該金属とシリコ
ン層接触部の導通不良を生じるという問題があった。た
とえばタングステン電極とp十拡散層との接触部では、
絶縁膜中のりんがダンゲステン層を経由し、p十拡散層
まで到達し。
In the above conventional technology, it is difficult to deposit tungsten or molybdenum on insulators such as silicon oxide, phosphosilicate glass, or boron-phosphosilicate glass provided in silicon semiconductor devices, and even if tungsten or molybdenum is deposited, the metal has a problem in that it has a weak adhesion to the above-mentioned insulator and peels off during the semiconductor manufacturing process. In addition, in electrodes and wiring made of the metal, during a high-temperature heat treatment process at 800 to 1000°C, these elements easily diffuse into the metal layer from the insulating layer containing phosphorus or boron, and the metal layer contacts the silicon layer. There was a problem in that poor conduction occurred. For example, at the contact part between the tungsten electrode and the p-type diffusion layer,
Phosphorus in the insulating film passes through the Dungesten layer and reaches the p-type diffusion layer.

電極−拡散層間絶縁抵抗を10″″δΩ・口から10−
8Ω・■まで増大させた。さらに、該金属からなる電極
・配線においては、熱処理により金属とシリコン層が容
易に反応し、反応に伴う体積収縮のため反応層が剥離す
るため、電極形式後約600℃以上の熱処理をほどこせ
ないという問題があった。
Insulation resistance between electrode and diffusion layer is 10""δΩ・10-
It was increased to 8Ω・■. Furthermore, in electrodes and wiring made of these metals, the metal and silicon layer easily react with each other due to heat treatment, and the reaction layer peels off due to volumetric contraction accompanying the reaction. The problem was that there was no.

本発明の目的は上記技術の問題点を解決したタングステ
ンあるいはモリブデン電極・配線を実現することにある
An object of the present invention is to realize a tungsten or molybdenum electrode/wiring that solves the problems of the above technology.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、シリコン層および絶縁層上にN a 。 The above purpose is to deposit N a on the silicon layer and the insulating layer.

Va、VIa族およびコバルト、テラケルなどの遷移金
属あるいはそれらのシリコン化合物を窒化物なしめた層
をあらかじめ形成した後、その上に化学蒸着法によりタ
ングステンあるいはモリブデンを堆積し、該金属と上記
窒化物を所望の電極・配線形状に加工することにより、
達成される。
After forming in advance a nitride layer of transition metals such as Va, Group VIa, cobalt, and teracel, or their silicon compounds, tungsten or molybdenum is deposited thereon by chemical vapor deposition, and the metal and the nitride are deposited thereon by chemical vapor deposition. By processing the into the desired electrode/wiring shape,
achieved.

〔作用〕[Effect]

該金属窒化物層はスパッタ法により所望窒化物からなる
スパッタ・ターゲットを用いて形成することができる。
The metal nitride layer can be formed by a sputtering method using a sputter target made of a desired nitride.

また所定金属あるいはシリコン化合物ターゲットを用い
、−坦これらの層を形成した後、窒素ガスもしくはアン
モニアガス雰囲気で熱処理することにより金属窒化物が
得られる。またスパッタ法により形成した膜は、その形
成状件を最適化することにより絶縁物に対し強力な接着
力を有するようにできる。なおIVa族金属あるいはそ
の化合物はシリコン酸化物系絶縁膜に対する接着力が強
いため、化学気相成長法により形成しても絶縁物層から
剥離することはない。このような金属窒化物膜上に化学
気相成長法で形成したタングステンおよびモリブデンは
接着力が強いため、従来技術の欠点であったこれら金属
からなる電極・配線の剥離の問題を生じない。また該金
属窒化物では、それを構成する金属あるいはシリコン化
合物と比較し、りんおよびボロンの拡散速度が1〜4桁
小さい。このため、該窒化物はりん、ボロン含有シリコ
ン酸化物からりん、ボロンのタングステンおよびモリブ
デン層への拡散の障壁となり、電極−拡散層間接触抵抗
の熱処理による増大を防止することができる。
Further, a metal nitride can be obtained by forming a planarized layer using a specified metal or silicon compound target and then heat-treating it in a nitrogen gas or ammonia gas atmosphere. Furthermore, a film formed by sputtering can be made to have strong adhesion to an insulator by optimizing its formation conditions. Note that since the IVa group metal or its compound has a strong adhesive force to the silicon oxide insulating film, it will not peel off from the insulating layer even if it is formed by chemical vapor deposition. Since tungsten and molybdenum formed by chemical vapor deposition on such a metal nitride film have strong adhesive strength, the problem of peeling off of electrodes and wiring made of these metals, which was a drawback of the prior art, does not occur. Further, in the metal nitride, the diffusion rate of phosphorus and boron is 1 to 4 orders of magnitude lower than that of the metal or silicon compound that constitutes the metal nitride. Therefore, the nitride acts as a barrier to diffusion of phosphorus and boron from the silicon oxide containing phosphorus and boron into the tungsten and molybdenum layers, and can prevent an increase in contact resistance between the electrode and the diffusion layer due to heat treatment.

さらに、タングステンおよびモリブデン層とシリコン層
間に該金属窒化物層を設けることにより900〜100
0℃の高温熱処理によっても該金属層とシリコン層の反
応を抑止できる。これは1000℃程度の高温熱処理を
経ても、該金属窒化物がシリコンおよびタングステン、
そしてモリブデンと急激な反応を生じないためである。
Furthermore, by providing the metal nitride layer between the tungsten and molybdenum layers and the silicon layer,
The reaction between the metal layer and the silicon layer can also be suppressed by high-temperature heat treatment at 0°C. This shows that even after high-temperature heat treatment of about 1000°C, the metal nitride remains intact with silicon and tungsten.
This is to prevent a rapid reaction with molybdenum.

〔実施例〕〔Example〕

以下、本発明の実施例を第1図により説明する。 Embodiments of the present invention will be described below with reference to FIG.

[実施例1コ シリコン基板に設けられたnウェル1yPウエル2内の
所定領域にボロンを拡散したp十拡散層3およびひ素を
拡散したn十拡散層4を形成し、次に層間絶縁膜層6と
して、ボロンを10mo1%。
[Example 1] A p-diffusion layer 3 in which boron is diffused and an n-diffusion layer 4 in which arsenic is diffused are formed in a predetermined region in an n-well 1yP-well 2 provided in a silicon substrate, and then an interlayer insulating film layer 6 is formed. As, boron is 10mo1%.

りんを5mo1%含有したシリコン酸化物を600nm
堆積した後、900℃、30分の窒素雰囲気中熱処理を
行なった0次にホトリソグラフィ技術、ドライエツチン
グ技術により0.5μmから1.0μm径のコンタクト
孔を絶縁膜に開けた後、窒素ガスによりチタンターゲッ
トからチタンをスパッタ法により飛翔させ、コンタク孔
内の拡散層および上記絶縁膜上にチタン窒化物7を11
00n堆積した。
600nm silicon oxide containing 5mol1% phosphorus
After the deposition, a contact hole with a diameter of 0.5 μm to 1.0 μm was opened in the insulating film using 0-order photolithography technology and dry etching technology. Titanium is sputtered from a titanium target, and titanium nitride 7 is deposited on the diffusion layer in the contact hole and on the insulating film.
00n was deposited.

次に上記試料を化学気相成長装置の反応用真空室内に装
填し300℃に加熱した後、真空室内にタングステン弗
化物ガスと水素を導入し、それらのガスを化学反応させ
、試料上に500nmのタングステン8を堆積した。こ
のように形成したタングステンとチタン窒化物層を通常
のホトリソグラフイ技術とイオウ弗化物を主成分とした
反応ガスを用いた異方性ドライエツチング技術により電
極・配線形状に加工した。最後にアルゴンガス中で、9
50℃、30分の熱処理を行ない半導体装置を作製した
。この装置作製過程の熱処理工程でタングステンの剥離
は生せず、チタン窒化物とタングステンおよびシリコン
基板との顕著な反応は観察されなかった。またタングス
テン電極・配線とn+およびp十拡散層間の接触抵抗は
ともに5×10−7Ω・d以下と良好な値を示し、オー
ミック特性を示した。これはチタン窒化物のりん、ボロ
ン含有シリコン酸化物からタングステン層への不純物拡
散に対する障壁効果による。なお上記チタン窒化物のか
わりにジルコニウム、ハフニウム。
Next, the above sample was loaded into a reaction vacuum chamber of a chemical vapor deposition apparatus and heated to 300°C, and then tungsten fluoride gas and hydrogen were introduced into the vacuum chamber to cause a chemical reaction between the gases and form a 500 nm layer on the sample. of tungsten 8 was deposited. The tungsten and titanium nitride layers thus formed were processed into electrode/wiring shapes using conventional photolithography and anisotropic dry etching using a reactive gas containing sulfur fluoride as a main component. Finally, in argon gas, 9
A semiconductor device was manufactured by performing heat treatment at 50° C. for 30 minutes. No peeling of tungsten occurred during the heat treatment step of this device fabrication process, and no significant reaction between titanium nitride, tungsten, and the silicon substrate was observed. Further, the contact resistance between the tungsten electrode/wiring and the n+ and p+ diffusion layers both showed good values of 5×10 −7 Ω·d or less, indicating ohmic characteristics. This is due to the barrier effect of titanium nitride against impurity diffusion from the phosphorus- and boron-containing silicon oxide to the tungsten layer. Note that zirconium or hafnium is used instead of the titanium nitride mentioned above.

タンタルバナジウム、ニオビウムの窒化物についても同
様の実験を試みた結果、はとんど同様の効果が得られた
Similar experiments were conducted with tantalum vanadium and niobium nitrides, and almost the same effect was obtained.

[実施例2] 本実例では実施例1のタングステンのかわりに、モリブ
デン塩化物源を用い化学気相成長法により、モリブデン
暎8を金属窒化物7上に堆積した。窒化物としてはコバ
ルトを50nmスパッタ法で堆積した後、アンモニアガ
ス雰囲気中で熱処理し、コバルト窒化物を形成した。電
極・配線形成にあたっては、レジストをマスクとし、イ
オウ弗化物ガスを用いた異方性ドライエツチング技術に
より、まずモリブデン層を加工した。次に、これらをマ
スクとして、イオンシリング装置を用い、モリブデン層
と同一の形状にコバルト窒化物を加工し、電極・配線と
した。本実施例のコバルト窒化物も実施例1と同様の効
果を示した。またニッケル窒化物を同様の方法で形成し
、本発明の効果を確認した。がお、スパッタ法で形成し
たクロム、タングステン、モリブデンの窒化物は本実施
例と同様アンモニアガス熱処理により形成したが、その
電極・配線への加工は、その上に化学気相成長法で形成
したモリブデンあるいはタングステンと同時に加工した
[Example 2] In this example, molybdenum chloride 8 was deposited on metal nitride 7 by chemical vapor deposition using a molybdenum chloride source instead of tungsten in Example 1. As the nitride, cobalt was deposited to a thickness of 50 nm by sputtering, and then heat treated in an ammonia gas atmosphere to form cobalt nitride. To form electrodes and wiring, the molybdenum layer was first processed using an anisotropic dry etching technique using sulfur fluoride gas using a resist as a mask. Next, using these as masks, cobalt nitride was processed into the same shape as the molybdenum layer using an ion silling device to form electrodes and wiring. The cobalt nitride of this example also showed the same effect as Example 1. Further, nickel nitride was formed using the same method, and the effects of the present invention were confirmed. However, the chromium, tungsten, and molybdenum nitrides formed by the sputtering method were formed by ammonia gas heat treatment as in this example, but the electrodes and wiring were formed on them by chemical vapor deposition. Processed at the same time as molybdenum or tungsten.

〔発明の効果〕〔Effect of the invention〕

本発明によれば半導体装置上に化学的気相成長法により
形成したタングステンあるいはモリブデンの剥離を防止
でき、また層間絶縁膜およびシリコン基板内拡散層に含
有させたボロン、りん不純物の該金属内への拡散を抑止
できるため、電極−拡散層間の接触抵抗増大を防止でき
る効果がある。
According to the present invention, it is possible to prevent tungsten or molybdenum formed on a semiconductor device by chemical vapor deposition from peeling off, and also to prevent boron and phosphorus impurities contained in the interlayer insulating film and the diffusion layer in the silicon substrate from penetrating into the metal. This has the effect of preventing an increase in contact resistance between the electrode and the diffusion layer.

さらに金属窒化物とシリコン層は1000℃程度の高温
まで顕著な反応を示さないため、タングステンあるいは
モリブデン電極・配線を用いた半導体装置作製において
も、高温熱処理工程が可能となり、製造プロセスの自由
度が向上するという効果がある。
Furthermore, since metal nitrides and silicon layers do not show any noticeable reaction up to high temperatures of around 1000°C, high-temperature heat treatment becomes possible even in the production of semiconductor devices using tungsten or molybdenum electrodes and wiring, increasing the flexibility of the manufacturing process. It has the effect of improving.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す断面図である。 1・・・Si基板に設けられたn型ウェル、2・・・p
型ウェル、3・・・p十拡散層、4・・・n÷拡散層、
5・・・素子間分離絶縁膜、6・・・層間絶縁膜、7・
・・金属窒化物層、8・・・化学気相成長法により形成
したタンーテ゛9 う /、、、fl’!l−ウェル 8・−・ル砧方薯讐寄讐°゛
FIG. 1 is a sectional view showing an embodiment of the present invention. 1... n-type well provided in Si substrate, 2... p
type well, 3...p + diffusion layer, 4...n÷diffusion layer,
5... Inter-element isolation insulating film, 6... Interlayer insulating film, 7.
...Metal nitride layer, 8... tandem layer formed by chemical vapor deposition method 9 u/,,,fl'! l-well 8...

Claims (1)

【特許請求の範囲】[Claims] 1、元素同期律表のIVa、Va、VIa族に属する金属、
ならびにコバルト、ニッケルなどの金属あるいはそれら
のシリコン化合物を窒化物ならしめ層上に化学的気相成
長法によりタングステンもしくはモリブデンを堆積し、
これらの層を所望の形状に加工したことを特徴とする半
導体装置用電極・配線。
1. Metals belonging to groups IVa, Va, and VIa of the element synchronization table,
In addition, metals such as cobalt and nickel or their silicon compounds are made into nitrides, and tungsten or molybdenum is deposited by chemical vapor deposition on the layer.
An electrode/wiring for a semiconductor device characterized by processing these layers into a desired shape.
JP25148887A 1987-10-07 1987-10-07 Electrode and wiring for semiconductor device Pending JPH0194657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25148887A JPH0194657A (en) 1987-10-07 1987-10-07 Electrode and wiring for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25148887A JPH0194657A (en) 1987-10-07 1987-10-07 Electrode and wiring for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0194657A true JPH0194657A (en) 1989-04-13

Family

ID=17223547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25148887A Pending JPH0194657A (en) 1987-10-07 1987-10-07 Electrode and wiring for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0194657A (en)

Cited By (7)

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JPH03175626A (en) * 1989-12-04 1991-07-30 Nmb Semiconductor:Kk Ic and its manufacture
US6197702B1 (en) 1997-05-30 2001-03-06 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US7049187B2 (en) 2001-03-12 2006-05-23 Renesas Technology Corp. Manufacturing method of polymetal gate electrode
US7053459B2 (en) 2001-03-12 2006-05-30 Renesas Technology Corp. Semiconductor integrated circuit device and process for producing the same
US7221056B2 (en) 2003-09-24 2007-05-22 Renesas Technology Corp. Semiconductor integrated circuit device and manufacturing method thereof
WO2021166935A1 (en) 2020-02-17 2021-08-26 保土谷化学工業株式会社 Organic electroluminescent element
KR20210143110A (en) 2020-05-19 2021-11-26 도쿄엘렉트론가부시키가이샤 Film forming method and film forming apparatus

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JPH03175626A (en) * 1989-12-04 1991-07-30 Nmb Semiconductor:Kk Ic and its manufacture
US7122469B2 (en) 1997-05-30 2006-10-17 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US6503819B2 (en) 1997-05-30 2003-01-07 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US6528403B2 (en) 1997-05-30 2003-03-04 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US6784116B2 (en) 1997-05-30 2004-08-31 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US6987069B2 (en) 1997-05-30 2006-01-17 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US6197702B1 (en) 1997-05-30 2001-03-06 Hitachi, Ltd. Fabrication process of a semiconductor integrated circuit device
US7053459B2 (en) 2001-03-12 2006-05-30 Renesas Technology Corp. Semiconductor integrated circuit device and process for producing the same
US7049187B2 (en) 2001-03-12 2006-05-23 Renesas Technology Corp. Manufacturing method of polymetal gate electrode
US7144766B2 (en) 2001-03-12 2006-12-05 Renesas Technology Corp. Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode
US7300833B2 (en) 2001-03-12 2007-11-27 Renesas Technology Corp. Process for producing semiconductor integrated circuit device
US7375013B2 (en) 2001-03-12 2008-05-20 Renesas Technology Corp. Semiconductor integrated circuit device and process for manufacturing the same
US7632744B2 (en) 2001-03-12 2009-12-15 Renesas Technology Corp. Semiconductor integrated circuit device and process for manufacturing the same
US7221056B2 (en) 2003-09-24 2007-05-22 Renesas Technology Corp. Semiconductor integrated circuit device and manufacturing method thereof
WO2021166935A1 (en) 2020-02-17 2021-08-26 保土谷化学工業株式会社 Organic electroluminescent element
KR20210143110A (en) 2020-05-19 2021-11-26 도쿄엘렉트론가부시키가이샤 Film forming method and film forming apparatus
US11549179B2 (en) 2020-05-19 2023-01-10 Tokyo Electron Limited Film forming method

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