JPH0132364Y2 - - Google Patents
Info
- Publication number
- JPH0132364Y2 JPH0132364Y2 JP1985030456U JP3045685U JPH0132364Y2 JP H0132364 Y2 JPH0132364 Y2 JP H0132364Y2 JP 1985030456 U JP1985030456 U JP 1985030456U JP 3045685 U JP3045685 U JP 3045685U JP H0132364 Y2 JPH0132364 Y2 JP H0132364Y2
- Authority
- JP
- Japan
- Prior art keywords
- crystallized glass
- gold
- eutectic solder
- substrate
- terminal portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011521 glass Substances 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 230000005496 eutectics Effects 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 claims description 4
- 238000005219 brazing Methods 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 5
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- -1 AI 2 O 3 Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Description
【考案の詳細な説明】
「産業上の利用分野」
本考案は、数ＧHzオーダーの高周波領域で超高
速用ICパツケージとして好適に利用される。[Detailed Description of the Invention] "Industrial Application Field" The present invention is suitably used as an ultra-high-speed IC package in a high frequency region on the order of several GHz.
「従来の技術」
GaAs，Ge等の半導体素子を収納する超高速用
ICパツケージの基板には、機械的強度、電気絶
縁性、気密性等において高信頼性が要求されるこ
とから、その材質としてアルミナ、ベリリヤ等の
セラミツクスが用いられている。而して該基板の
外表面には導体材料よりなる端子部が設けられて
おり、この端子部に通常銀ろう又は銀−銅共晶ろ
うを用いて800℃以上の高温でろう付接合し、後
工程で半導体素子を装着し気密封止して完成され
る。"Conventional technology" For ultra-high speed applications that house semiconductor elements such as GaAs and Ge.
Since IC package substrates are required to have high reliability in terms of mechanical strength, electrical insulation, airtightness, etc., ceramics such as alumina and beryllia are used as the material. A terminal portion made of a conductive material is provided on the outer surface of the substrate, and this terminal portion is usually soldered to the terminal portion using silver solder or silver-copper eutectic solder at a high temperature of 800°C or higher. In the post-process, semiconductor elements are attached and hermetically sealed.
「考案が解決しようとする問題点」
数ＧHzオーダーの高周波領域で使用する場合、
誘電率の高いアルミナやベリリヤでは信号伝播速
度に限界があり、近年の使用帯域の高周波化傾向
に適さない。そこで出願人は低誘電率でしかも易
焼結性のSiO2−Al2O3−MgO−ZnO系結晶化ガラ
ス体を基板等に利用することを提案し、その組成
を特開昭59−92943号公報に開示した。``Problems that the invention attempts to solve'' When used in the high frequency region of the order of several GHz,
Alumina and Beryllium, which have high dielectric constants, have a limited signal propagation speed, making them unsuitable for the recent trend toward higher frequency bands. Therefore, the applicant proposed the use of SiO 2 -Al 2 O 3 -MgO-ZnO-based crystallized glass, which has a low dielectric constant and is easily sintered, for substrates, etc., and disclosed its composition in JP-A No. 59-92943. It was disclosed in the publication.
しかし、結晶化ガラスはアルミナやベリリヤほ
どに高い機械的強度も耐熱性も有していないた
め、同公報記載の結晶化ガラス体を含めて多くの
結晶化ガラス体は、その表面の端子部に銀ろう等
の高温ろう材で金属リードを接合すると熱膨張差
に起因して接合部に応力歪が生じ、クラツクを生
じ易い。 However, since crystallized glass does not have as high mechanical strength or heat resistance as alumina or beryllia, many crystallized glass bodies, including the crystallized glass body described in the same publication, do not have the terminals on their surfaces. When metal leads are bonded using a high-temperature brazing material such as silver solder, stress strain occurs in the bonded portion due to the difference in thermal expansion, and cracks are likely to occur.
本考案は以上の問題点を解決し、低誘電率でし
かも外部金属リードが良好に接合した超高速用
ICパツケージを提供することを目的とする。 This invention solves the above problems and has a low dielectric constant and a well-bonded external metal lead for ultra-high-speed applications.
The purpose is to provide IC packages.
「問題点を解決するための手段」
基板材質を誘電率6.0以下の結晶化ガラスとし、
端子部と金属リードとの接合用ろう材に金−スズ
共晶ろう又は金−ケイ素共晶ろうを適用する。``Means to solve the problem'' The substrate material is crystallized glass with a dielectric constant of 6.0 or less,
Gold-tin eutectic solder or gold-silicon eutectic solder is used as the brazing material for joining the terminal portion and the metal lead.
「作用」
金−スズ共晶ろう及び金−ケイ素共晶ろうは、
ろう付温度がそれぞれ200〜300℃及び400〜450℃
という低温であることから、接合時の基板との熱
膨張差が少なく、結晶化ガラスにクラツクが生じ
ることがなく且つ強固に接合できる。"Function" Gold-tin eutectic solder and gold-silicon eutectic solder are
Brazing temperature is 200~300℃ and 400~450℃ respectively
Because of this low temperature, the difference in thermal expansion with the substrate during bonding is small, and the crystallized glass is not cracked and can be bonded firmly.
実施例
上記手段において最適な例は、所定含有量の
SiO2，AI2O3，MgO，ZnOよりなる主成分に
B2O3及び／又はP2O5を所定量添加し、結晶化さ
せてなる特開昭59−92943号公報記載の結晶化ガ
ラス体を基板とし、この基板の表面にAu，Cu，
Ag及びPdより選ばれる一種以上の金属を含むペ
ーストを厚膜印刷して端子部とし、この端子部に
Kovar，42alloy，Ｗ又はMoよりなる金属リード
を金−スズ共晶ろう又は金−ケイ素共晶ろうにて
接合する組み合わせである。Example In the above means, the best example is a predetermined content of
The main components are SiO 2 , AI 2 O 3 , MgO, and ZnO.
The crystallized glass body described in JP-A-59-92943, which is obtained by adding a predetermined amount of B 2 O 3 and/or P 2 O 5 and crystallizing it, is used as a substrate, and the surface of this substrate is coated with Au, Cu,
A thick film of paste containing one or more metals selected from Ag and Pd is printed to form a terminal part, and this terminal part is
This is a combination in which metal leads made of Kovar, 42alloy, W, or Mo are joined using gold-tin eutectic solder or gold-silicon eutectic solder.
以下図面にもとづいて具体的に説明する。 A detailed explanation will be given below based on the drawings.
第１図、第２図及び第３図はそれぞれ本考案の
一実施例に係る結晶化ガラスICパツケージの側
面図、平面図及び底面図である。 1, 2, and 3 are a side view, a top view, and a bottom view, respectively, of a crystallized glass IC package according to an embodiment of the present invention.
１はICパツケージを示し、２は基板を示し、
結晶化ガラス成分を樹脂等と共に混練、成形して
なるグリーンシートを温度900〜1000℃で焼成し
て得られ、その誘電率は5.5でその組成は重量基
準でSiO258％、AI2O323％，MgO13％、ZnO4
％、B2O31％及びP2O51％よりなる。３，３…は
端子部を示し、上記グリーンシート上に金ペース
ト（住友金属鉱山(株)製Ｃ−5025）を厚膜印刷後グ
リーンシートと共に同時焼成して得られる。４，
４…４は金−スズ共晶ろうを示す。５，５…５は
Kovarよりなる金属リードを示し、焼成後の基板
２の表面に設けられた端子部３，３…３に金−ス
ズ共晶ろうを用いて温度300℃で基板２にクラツ
クを生じることなく良好に接合されている。この
場合の端子部３，３…３と金属リード５，５…５
との接合強度は１Kg／mm2以上であつた。 1 indicates the IC package, 2 indicates the board,
It is obtained by kneading and molding a crystallized glass component with a resin, etc., and firing a green sheet at a temperature of 900 to 1000°C. Its dielectric constant is 5.5, and its composition is 58% SiO 2 and AI 2 O 3 on a weight basis. 23%, MgO13%, ZnO4
%, B 2 O 3 1% and P 2 O 5 1%. 3, 3, . . . indicate terminal portions, which are obtained by printing a thick film of gold paste (C-5025 manufactured by Sumitomo Metal Mining Co., Ltd.) on the green sheet and then co-firing it together with the green sheet. 4,
4...4 indicates a gold-tin eutectic solder. 5, 5...5 is
A metal lead made of Kovar is shown, and a gold-tin eutectic solder is used for the terminal parts 3, 3...3 provided on the surface of the substrate 2 after firing, so that the substrate 2 can be well bonded at a temperature of 300℃ without causing any cracks. It is joined. In this case, terminal parts 3, 3...3 and metal leads 5, 5...5
The bonding strength with the material was 1 Kg/mm 2 or more.
なお、６は図示しない半導体素子を接合するア
イランド部を示し、端子部３，３…３と同材質よ
りなる。７は半導体素子を装着後、図示しない蓋
体と共に内部を気密封止する枠体を示す。 Note that 6 indicates an island portion to which a semiconductor element (not shown) is bonded, and is made of the same material as the terminal portions 3, 3, . . . 3. Reference numeral 7 denotes a frame whose interior is hermetically sealed together with a lid (not shown) after the semiconductor element is mounted.
「考案の効果」
低誘電率、易焼結性の結晶化ガラスを基板材質
に適用できるので、信号伝播速度が速くなりま
た、Au，Cu等の低抵抗金属を端子部材に適用で
きる。``Effects of the invention'' Since crystallized glass with a low dielectric constant and easy sinterability can be used as the substrate material, the signal propagation speed becomes faster, and low-resistance metals such as Au and Cu can be used as the terminal material.
第１図、第２図及び第３図はそれぞれ本考案の
一実施例に係る結晶化ガラスICパツケージの側
面図、平面図及び底面図である。
1, 2, and 3 are a side view, a top view, and a bottom view, respectively, of a crystallized glass IC package according to an embodiment of the present invention.
Claims (1)
ケージ基板の外表面に導出してなる端子部に金属
リードをろう付接合してなるものにおいて、端子
部と金属リードとの接合用ろう材が金−スズ共晶
ろう又は金−ケイ素共晶ろうであることを特徴と
する結晶化ガラスICパツケージ。 In an IC package made of crystallized glass with a dielectric constant of 6.0 or less, a metal lead is soldered to a terminal portion extending from the outer surface of the substrate, and the brazing material for joining the terminal portion and the metal lead is gold. A crystallized glass IC package characterized by being a tin eutectic solder or a gold-silicon eutectic solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985030456U JPH0132364Y2 (en) | 1985-03-04 | 1985-03-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985030456U JPH0132364Y2 (en) | 1985-03-04 | 1985-03-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61146958U JPS61146958U (en) | 1986-09-10 |
| JPH0132364Y2 true JPH0132364Y2 (en) | 1989-10-03 |
Family
ID=30530170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985030456U Expired JPH0132364Y2 (en) | 1985-03-04 | 1985-03-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0132364Y2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128899A (en) * | 1979-03-23 | 1980-10-06 | Ibm | Method of fabricating glass ceramic structure |
| JPS60170286A (en) * | 1984-02-14 | 1985-09-03 | 富士通株式会社 | Method of producing glass ceramic substrate |
| JPS60198763A (en) * | 1984-03-22 | 1985-10-08 | Nec Corp | Pinned substrate and manufacture thereof |
| JPS60198760A (en) * | 1984-03-22 | 1985-10-08 | Nec Corp | Soldering method |
-
1985
- 1985-03-04 JP JP1985030456U patent/JPH0132364Y2/ja not_active Expired
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128899A (en) * | 1979-03-23 | 1980-10-06 | Ibm | Method of fabricating glass ceramic structure |
| JPS60170286A (en) * | 1984-02-14 | 1985-09-03 | 富士通株式会社 | Method of producing glass ceramic substrate |
| JPS60198763A (en) * | 1984-03-22 | 1985-10-08 | Nec Corp | Pinned substrate and manufacture thereof |
| JPS60198760A (en) * | 1984-03-22 | 1985-10-08 | Nec Corp | Soldering method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61146958U (en) | 1986-09-10 |
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