JPH01315144A - Silicon wafer of excellent gettering capacity and its manufacture - Google Patents
Silicon wafer of excellent gettering capacity and its manufactureInfo
- Publication number
- JPH01315144A JPH01315144A JP7976289A JP7976289A JPH01315144A JP H01315144 A JPH01315144 A JP H01315144A JP 7976289 A JP7976289 A JP 7976289A JP 7976289 A JP7976289 A JP 7976289A JP H01315144 A JPH01315144 A JP H01315144A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon
- substrate
- polycrystalline silicon
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 43
- 239000010703 silicon Substances 0.000 title claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 238000005247 gettering Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 51
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 17
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 25
- 239000002245 particle Substances 0.000 abstract description 9
- 239000007789 gas Substances 0.000 abstract description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 6
- 229910001873 dinitrogen Inorganic materials 0.000 abstract description 6
- 229910001882 dioxygen Inorganic materials 0.000 abstract description 6
- 150000003376 silicon Chemical class 0.000 abstract description 3
- 150000004756 silanes Chemical class 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 46
- 235000012431 wafers Nutrition 0.000 description 39
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 239000012535 impurity Substances 0.000 description 8
- 235000013339 cereals Nutrition 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000000356 contaminant Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 150000003839 salts Chemical class 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- VLTRZXGMWDSKGL-UHFFFAOYSA-N perchloric acid Chemical compound OCl(=O)(=O)=O VLTRZXGMWDSKGL-UHFFFAOYSA-N 0.000 description 2
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- CMMUKUYEPRGBFB-UHFFFAOYSA-L dichromic acid Chemical compound O[Cr](=O)(=O)O[Cr](O)(=O)=O CMMUKUYEPRGBFB-UHFFFAOYSA-L 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、集積回路等の電子デバイスに使用されるゲッ
タリング能力の優れたシリコンウェーハおよびその製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a silicon wafer with excellent gettering ability used for electronic devices such as integrated circuits, and a method for manufacturing the same.
（従来技術および発明が解決しようとする課題）シリコ
ンウエーハ−ヒの集積回路デバイスの製造時に、ウェー
ハのデバイス形成表面近辺に欠陥、汚染物または不純物
が存在するかあるいは導入されると、過度の電流漏れを
生じ、これらは得られる使用可能なデバイスの歩留りに
大きく影響する。PRIOR ART AND PROBLEM TO BE SOLVED BY THE INVENTION During the manufacture of integrated circuit devices on silicon wafers, the presence or introduction of defects, contaminants, or impurities near the device-forming surface of the wafer can cause excessive current flow. leakage, which greatly affects the yield of usable devices obtained.
このｈ−害な欠陥、汚染物および不純物は、ある程度ま
ではデバイス形成領域から基質材料中の無害な領域に再
配置できることが技術上認識されている。デバイスの形
成前および形成中の両方で、活性デバイス領域からこの
欠陥、汚染物および不純物を拡散しかつトラップする方
法および工程を、エレクトロニクス工業技術の分野にお
いてゲッタリングと称する。It is recognized in the art that these harmful defects, contaminants, and impurities can, to some extent, relocate from the device forming region to benign regions in the substrate material. The methods and processes for diffusing and trapping defects, contaminants, and impurities from active device regions both before and during device formation are referred to in the electronics industry as gettering.
このようなゲッタリング能力を付与るために、例えばシ
ランガスの熱分解によりシリコンウェーハの裏面に多結
晶のシリコン層を気相成長させる方法は、公知である（
特開昭５８−１３８．０３５号、同昭５９−１８６，３
３１号および同昭５２−１２０．７７７号）。In order to provide such gettering ability, a method is known in which a polycrystalline silicon layer is grown in a vapor phase on the back surface of a silicon wafer by, for example, thermal decomposition of silane gas (
JP-A-58-138.035, JP-A No. 59-186, 3
No. 31 and No. 1977-120.777).
ところで、多結晶シリコン層によるゲッタリングは、単
結晶シリコン中の不純物が多結晶シリコンの結晶粒界に
トラップされることにより行なわれる。そこで、ゲッタ
リング能力を高めるためには、単結晶シリコン基体に多
結晶シリコン層が密着して形成され、しかも結晶粒界の
面積が大きな多結晶シリコン層であることが要求される
。この結晶粒界の面積を大きくするためには、個々の結
晶粒を小さ（し、しかも粒子の大きさを均一化すること
が望まれる。By the way, gettering by the polycrystalline silicon layer is performed by trapping impurities in the single crystal silicon at the crystal grain boundaries of the polycrystalline silicon. Therefore, in order to improve the gettering ability, it is required that the polycrystalline silicon layer be formed in close contact with the single crystal silicon substrate and that the polycrystalline silicon layer has a large area of crystal grain boundaries. In order to increase the area of this crystal grain boundary, it is desirable to make each crystal grain small (and to make the grain size uniform).
しかるに、特開昭５２−１２０，７７７号に開示れてい
るシリコンウェーハでは、その実施例１において、シリ
コンウェーハの裏面の厚さ２，７００への酸化膜の片側
半分をエッチオフして、該シリコンウェーハの裏面１２
１．６ミクロンの多結晶シリコン膜を堆積させ、ＭＯＳ
キャパシターのリーク電流の減少によってゲッタリング
の効果を評価した結果、酸化膜をエッチオフした側でリ
一り電流が約２桁減少したことが示されている。However, in the silicon wafer disclosed in JP-A-52-120,777, in Example 1, one half of the oxide film on the back side of the silicon wafer is etched off to a thickness of 2,700 mm. Back side 12 of silicon wafer
A 1.6 micron polycrystalline silicon film is deposited and the MOS
The results of evaluating the gettering effect by reducing the leakage current of the capacitor showed that the leakage current was reduced by about two orders of magnitude on the side where the oxide film was etched off.
この実施例１では、明らかにシリコン基体と多結晶シリ
コン膜との間に酸化膜が存在しないことがゲッタリング
効果を付与させるために必要な条件であることが述べら
れている。This Example 1 clearly states that the absence of an oxide film between the silicon substrate and the polycrystalline silicon film is a necessary condition for imparting the gettering effect.
本発明者らは、前記実施例を、つぎの実験により追試し
た。すなわち、シリコンウェーハを１％弗酸に浸漬して
シリコンウェーハ表面上の酸化膜をエッチオフし、シリ
コンの単結晶の表面を露出させた。このウェーハを、表
面に酸化膜が成長しないように、常温で窒素ガスを２０
ρ／分流通させた減圧 Ｃｈｅｍｉｃａｌ ｖａｐｏｒ
ｄｅｐｏｓｉｔｉｏｎ （ＣＶＤ）炉に入れ、その後
、窒素ガスをＱ、５Ω／分流通させながら４０Ｐａに減
圧して温度を常温から６５０°Ｃまで昇温させた。温度
が６５０℃に達した時点で、シランガス０．３５ρ／分
をキャリヤーガスである窒素ガス０．５ｆＪ／分の流れ
とともに流通させてシリコンウェーハの表面上に多結晶
シリコン膜を１２０分間にわたって堆積させた。堆積処
理の終ったシリコンウェーハの表面を金属顕微鏡および
走査電子顕微鏡で調べたところ、シリコンウェーハ表面
上に多結晶シリコン膜が成長しておらず、あるいは成長
しても部分的であった。また、部分的に成長したところ
をよく調べてみると、減圧ＣＶＤ炉中で発生したパーテ
ィクルが付着した部分あるいは弗酸で酸化膜をエラオフ
した時に、液中のパーティクルが付着した部分に多結晶
シリコン膜が成長していることがわかった。この事実は
、つぎのように理解できる。すなわち、表面の酸化膜を
エッチオフし、シリコン単結晶の表面を露出したシリコ
ンウェーハの表面では、ＣＶＤ反応がエピタキシー反応
になるため、多結晶シリコン膜は成長せず、パーティク
ル等のあるところでのみそれが成長核となるので、その
回りの多結晶シリコン膜が島状に成長するのである。The present inventors re-tried the above-mentioned example through the following experiment. That is, the silicon wafer was immersed in 1% hydrofluoric acid to etch off the oxide film on the surface of the silicon wafer, exposing the surface of the silicon single crystal. This wafer was heated with nitrogen gas for 20 minutes at room temperature to prevent an oxide film from growing on the surface.
Reduced pressure chemical vapor flowing at ρ/min
After that, the pressure was reduced to 40 Pa and the temperature was raised from room temperature to 650° C. while flowing nitrogen gas at Q and 5 Ω/min. When the temperature reached 650° C., a polycrystalline silicon film was deposited on the surface of the silicon wafer for 120 minutes by flowing silane gas at 0.35 ρ/min together with a flow of nitrogen gas as a carrier gas at 0.5 fJ/min. Ta. When the surface of the silicon wafer after the deposition process was examined using a metallurgical microscope and a scanning electron microscope, it was found that no polycrystalline silicon film had grown on the surface of the silicon wafer, or even if it had grown, it was only partial. In addition, when we carefully examine the parts where it has grown, we find that polycrystalline silicon is found in areas where particles generated in the low-pressure CVD furnace have adhered, or where particles in the solution have adhered when the oxide film is etched off with hydrofluoric acid. It was found that a film was growing. This fact can be understood as follows. In other words, on the surface of a silicon wafer where the oxide film on the surface has been etched off and the surface of the silicon single crystal is exposed, the CVD reaction becomes an epitaxial reaction, so a polycrystalline silicon film does not grow, but only where there are particles, etc. serves as a growth nucleus, and the polycrystalline silicon film around it grows in an island shape.
また、特開昭５８−１３８，０３５号に記載の方法では
、多結晶シリコン層は、単結晶シリコン基体の裏面に直
接形成されるので、前記のごときゲッタリング能力は未
だ充分ではない。Furthermore, in the method described in JP-A-58-138,035, the polycrystalline silicon layer is formed directly on the back surface of the single-crystal silicon substrate, so the gettering ability as described above is not yet sufficient.
さらに、特開昭５９−１８６，３３１号の方法では、単
結晶シリコン基の裏面に形成されている多結晶シリコン
層が酸素でドープされているが、この酸素ドー°プは、
多結晶シリコン層によるゲッタリング効果をむしろ損っ
ているのである。Furthermore, in the method of JP-A-59-186,331, the polycrystalline silicon layer formed on the back surface of the single crystal silicon base is doped with oxygen;
This actually impairs the gettering effect of the polycrystalline silicon layer.
したがって、本発明の一目的は、ゲッタリング能力の優
れたシリコンウェーハおよびその製造方法を提供するこ
とにある。Therefore, one object of the present invention is to provide a silicon wafer with excellent gettering ability and a method for manufacturing the same.
（課題を解決するための手段）
上記目的は、単結晶シリコン基体と、該基体の−ｈ″の
表面に形成された厚さ１〜８への酸化シリコン膜と、該
酸化シリコン膜上に形成された多結晶シリコン層とより
なるゲッタリング能力の優れたシリコンウェーハにより
達成される。(Means for Solving the Problems) The above object includes a single crystal silicon substrate, a silicon oxide film formed on the -h'' surface of the substrate to a thickness of 1 to 8, and a silicon oxide film formed on the silicon oxide film. This is achieved using a silicon wafer with excellent gettering ability made of a polycrystalline silicon layer.
［ユ記目的は、単結晶シリコン基体の少なくとも一方の
表面を酸化して厚さ１〜８への酸化シリコン膜を形成さ
せ、かつ該酸化シリコン膜をガス状シラン類と加熱下に
接触させて該酸化シリコン膜上に多結晶シリコン層を形
成させることを特徴とするゲッタリング能力の優れたシ
リコンウェーハの製造方法により達成させる。[The purpose of this article is to oxidize at least one surface of a single crystal silicon substrate to form a silicon oxide film with a thickness of 1 to 8, and to contact the silicon oxide film with a gaseous silane under heating. This is achieved by a method for manufacturing a silicon wafer with excellent gettering ability, which is characterized by forming a polycrystalline silicon layer on the silicon oxide film.
（作用）
本発明によるゲッタリング能力の優れたシリコンウェー
ハは、単結晶基体と、該基体の一方の表面に形成された
厚さ１〜８への酸化シリコン膜と、該酸化シリコン膜上
に形成された多結晶シリコン層とよりなるものである。(Function) The silicon wafer with excellent gettering ability according to the present invention includes a single crystal substrate, a silicon oxide film with a thickness of 1 to 8 formed on one surface of the substrate, and a silicon oxide film formed on the silicon oxide film. It consists of a polycrystalline silicon layer.
本発明で使用される単結晶シリコン基板は、単結晶基板
の表面をラッピングし、ついでケミカルエツチング処理
をして数十ミクロン以下の表面層をエツチング除去する
ことにより表面研磨されて゛なるもので表面研磨後の基
板の厚さは２００〜２゜０００ミクロン、好ましくは３
００〜１． ０００ミクロンである。The single-crystal silicon substrate used in the present invention is surface-polished by lapping the surface of the single-crystal substrate, followed by chemical etching to remove the surface layer of several tens of microns or less. The thickness of the subsequent substrate is between 200 and 2000 microns, preferably 3
00-1. 000 microns.
この単結晶シリコン基体の表面に形成される酸化シリコ
ン膜の厚さは１〜８人、好ましくは１〜５八である。す
なわち、Ｉへ以上の厚みを持つ酸化シリコン膜が単結晶
シリコン基体の表面に形成されると、その上に形成され
る多結晶シリコン層が単結晶シリコン基体の全面にわた
って均一にかつ高い密着性で形成される。この酸化シリ
コン膜の厚みが１八未満であると、その上に形成される
多結晶シリコン層が不均一に形成され、しかも密着力が
低下し、しかも多結晶シリコン層の結晶粒が大き（なる
。他方、酸化シリコン膜の厚みが８八を越えると、単結
晶シリコン基体中の不純物が多結晶シリコン層中に移動
する際に、酸化シリコン膜が障害となってゲッタリング
能力を低下させる。この点から、酸化シリコン膜の厚み
は１〜８Ａが望ましい。The thickness of the silicon oxide film formed on the surface of this single-crystal silicon substrate is 1 to 8 thick, preferably 1 to 58 thick. In other words, when a silicon oxide film with a thickness greater than I is formed on the surface of a single-crystal silicon substrate, the polycrystalline silicon layer formed thereon has uniform and high adhesion over the entire surface of the single-crystal silicon substrate. It is formed. If the thickness of this silicon oxide film is less than 18 cm, the polycrystalline silicon layer formed on it will be formed non-uniformly, the adhesion will be reduced, and the crystal grains of the polycrystalline silicon layer will become large ( On the other hand, if the thickness of the silicon oxide film exceeds 88 mm, the silicon oxide film becomes an obstacle when the impurities in the single crystal silicon substrate move into the polycrystalline silicon layer, reducing the gettering ability. From this point of view, the thickness of the silicon oxide film is preferably 1 to 8 Å.
単結晶シリコン基体の表面に酸化シリコン膜を形成する
ためには、まず、該単結晶シリコン基体の表面に付着し
ている酸化物や汚染物質を希弗酸で除去し、ついで脱イ
オン水でリンスし、さらに乾燥する。ついで、この単結
晶シリコン基体を分子状酸素含有ガスまた水蒸気雰囲気
中で加熱することにより酸化シリコン膜を形成させる。In order to form a silicon oxide film on the surface of a single crystal silicon substrate, first remove oxides and contaminants adhering to the surface of the single crystal silicon substrate with dilute hydrofluoric acid, and then rinse with deionized water. and further dry. Next, a silicon oxide film is formed by heating this single crystal silicon substrate in a molecular oxygen-containing gas or water vapor atmosphere.
分子状酸素含有ガスとしては、純酸素ガス、酸素ガスと
不活性ガスとの混合ガス、空気、酸素リッチ空気等があ
る。また、単結晶シリコン基板を酸素プラズマ中に置い
ても酸化シリコン膜は形成され得る。Examples of the molecular oxygen-containing gas include pure oxygen gas, a mixed gas of oxygen gas and an inert gas, air, and oxygen-rich air. Further, a silicon oxide film can also be formed by placing a single crystal silicon substrate in oxygen plasma.
さらに、単結晶シリコン基体を酸化性薬品中に浸漬する
か陽極酸化しても酸化シリコン膜は形成され得る。酸化
性薬品としては、例えば硝酸、重クロム酸またはその塩
、過マンガン酸またはその塩、過塩素酸またはその塩、
過酸化水素水等がある。Furthermore, a silicon oxide film can be formed by immersing a single crystal silicon substrate in an oxidizing chemical or by anodic oxidation. Examples of oxidizing chemicals include nitric acid, dichromic acid or its salts, permanganic acid or its salts, perchloric acid or its salts,
There are hydrogen peroxide solutions, etc.
酸化シリコン膜の膜厚は酸化条件により左右され、例え
ば空気中で１気圧の圧力で単結晶シリコン基板を加熱し
て酸化シリコン膜を形成する場合には、酸化物膜の成長
速度と単結晶シリコン基板の温度とは、次の関係のよう
になる。The thickness of the silicon oxide film depends on the oxidation conditions. For example, when forming a silicon oxide film by heating a single crystal silicon substrate in air at a pressure of 1 atm, the thickness of the oxide film and the single crystal silicon depend on the growth rate of the oxide film and the The relationship with the substrate temperature is as follows.
基板温度（℃）」赳 Ｊ肥 」川 」赳 ユ並酸化物膜
成長 ０．１ ０．１４ ０．２２ ０．３３ ０．４
６速度（八／ｍ１ｎ）
したがって、空気中で酸化膜を形成させるには、３００
〜７００℃、好ましくは３００〜５００℃の温度で２〜
１００分、好ましくは２〜５０分間で加熱される。Substrate temperature (°C) 0.1 0.14 0.22 0.33 0.4
6 speed (8/m1n) Therefore, to form an oxide film in air, 300
2 to 700°C, preferably 300 to 500°C.
It is heated for 100 minutes, preferably 2 to 50 minutes.
なお、本発明における酸化シリコン膜の膜厚の測定値は
、エリプソメータで測定した値である。Note that the measured value of the film thickness of the silicon oxide film in the present invention is a value measured with an ellipsometer.
すなわち、単結晶シリコン基板を酸化処理した直後、す
なわち、多結晶シリコン層を形成する前にエリプソメー
タで測定した。このとき、っぎのように決めたゼロ点を
エリプソメータの表示値から差し引いた。単結晶シリコ
ン基板を１％弗酸中に浸漬して基板表面の自然酸化膜を
除去したのち、脱イオン水でリンスし、ついでスピン乾
燥し、直ちにエリプソメータで測定した時に得られる値
をゼロ点とした。なお、酸化物膜の屈折率は１．４６０
とした。That is, the measurement was performed using an ellipsometer immediately after the single crystal silicon substrate was oxidized, that is, before the polycrystalline silicon layer was formed. At this time, the zero point determined as shown above was subtracted from the displayed value of the ellipsometer. After immersing a single crystal silicon substrate in 1% hydrofluoric acid to remove the natural oxide film on the substrate surface, rinsing with deionized water, then spin drying, and immediately measuring with an ellipsometer, the value obtained is taken as the zero point. did. Note that the refractive index of the oxide film is 1.460.
And so.
この酸化シリコン膜の上には、多結晶シリコン層が形成
される。該多結晶シリコン層の厚みは１゜０００八〜５
μｍ１好ましくは５．０ＯＯＡ 〜１゜５μｍであり、
その結晶粒はアモルファスではなく、２ミクロン以下、
好ましくは０．０５〜０゜５ミクロンである。A polycrystalline silicon layer is formed on this silicon oxide film. The thickness of the polycrystalline silicon layer is 1°0008~5.
μm1 is preferably 5.0OOA to 1°5 μm,
Its crystal grains are not amorphous, but less than 2 microns,
Preferably it is 0.05 to 0.5 microns.
酸化シリコン膜の上に多結晶シリコン層を形成させるに
は、窒素ガス、アルゴンガス等によって希釈したガス状
シラン類の雰囲気中で前記単結晶基板を５７０〜８００
℃、好ましくは５８０〜７００℃の温度で０．１〜７時
間、好ましくは０゜３〜２時間減圧下または常圧下で加
熱することにより行なわれる。このような方法としては
、例えば減圧ＣＶＤ法がある。本発明で使用されるシラ
ン類としては、モノシラン（Ｓ Ｉ Ｈ４） 、ジクロ
ロシラン（ＳｉＨ２Ｃ１２）、モノクロロシラン（Ｓｉ
Ｈ３ｃ１）等がある。In order to form a polycrystalline silicon layer on the silicon oxide film, the single crystal substrate is heated to a temperature of 570 to 800 nm in an atmosphere of gaseous silane diluted with nitrogen gas, argon gas, etc.
The reaction is carried out by heating at a temperature of 580 to 700°C for 0.1 to 7 hours, preferably 0.3 to 2 hours under reduced pressure or normal pressure. Such a method includes, for example, a low pressure CVD method. Silanes used in the present invention include monosilane (S I H4), dichlorosilane (SiH2C12), and monochlorosilane (SiH2C12).
H3c1) etc.
本発明によるシリコンウェーハは、単結晶シリコン基体
の表面に、特定の厚みを有する酸化シリコン膜が形成さ
れているので、多結晶シリコン層が優れた密着力で均一
な厚みに形成される。しかも、酸化シリコン膜は多結晶
シリコン層の成長のために必要な成長核を無数に与える
ので、酸化シリコン膜なしの場合には、汚れなどを核と
して島状に多結晶シリコン層が成長するので一概に成長
速度が規定できず、島状に成長した部分では数十へ／分
の成長速度で、また成長していない場合ではほとんどゼ
ロ（測定できない）であるのに対し、酸化シリコン膜が
ある場合には１５０Ａ／分と多結晶シリコン層の成長速
度が向上する。また、酸化シリコン膜がない場合には、
島状に成長した部分で多結晶シリコンの結晶粒径が３〜
１０ミクロンであるのに対して、本発明においては結晶
粒径が約０．１〜０．４ミクロン（断面ＴＥＭ観察の結
果）と小さくかつ均一である。また、単結晶シリコン基
体の表面に僅かな汚染があっても、多結晶シリコン膜が
形成された後に汚れ模様は生じない。In the silicon wafer according to the present invention, a silicon oxide film having a specific thickness is formed on the surface of a single crystal silicon substrate, so that a polycrystalline silicon layer is formed with excellent adhesion and a uniform thickness. Moreover, since the silicon oxide film provides countless growth nuclei necessary for the growth of the polycrystalline silicon layer, in the case without the silicon oxide film, the polycrystalline silicon layer would grow in island shapes using dirt etc. as nuclei. The growth rate cannot be determined unconditionally; in the case of island-like growth, the growth rate is several tens of minutes per minute, and in the case of no growth, it is almost zero (unmeasurable), whereas in the case of silicon oxide films, In this case, the growth rate of the polycrystalline silicon layer increases to 150 A/min. In addition, if there is no silicon oxide film,
The crystal grain size of polycrystalline silicon in the island-like grown part is 3~
10 microns, whereas in the present invention, the crystal grain size is as small and uniform as about 0.1 to 0.4 microns (as a result of cross-sectional TEM observation). Furthermore, even if there is slight contamination on the surface of the single-crystal silicon substrate, no contamination pattern will appear after the polycrystalline silicon film is formed.
また、本発明によるシリコどウェーハを使用すると、例
えばＩＣ製造工程の最初に行なわれる９００°Ｃ以上の
熱処理によって、酸化シリコン膜は島状に凝縮して消滅
し、単結晶基体と多結晶シリコン膜とが直接接するよう
になる。Further, when using the silicon wafer according to the present invention, the silicon oxide film condenses into islands and disappears due to heat treatment at 900°C or higher performed at the beginning of the IC manufacturing process, and the single crystal substrate and polycrystalline silicon film are removed. come into direct contact with.
本発明において、ゲッタリング能力の測定は、つぎのよ
うにして行なった。In the present invention, gettering ability was measured as follows.
単結晶シリコン基体の一つの表面に酸化シリコン膜およ
び該膜上に多結晶シリコン層が形成されており、他方の
面が鏡面に研磨されているシリコンウェーハにおいて、
該鏡面を１，０００°Ｃに加熱されている純酸素ガス中
で酸化して約３００への酸化物膜を形成し、ついで該酸
化物膜上に直径１ｍｍ、厚さ５，０００への円盤状のア
ルミニウムの電極を蒸着により形成する。このようにし
て基板上に形成されたＭＯＳキャパシターの小数キャリ
ヤーの生成ライフタイムを測定することによリゲッタリ
ング能力が評価される。小数キャリヤーの生成ライフタ
イムの測定については、Ｅ、Ｈ，Ｎ１ｃｏｌｌｉａｎ
ａｎｄ Ｊ、Ｒ，Ｂｒｅｗｗｓ著 ＭＯＳ Ｐｈｙｓｉ
ｃｓ ａｎｄ Ｔｅｃｈｎｏｌｏｇｙ（Ｊｏｈｎ Ｗｉ
ｌｅｙ ＆ ５ｏｎｓ）を参照されたし。In a silicon wafer in which a silicon oxide film and a polycrystalline silicon layer are formed on one surface of a single crystal silicon substrate, and the other surface is polished to a mirror surface,
The mirror surface is oxidized in pure oxygen gas heated to 1,000°C to form an oxide film with a diameter of about 300 mm, and then a disk with a diameter of 1 mm and a thickness of 5,000 mm is formed on the oxide film. A shaped aluminum electrode is formed by vapor deposition. The regettering ability is evaluated by measuring the generation lifetime of minority carriers of the MOS capacitor thus formed on the substrate. For measurement of generation lifetime of fractional carriers, E, H, N1 collian
and J, R, Brewers MOS Physi
cs and Technology (John Wi
ley & 5ons).
シリコン基板が金属不純物で汚染されると、小数キャリ
ヤーの生成ライフタイムは短くなる。金属不純物がゲッ
タリングされると、ライフタイムは回復して長くなる。When a silicon substrate becomes contaminated with metal impurities, the generation lifetime of minority carriers is shortened. Once the metal impurities are gettered, the lifetime is restored and extended.
通常ＭＯＳキャパシターを製作する酸化工程で周辺雰囲
気から自然に極微量の金属不純物が導入されるのを防ぐ
ことはできない。Normally, it is impossible to prevent extremely small amounts of metal impurities from being naturally introduced from the surrounding atmosphere during the oxidation process used to manufacture MOS capacitors.
したがって、ゲッタリング能力に差のある複数個のシリ
コン基板を同時に処理すれば、自ずと小数キャリヤーの
生成ライフタイムに差が出るのでゲッタリング能力が相
対的に比較できる。Therefore, if a plurality of silicon substrates having different gettering abilities are processed simultaneously, there will naturally be a difference in the generation lifetime of fractional carriers, so the gettering abilities can be compared relatively.
（実施例）
つぎに、実施例を挙げて本発明をさらに詳細に説明する
。(Example) Next, the present invention will be described in further detail by giving examples.
実施例１〜４
厚さ６００ミクロンの単結晶シリコン基板を１％弗酸に
浸漬して表面に付着していた自然酸化物膜を除去、つい
で、脱イオン水でリンスし、さらにスピンドライヤーで
乾燥した。乾燥終了後の単結晶基板を直ちに４００℃の
空気雰囲気の電気炉中に７分、２２分、３６分および４
３分分間−てそれぞれ１人、３Ａ、５Ａおよび６への酸
化シリコン膜を形成させた。ついで、減圧ＣＶＤ法によ
り、シリコン（ＳｉＨ４）ガスを窒素ガスをキャリヤー
として６５０℃で熱分解させて、酸化シリコン膜の１−
に多結晶シリコン層を約１ミクロン堆積させた。Examples 1 to 4 A single crystal silicon substrate with a thickness of 600 microns was immersed in 1% hydrofluoric acid to remove the native oxide film attached to the surface, then rinsed with deionized water, and further dried with a spin dryer. did. Immediately after drying, the single crystal substrate was placed in an electric furnace in an air atmosphere at 400°C for 7 minutes, 22 minutes, 36 minutes, and 4 minutes.
Silicon oxide films were formed for 1 person, 3A, 5A, and 6 for 3 minutes, respectively. Next, by low pressure CVD method, silicon (SiH4) gas is thermally decomposed at 650°C using nitrogen gas as a carrier, and 1-
A layer of polycrystalline silicon was deposited to a thickness of about 1 micron.
このように、多結晶シリコン層を堆積したつ工−ハは両
面に多結晶シリコン層および酸化シリコン膜が堆積して
いるので、その−面を研磨して多結晶シリコン層とその
下の酸化シリコン膜を除去して単結晶シリコン基板を露
出させ、さらにこれを鏡面に仕上げた。このようにして
製作したシリコンウェーハの鏡面側に、前記のごときＭ
ＯＳキャパシターを形成させて、小数キャリヤーのライ
フタイムの値によってゲッタリング能力の評価を行なっ
た。その結果を第１表に示す。In this way, since the polycrystalline silicon layer and the silicon oxide film are deposited on both sides of the structure in which the polycrystalline silicon layer is deposited, the polycrystalline silicon layer and the silicon oxide film underneath are polished. The film was removed to expose the single-crystal silicon substrate, which was then polished to a mirror surface. On the mirror surface side of the silicon wafer manufactured in this way, the M
An OS capacitor was formed and the gettering ability was evaluated based on the lifetime value of the decimal carrier. The results are shown in Table 1.
なお、これらのシリコンウェーハについて、金属顕微鏡
および走査電子顕微鏡および透過電子顕微鏡を用いて観
察したところ、多結晶シリコン層の成長速度は１５０八
／分、結晶粒径は０．１〜０．４ミクロンであった。さ
らに、このシリコンウェーハを暗室で集光灯で暗視野に
して散乱光で見たところ、白模様は全くみられなかった
。In addition, when these silicon wafers were observed using a metallurgical microscope, a scanning electron microscope, and a transmission electron microscope, the growth rate of the polycrystalline silicon layer was 1508/min, and the crystal grain size was 0.1 to 0.4 microns. Met. Furthermore, when this silicon wafer was viewed in a dark room using a condensing light in the dark field and using scattered light, no white pattern was observed.
比較例１
実施例１〜４の方法において、単結晶シリコン基板の表
面に酸化シリコン膜を形成しない以外は、実施例１と同
様の方法を行なってシリコンウェーハを得た。この単結
晶シリコン基板の表面に多結晶シリコン層を形成してな
るシリコンウェーハについて、実施例１〜４と同様な方
法によりゲッタリング能力の評価を行なった。その結果
を第１表に示す。Comparative Example 1 A silicon wafer was obtained in the same manner as in Example 1 except that a silicon oxide film was not formed on the surface of the single crystal silicon substrate in the method of Examples 1 to 4. The gettering ability of the silicon wafer formed by forming a polycrystalline silicon layer on the surface of this single crystal silicon substrate was evaluated by the same method as in Examples 1 to 4. The results are shown in Table 1.
なお、これらのシリコンウェーハについて、金属顕微鏡
および走査電子顕微鏡および透過電子顕微鏡を用いたと
ころ、島状に成長した部分で数十六方の成長速度で多結
晶シリコン層が成長していたが、成長していない部分で
はほとんどゼロであり、汚れ等を核として多結晶シリコ
ン層が成長するので、−ｔａには成長速度が規定できな
かった。Furthermore, when these silicon wafers were examined using a metallurgical microscope, a scanning electron microscope, and a transmission electron microscope, it was found that polycrystalline silicon layers were growing at a growth rate of several tens of six directions in the areas where the island-like growth occurred. It is almost zero in the areas where it is not exposed, and since the polycrystalline silicon layer grows using dirt and the like as nuclei, it was not possible to specify the growth rate for -ta.
また、結晶粒径は、島状に成長した部分では３〜１０ミ
クロンであった。さらに、このシリコンウェーハを暗室
で集光灯で暗視野にして散乱光で見たところ、星状、島
状あるいは液体が流れたような白い模様が見えた。星状
のものは減圧ＣＶＤ炉内で発生したパーティクルを成長
核として、その周りに多結晶シリコン層が成長したもの
であり、島状のものは星状のものが集ったものあるいは
シリコンウェーハとボート（ウェーハを載置する石英治
具）との接触点から成長した多結晶シリコン層等であり
、流体が流れたような模様はウェーハ表面の酸化物膜を
エッチオフしたのち、脱イオン水でリンスしてリンス槽
から引き上げた時につ工−ハ表面に残されたパーティク
ルを成長核として成長した多結晶シリコン層である。減
圧ＣＶＤ炉に１００枚チャージして９５枚にはなんらか
の白模様が見られた。白模様が見られなかったウェーハ
には多結晶シリコン層が堆積されていなかった。Further, the crystal grain size was 3 to 10 microns in the island-shaped portion. Furthermore, when this silicon wafer was viewed in a dark room using a condensing light in the dark field and using scattered light, white patterns that looked like stars, islands, or flowing liquid could be seen. Star-shaped particles are particles generated in a low-pressure CVD furnace as growth nuclei, and a polycrystalline silicon layer has grown around them. Island-shaped particles are a collection of star-shaped particles or a silicon wafer. This is a polycrystalline silicon layer that has grown from the point of contact with the boat (a quartz jig that holds the wafer). This is a polycrystalline silicon layer that grows using particles left on the surface of the substrate when it is rinsed and pulled out of the rinsing bath as growth nuclei. 100 sheets were charged in the low pressure CVD furnace, and 95 sheets had some kind of white pattern. Wafers on which no white pattern was observed did not have a polycrystalline silicon layer deposited on them.
比較例２
実施例１〜４の方法において、酸化シリコン膜の膜厚を
１０八にした以外は実施例１と同様の方法を行なってシ
リコンウェーハを得、さらに同様の方法でゲッタリング
能力の評価を行なった。その結果を第１表に示す。Comparative Example 2 A silicon wafer was obtained in the same manner as in Example 1 except that the thickness of the silicon oxide film was changed to 108 in the method of Examples 1 to 4, and the gettering ability was evaluated in the same manner. I did it. The results are shown in Table 1.
第１表
香 リ 酸化シリコン膜 ゲッタリング能力厚み（八
） （ｍＳ）
比較例１ ０ １． ０〜１，４実施例
１ １ ３．０〜８．５実施例２
３ ３．３〜６．７実施例３ ５
２．６〜５．２実施例４ ６ １
．８〜３．７比較例２ １０ １．２〜１
．６第１表から明らかなように、本発明によるシリコン
ウェーハ（実施例１〜４）は、従来のもの（比較例１）
と比較して小数のキャリヤの発生寿命が長く、ゲッタリ
ング能力が著しく優れていることがわかる。また、酸化
シリコン膜を設けていない比較例１のウェーハにおいて
は、単結晶シリコン基体上に多結晶シリコンの結晶粒が
成長する部位と成長しない部位とができ、かつ結晶粒径
は平均３ミクロン以上であり、中には１０ミクロン以−
ヒのものも生成している。これに対して、酸化シリコン
膜の厚みが１八以上である実施例１〜４のウェーハの場
合には、単結晶シリコン基体の全面にわたって多結晶シ
リコンの結晶粒が成長し、その結晶粒径は０．１〜０．
４ミクロンの均一なものである。1st surface Silicon oxide film Gettering ability thickness (8) (mS) Comparative example 1 0 1. 0-1,4 Example 1 1 3.0-8.5 Example 2
3 3.3-6.7 Example 3 5
2.6-5.2 Example 4 6 1
．． 8-3.7 Comparative Example 2 10 1.2-1
．． 6 As is clear from Table 1, the silicon wafers according to the present invention (Examples 1 to 4) are different from the conventional silicon wafers (Comparative Example 1).
It can be seen that the lifetime of generation of a small number of carriers is longer than that of the conventional method, and the gettering ability is significantly superior. In addition, in the wafer of Comparative Example 1 in which no silicon oxide film was provided, there were regions where polycrystalline silicon crystal grains grew and regions where they did not grow on the single crystal silicon substrate, and the crystal grain size was on average 3 microns or more. Some of them are 10 microns or more.
They are also producing H. On the other hand, in the case of the wafers of Examples 1 to 4 in which the silicon oxide film has a thickness of 18 or more, polycrystalline silicon crystal grains grow over the entire surface of the single crystal silicon substrate, and the crystal grain size is 0.1~0.
It has a uniform diameter of 4 microns.
参考例
実施例３で得られた５への膜厚の酸化シリコン膜および
１ミクロンの層厚の多結晶シリコン層を有するシリコン
ウェーへのを９００℃の水蒸気雰囲気中で２時間の条件
で酸化したのち、透過電子顕微鏡で断面を観察するとと
もに組成分析を行なったところ、単結晶シリコン基体と
多結晶シリコン層との界面には連続的な酸化物膜は見ら
れず、米粒のように島状に点在する酸化物が見られた。Reference Example A silicon wafer having a silicon oxide film with a thickness of 5 mm and a polycrystalline silicon layer with a thickness of 1 micron obtained in Example 3 was oxidized in a steam atmosphere at 900° C. for 2 hours. Later, when the cross section was observed using a transmission electron microscope and the composition was analyzed, no continuous oxide film was found at the interface between the single crystal silicon substrate and the polycrystalline silicon layer, but an island-like film like a grain of rice was found. Scattered oxides were observed.
そして、界面の大部分において単結晶シリコン基体と多
結晶シリコン層が密着し、多結晶シリコン層の一部は固
相エピタキシャル成長していた。The single crystal silicon substrate and the polycrystalline silicon layer were in close contact with each other at most of the interface, and a portion of the polycrystalline silicon layer was grown by solid phase epitaxial growth.
例えば、ＩＣの製造工程ではウェルを形成したり、ある
いは素子領域を厚い酸化膜で絶縁分離するために窒化膜
をマスクとして使用するが、通常、この窒化１１ｍの下
に酸化膜を形成する。この酸化膜をパッド酸化膜という
が、ＩＣ製造工程では、最初のウェーハの洗浄工程の直
後に、このパッド酸化膜を形成する工程がくることが多
い。パッド酸化の代表的な例は、例えば１，０００℃の
ドライ酸素雰囲気中で１時間、あるいは９００℃の水蒸
気雰囲気中で２時間である。これらの条件によっておよ
そ５００八厚のパッド酸化膜が形成される。For example, in an IC manufacturing process, a nitride film is used as a mask to form a well or to insulate and isolate an element region with a thick oxide film, and an oxide film is usually formed under the nitride layer 11m. This oxide film is called a pad oxide film, and in the IC manufacturing process, the process of forming this pad oxide film often occurs immediately after the first wafer cleaning process. Typical pad oxidation is, for example, 1 hour in a dry oxygen atmosphere at 1,000°C or 2 hours in a steam atmosphere at 900°C. Under these conditions, a pad oxide film approximately 500 mm thick is formed.
参考例から明らかなように、本発明によるシリコンウェ
ーハにおいてはこのようなパッド酸化膜は形成する工程
を経過することによって単結晶シリコン基体と多結晶シ
リコン層との間の１〜８への酸化膜が消滅し、単結晶シ
リコン基体と多結晶シリコン層とが密着する。As is clear from the reference example, in the silicon wafer according to the present invention, such a pad oxide film is formed by forming oxide films 1 to 8 between the single crystal silicon substrate and the polycrystalline silicon layer. disappears, and the single-crystal silicon substrate and polycrystalline silicon layer come into close contact.
（発明の効果）
本発明によれば、特定された厚みを持つ酸化シリコン膜
を介して単結晶シリコン基体上に多結晶シリコン層を形
成してなるものであるから、多結晶シリコン層の密着性
および均一性が優れたものとなっており、しかも、多結
晶シリコン層の結晶粒の大きさが均一なため、従来の単
に多結晶シリコン層を形成したものに比較して結晶粒界
の面積が大き（、ゲッタリング能力が優れている。した
がって、高密度集積回路のデバイスとしての歩留りが高
い材料として使用され得る。(Effects of the Invention) According to the present invention, since a polycrystalline silicon layer is formed on a single crystal silicon substrate via a silicon oxide film having a specified thickness, the adhesion of the polycrystalline silicon layer is improved. Furthermore, since the crystal grain size of the polycrystalline silicon layer is uniform, the area of the grain boundaries is smaller than that of conventional polycrystalline silicon layers. It has a large size and excellent gettering ability. Therefore, it can be used as a material with high yield as a device for high-density integrated circuits.
Claims (2)
成された厚さ１〜８Åの酸化シリコン膜と、該酸化シリ
コン膜上に形成された多結晶シリコン層とよりなるゲッ
タリング能力の優れたシリコンウェーハ。(1) Gettering ability consisting of a single crystal silicon substrate, a silicon oxide film with a thickness of 1 to 8 Å formed on one surface of the substrate, and a polycrystalline silicon layer formed on the silicon oxide film. Superior silicon wafer.
化して厚さ１〜８Åの酸化シリコン膜を形成させ、かつ
該酸化シリコン膜をガス状シラン類と加熱下に接触させ
て該酸化シリコン膜上に多結晶シリコン層を形成させる
ことを特徴とするゲッタリング能力の優れたシリコンウ
ェーハの製造方法。(2) Oxidizing at least one surface of a single crystal silicon substrate to form a silicon oxide film with a thickness of 1 to 8 Å, and contacting the silicon oxide film with a gaseous silane under heating to form the silicon oxide film. A method for manufacturing a silicon wafer with excellent gettering ability, characterized by forming a polycrystalline silicon layer thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1079762A JPH0648686B2 (en) | 1988-03-30 | 1989-03-30 | Silicon wafer having excellent gettering ability and method of manufacturing the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-78370 | 1988-03-30 | ||
| JP7837088 | 1988-03-30 | ||
| JP1079762A JPH0648686B2 (en) | 1988-03-30 | 1989-03-30 | Silicon wafer having excellent gettering ability and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01315144A true JPH01315144A (en) | 1989-12-20 |
| JPH0648686B2 JPH0648686B2 (en) | 1994-06-22 |
Family
ID=26419455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1079762A Expired - Lifetime JPH0648686B2 (en) | 1988-03-30 | 1989-03-30 | Silicon wafer having excellent gettering ability and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0648686B2 (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05299426A (en) * | 1992-02-21 | 1993-11-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device and semiconductor substrate |
| US5374842A (en) * | 1992-02-21 | 1994-12-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a gettering sink material layer |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
| WO2010131412A1 (en) * | 2009-05-15 | 2010-11-18 | 株式会社Sumco | Silicon wafer and method for producing the same |
| JP2011009613A (en) * | 2009-06-29 | 2011-01-13 | Sumco Corp | Epitaxial silicon wafer, and method of manufacturing the same |
| USRE43450E1 (en) | 1994-09-29 | 2012-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating semiconductor thin film |
| JP2012199550A (en) * | 2011-03-22 | 2012-10-18 | Soytec | Method of manufacturing base substrate for semiconductor type substrate on insulator |
| WO2016140850A1 (en) * | 2015-03-03 | 2016-09-09 | Sunedison Semiconductor Limited | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
| US10290533B2 (en) | 2015-03-17 | 2019-05-14 | Globalwafers Co., Ltd. | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
| US10304722B2 (en) | 2015-06-01 | 2019-05-28 | Globalwafers Co., Ltd. | Method of manufacturing semiconductor-on-insulator |
| US10332782B2 (en) | 2015-06-01 | 2019-06-25 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
| US10546771B2 (en) | 2016-10-26 | 2020-01-28 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency |
| US10755966B2 (en) | 2015-11-20 | 2020-08-25 | GlobaWafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
| US10796945B2 (en) | 2014-11-18 | 2020-10-06 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He—N2 co-implantation |
| US10818540B2 (en) | 2018-06-08 | 2020-10-27 | Globalwafers Co., Ltd. | Method for transfer of a thin layer of silicon |
| US10825718B2 (en) | 2016-06-22 | 2020-11-03 | Globalwafers Co., Ltd. | Method of preparing an isolation region in a high resistivity silicon-on-insulator substrate |
| US11139198B2 (en) | 2014-11-18 | 2021-10-05 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
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| JPS52120777A (en) * | 1976-04-02 | 1977-10-11 | Ibm | Ic |
| JPS58138035A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Semiconductor device and manufacture thereof |
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1989
- 1989-03-30 JP JP1079762A patent/JPH0648686B2/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52120777A (en) * | 1976-04-02 | 1977-10-11 | Ibm | Ic |
| JPS58138035A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Semiconductor device and manufacture thereof |
Cited By (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05299426A (en) * | 1992-02-21 | 1993-11-12 | Mitsubishi Electric Corp | Manufacture of semiconductor device and semiconductor substrate |
| US5374842A (en) * | 1992-02-21 | 1994-12-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a gettering sink material layer |
| US5516706A (en) * | 1992-02-21 | 1996-05-14 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device with a gettering sink material layer |
| US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP0635879A3 (en) * | 1993-07-22 | 1996-10-23 | Toshiba Kk | Semiconductor silicon wafer and process for producing it. |
| US5738942A (en) * | 1993-07-22 | 1998-04-14 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| USRE43450E1 (en) | 1994-09-29 | 2012-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating semiconductor thin film |
| WO2010131412A1 (en) * | 2009-05-15 | 2010-11-18 | 株式会社Sumco | Silicon wafer and method for producing the same |
| JP2011009613A (en) * | 2009-06-29 | 2011-01-13 | Sumco Corp | Epitaxial silicon wafer, and method of manufacturing the same |
| JP2012199550A (en) * | 2011-03-22 | 2012-10-18 | Soytec | Method of manufacturing base substrate for semiconductor type substrate on insulator |
| US11139198B2 (en) | 2014-11-18 | 2021-10-05 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
| US10796945B2 (en) | 2014-11-18 | 2020-10-06 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He—N2 co-implantation |
| US11699615B2 (en) | 2014-11-18 | 2023-07-11 | Globalwafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacture |
| WO2016140850A1 (en) * | 2015-03-03 | 2016-09-09 | Sunedison Semiconductor Limited | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
| EP3367424A1 (en) * | 2015-03-03 | 2018-08-29 | Sunedison Semiconductor Limited | Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
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| US10332782B2 (en) | 2015-06-01 | 2019-06-25 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
| US10510583B2 (en) | 2015-06-01 | 2019-12-17 | Globalwafers Co., Ltd. | Method of manufacturing silicon germanium-on-insulator |
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| US10818539B2 (en) | 2015-11-20 | 2020-10-27 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
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| US11655560B2 (en) | 2016-06-08 | 2023-05-23 | Globalwafers Co., Ltd. | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
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|---|---|
| JPH0648686B2 (en) | 1994-06-22 |
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