JP2602598B2 - Semiconductor substrate processing method - Google Patents
Semiconductor substrate processing methodInfo
- Publication number
- JP2602598B2 JP2602598B2 JP10206292A JP10206292A JP2602598B2 JP 2602598 B2 JP2602598 B2 JP 2602598B2 JP 10206292 A JP10206292 A JP 10206292A JP 10206292 A JP10206292 A JP 10206292A JP 2602598 B2 JP2602598 B2 JP 2602598B2
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- JP
- Japan
- Prior art keywords
- oxide film
- breakdown voltage
- heat treatment
- crystal growth
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【０００１】本発明は、チョクラルスキー法によって広
範囲にわたる結晶成長速度で製造したシリコンウェー
ハ、特にＭＯＳ型半導体ウェーハにおける酸化膜耐圧特
性を改善することを可能とした半導体基板の処理方法に
関する。The present invention relates to a method for treating a semiconductor substrate which makes it possible to improve the withstand voltage characteristics of an oxide film on a silicon wafer, particularly a MOS type semiconductor wafer, manufactured at a wide range of crystal growth rates by the Czochralski method.
【０００２】[0002]
【従来の技術】チョクラルスキー法によって製造された
シリコン単結晶中には結晶育成時の熱履歴に起因した結
晶欠陥が導入されている。かかる結晶欠陥は結晶育成時
の成長速度と相関がみられ結晶成長速度が遅い場合には
欠陥密度が低く、従ってシリコン単結晶の酸化膜耐圧は
良好である。しかし、この様なシリコン単結晶は生産性
からみて産業上の効率が悪いことは明白である。一方、
結晶成長速度が速い場合には、生産効率がよいことはい
うまでもないが、得られたシリコン単結晶の欠陥密度が
高く、従ってシリコン単結晶の酸化膜耐圧は不良であっ
た。2. Description of the Related Art In silicon single crystals manufactured by the Czochralski method, crystal defects due to thermal history during crystal growth are introduced. Such crystal defects are correlated with the growth rate during crystal growth. When the crystal growth rate is low, the defect density is low, and thus the silicon single crystal has a good oxide film breakdown voltage. However, it is clear that such a silicon single crystal is industrially inefficient from the viewpoint of productivity. on the other hand,
When the crystal growth rate is high, it goes without saying that the production efficiency is good, but the defect density of the obtained silicon single crystal is high, and thus the oxide film breakdown voltage of the silicon single crystal is poor.
【０００３】また、デバイスプロセスにおいて酸化膜耐
圧特性を改善させる前熱処理方法としては犠牲酸化が知
られている。この犠牲酸化に用いられる熱処理温度は通
常９００〜１１００℃程度であり、このような処理を施
しても結晶成長速度の速いシリコン単結晶では酸化膜耐
圧特性の改善はあまり期待できなかつた。Further, sacrificial oxidation is known as a pre-heat treatment method for improving oxide film breakdown voltage characteristics in a device process. The heat treatment temperature used for the sacrificial oxidation is usually about 900 to 1100 ° C., and even if such a treatment is performed, improvement of the oxide film breakdown voltage characteristics cannot be expected much with a silicon single crystal having a high crystal growth rate.
【０００４】半導体集積回路においてデバイス素子の動
作時に絶縁耐圧が高いこと、リーク電流が小さく酸化膜
の信頼性が高いことが必要とされる。ここで用いられる
材料はチョクラルスキー法で製造されたシリコン単結晶
ウェーハであるが、この種のシリコン単結晶には単結晶
育成工程中の熱履歴により結晶欠陥が導入されているこ
とは既に述べた通りである。[0004] In a semiconductor integrated circuit, it is required that the withstand voltage is high during the operation of the device element, the leak current is small, and the reliability of the oxide film is high. The material used here is a silicon single crystal wafer manufactured by the Czochralski method, but it has already been mentioned that this type of silicon single crystal has crystal defects introduced due to the thermal history during the single crystal growth process. As expected.
【０００５】[0005]
【発明が解決しようとする課題】この様な結晶欠陥をも
ったシリコンウェーハを使用して集積回路を製造した場
合には酸化膜耐圧の不良が問題となる。従って、歩留ま
りよく集積回路を製造する為には酸化膜耐圧特性の優れ
たシリコンウェーハが必要となる。その為には、生産効
率のよい結晶成長速度の速いシリコン単結晶において
も、酸化膜耐圧を低下させる様なシリコン単結晶中の微
小欠陥をなくす処理方法の開発が当業界における課題と
なっている。When an integrated circuit is manufactured using a silicon wafer having such crystal defects, there is a problem in that the breakdown voltage of the oxide film is poor. Therefore, in order to manufacture an integrated circuit with a high yield, a silicon wafer having excellent oxide film breakdown voltage characteristics is required. For this reason, even in a silicon single crystal with high production efficiency and a high crystal growth rate, development of a processing method for eliminating minute defects in the silicon single crystal that lowers the oxide film breakdown voltage has been an issue in this industry. .
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体基板の処理方法においては、チョク
ラルスキー法によって製造されたシリコン単結晶ウェー
ハを１２５０〜１３００℃の高温領域で０．５〜４時間
の熱処理を施し、この時に形成される酸化膜を除去し清
浄化した後に熱酸化膜を形成するようにしたものであ
る。In order to solve the above-mentioned problems, in a method for processing a semiconductor substrate according to the present invention, a silicon single crystal wafer manufactured by the Czochralski method is used in a high-temperature region of 1250-1300 ° C. The heat treatment is performed for 0.5 to 4 hours to remove and clean the oxide film formed at this time, and then a thermal oxide film is formed.
【０００７】上記高温領域は１２５０〜１３００℃の範
囲が必要で、この範囲を外れると酸化膜耐圧特性の改善
は十分でなくなる。The high-temperature region needs to be in the range of 1250 to 1300 ° C. If the temperature is outside this range, the oxide film breakdown voltage characteristics cannot be sufficiently improved.
【０００８】また、上記熱処理は、０．５〜４時間の範
囲で行うことが必要で、０．５時間に満たないと酸化膜
耐圧特性の改善は十分でなく、４時間を越えると新たな
欠陥、例えばＯＳＦ等が発生してしまう。なお、上記熱
処理は乾燥酸素または酸素窒素混合雰囲気中で行うのが
好ましい。The heat treatment needs to be performed in the range of 0.5 to 4 hours. If the heat treatment is performed for less than 0.5 hour, the oxide film breakdown voltage characteristics cannot be sufficiently improved. Defects, such as OSF, occur. Note that the heat treatment is preferably performed in a mixed atmosphere of dry oxygen or oxygen and nitrogen.
【０００９】[0009]
【作用】シリコン単結晶の結晶欠陥の消滅に着目すれば
例えば１２８０℃の熱処理を施すと欠陥核の溶体化に効
果があることが公知となっている。しかし、この熱処理
を施した後の酸化膜耐圧特性については何等の開示もな
されていない。When attention is paid to the elimination of crystal defects in a silicon single crystal, it is known that, for example, heat treatment at 1280 ° C. is effective in solutionizing defect nuclei. However, there is no disclosure about the oxide film breakdown voltage characteristics after the heat treatment.
【００１０】本発明の半導体基板の処理方法は、１２５
０〜１３００℃、０．５〜４時間の熱処理を施し、この
時に形成された熱酸化膜を希ＨＦにより除去し、しかる
後に再び熱酸化膜を形成するものである。本発明は、上
記したごとく熱酸化膜を再び形成することによって、当
該酸化膜中に取り込まれる結晶欠陥は無くなり酸化膜耐
圧特性は大幅に改善されたものと考えられる。The method for processing a semiconductor substrate according to the present invention comprises:
A heat treatment is performed at 0 to 1300 ° C. for 0.5 to 4 hours, the thermal oxide film formed at this time is removed by dilute HF, and then a thermal oxide film is formed again. According to the present invention, it is considered that by forming the thermal oxide film again as described above, the crystal defects taken into the oxide film disappeared and the withstand voltage characteristics of the oxide film were greatly improved.
【００１１】前述したチョクラルスキー法によって製造
される結晶成長速度の速いシリコン単結晶において、酸
化膜耐圧に影響を与える要因としては、主に結晶育成時
に取り込まれたフローパターン欠陥と副次的に格子間酸
素に起因した欠陥とを挙げることができる（１９９１年
春期応用物理学会予稿集２８ｐ−ＺＬ−１，同２８ｐ−
ＺＬ−２，同２８ｐ−ＺＬ−３，同２８ｐ−ＺＬ−４及
びＳｅｍｉｃｏｎｄ．Ｓｃｉ．Ｔｅｃｈｎｏｌ．７（１
９９２）Ａ１３５−Ａ１４０を参照）。本発明方法で用
いられる熱処理中に、シリコンウェーハ中のフローパタ
ーン欠陥はほとんど消滅する。In a silicon single crystal manufactured by the above-described Czochralski method and having a high crystal growth rate, factors that affect the oxide film breakdown voltage are mainly caused by flow pattern defects introduced during crystal growth and secondaryly. Defects caused by interstitial oxygen can be cited (Proceedings of the Japan Society of Applied Physics Spring 1991, 28p-ZL-1, 28p-
ZL-2, 28p-ZL-3, 28p-ZL-4 and Semicond. Sci. Technol. 7 (1
992) A135-A140). During the heat treatment used in the method of the present invention, flow pattern defects in the silicon wafer almost disappear.
【００１２】また、本発明の高温領域の熱処理によって
シリコンウェーハ表面近傍の格子間酸素は外方拡散によ
り密度が低下し、それに伴い格子間酸素起因の微小欠陥
密度も低下する。従って、その後の熱酸化膜形成におい
て酸化膜中に微小な欠陥はほとんど取り込まれない。よ
って、本発明によれば、酸化膜耐圧特性の優れたシリコ
ンウェーハを得ることが可能となるものである。Further, the density of interstitial oxygen near the silicon wafer surface is reduced by the outward diffusion due to the heat treatment in the high temperature region according to the present invention, and accordingly, the density of minute defects caused by interstitial oxygen is also reduced. Therefore, in the subsequent formation of the thermal oxide film, a minute defect is hardly taken in the oxide film. Therefore, according to the present invention, it is possible to obtain a silicon wafer having excellent oxide film breakdown voltage characteristics.
【００１３】[0013]
【実施例】以下に本発明の実施例を挙げてさらに具体的
に説明する。 実験例１ チョクラルスキー法により広範囲にわたる結晶成長速度
（０．４〜１．７ｍｍ／ｍｉｎ）で製造したシリコン単
結晶（結晶直径：５”φ、成長方位：＜１００＞、導伝
型：ｐ型、比抵抗：１０Ω・ｃｍ）より採取した未熱処
理ウェーハの酸化膜耐圧の良品率を測定して図１に示し
た。酸化膜耐圧を測定するためのＭＯＳダイオードは、
ゲート酸化膜を２５ｎｍ（乾燥酸素雰囲気中で形成）、
リンドープポリシリコン電極とした。酸化膜耐圧はウェ
ーハ当り１００個のダイオードについて測定（ゲート面
積８ｍｍ2 、判定電流値１ｍＡ／ｃｍ2 ）し、８ＭＶ／
ｃｍ以上を良品とした。The present invention will be described more specifically with reference to the following examples. Experimental Example 1 A silicon single crystal (crystal diameter: 5 ″ φ, growth direction: <100>, conduction type: p) manufactured by the Czochralski method at a wide range of crystal growth rate (0.4 to 1.7 mm / min) The non-heat-treated wafer sampled from the mold (specific resistance: 10 Ω · cm) was measured for the yield rate of the oxide film breakdown voltage and shown in Fig. 1. The MOS diode for measuring the oxide film breakdown voltage is shown in FIG.
A gate oxide film of 25 nm (formed in a dry oxygen atmosphere),
A phosphorus-doped polysilicon electrode was used. The oxide film breakdown voltage was measured for 100 diodes per wafer (gate area 8 mm 2 , judgment current value 1 mA / cm 2 ), and 8 MV /
cm or more was defined as a good product.
【００１４】また、上記未熱処理ウェーハのフローパタ
ーン欠陥と酸化膜耐圧との関係を測定して図２に示し
た。フローパターン欠陥は選択エッチング法（Ｋ2 Ｃｒ
2 Ｏ7２ｇ：Ｈ2 Ｏ５０ｍｌ：ＨＦ１００ｍｌ）を用
い、３０分エッチング後に光学顕微鏡によりカウントし
た。FIG. 2 shows the relationship between the flow pattern defect of the unheated wafer and the breakdown voltage of the oxide film. The flow pattern defect is selectively etched (K 2 Cr
2 O 7 2g: H 2 O50ml : HF100ml) was used to count by optical microscopy after 30 minutes etching.
【００１５】図１及び図２に示した結果から、酸化膜耐
圧の良品率は結晶成長速度の速いシリコンウェーハほど
低下し、また、シリコンウェーハ中のフローパターン欠
陥密度が高くなるに従い低下することが分かった。From the results shown in FIGS. 1 and 2, it can be seen that the yield rate of the oxide film withstand voltage decreases as the crystal growth rate of the silicon wafer increases, and also as the flow pattern defect density in the silicon wafer increases. Do you get it.
【００１６】さらに、シリコン単結晶中の格子間酸素と
酸化膜耐圧の良品率との関係を測定して図１及び図２に
示した。図１、図２、図３及び図５において、○印は格
子間酸素濃度の低い（７．１〜１２．８ｘ１０17／ｃｍ
3 old ASTM) シリコンウェーハ、△印は格子間酸素濃度
の高い（１４．１〜１５．６ｘ１０17／ｃｍ3 ）シリコ
ンウェーハを示す。Further, the relationship between the interstitial oxygen in the silicon single crystal and the yield rate of the oxide film breakdown voltage was measured and shown in FIGS. 1 and 2. 1, 2, 3, and 5, a circle indicates that the interstitial oxygen concentration is low (7.1 to 12.8 × 10 17 / cm).
3 old ASTM) A silicon wafer, and a triangle indicates a silicon wafer having a high interstitial oxygen concentration (14.1 to 15.6 × 10 17 / cm 3 ).
【００１７】図１及び図２の結果から、シリコン単結晶
の格子間酸素濃度の低いグループの酸化膜耐圧良品率が
若干よいことが分かった。From the results shown in FIGS. 1 and 2, it was found that the group having a low interstitial oxygen concentration of the silicon single crystal had a slightly better oxide film breakdown voltage non-defective rate.
【００１８】従って、酸化膜耐圧に影響を与えた要因は
主に結晶育成時に取り込まれたフローパターン欠陥と副
次的に格子間酸素に起因した欠陥であることが判明し
た。酸化膜耐圧を改善させる為にはこれらの欠陥が酸化
膜中に取り込まれないことが必要である。Therefore, it was found that the factors that influenced the breakdown voltage of the oxide film were mainly flow pattern defects introduced during crystal growth and defects secondary to interstitial oxygen. In order to improve the breakdown voltage of the oxide film, it is necessary that these defects are not taken into the oxide film.
【００１９】実験例２ チョクラルスキー法により１．２ｍｍ／ｍｉｎの結晶成
長速度で製造したシリコンウェーハについて未熱処理品
と、１０００℃（２時間）、１１００℃（２時間）、１
１５０℃（２時間）、１２００℃（２時間）の熱処理
（乾燥酸素雰囲気中）を施し、各熱処理温度とフローパ
ターン欠陥との関係を測定し、その結果を図３に示し
た。図３の結果から、フローパターン欠陥は１１００℃
で減少し始め１２００℃でほとんど消滅しており、高温
の熱処理は欠陥消滅に効果があることが認められた。ま
た、シリコン単結晶の格子間酸素濃度は、フローパター
ン欠陥密度にあまり影響を与えないことがわかった。EXPERIMENTAL EXAMPLE 2 A silicon wafer manufactured at a crystal growth rate of 1.2 mm / min by the Czochralski method was compared with an unheated silicon wafer at 1000 ° C. (2 hours), 1100 ° C. (2 hours),
Heat treatment (in a dry oxygen atmosphere) at 150 ° C. (2 hours) and 1200 ° C. (2 hours) was performed, and the relationship between each heat treatment temperature and flow pattern defects was measured. The results are shown in FIG. From the results in FIG. 3, the flow pattern defect is 1100 ° C.
, And almost disappeared at 1200 ° C., and it was confirmed that heat treatment at a high temperature was effective in eliminating defects. In addition, it was found that the interstitial oxygen concentration of the silicon single crystal did not significantly affect the flow pattern defect density.
【００２０】実験例３ さらに酸化膜耐圧への効果を調査するために、実験例２
と同じ結晶成長速度で製造したシリコンウェーハについ
て未熱処理品と、１１００℃（２時間）、１１５０℃
（２時間）、１２００℃（２時間）の熱処理を施した。
これらのウェーハについてＨＦで酸化膜を除去し清浄化
した後乾燥酸素雰囲気中でゲート酸化膜を２５ｎｍ形成
してその酸化膜耐圧特性を測定して、その結果を図４に
示した。同図の結果から明らかなように、１２００℃の
熱処理においては酸化膜耐圧の改善はみられるものの完
全でない。また、１２００℃未満の熱処理ではほとんど
効果が認められない。Experimental Example 3 In order to further investigate the effect on the oxide film breakdown voltage, Experimental Example 2
The silicon wafer manufactured at the same crystal growth rate as that of the unheated product, 1100 ° C. (2 hours), 1150 ° C.
(2 hours) A heat treatment at 1200 ° C. (2 hours) was performed.
After removing the oxide film with HF and cleaning the wafer, a gate oxide film was formed with a thickness of 25 nm in a dry oxygen atmosphere, and the breakdown voltage characteristics of the oxide film were measured. The results are shown in FIG. As is clear from the results of FIG. 7, the heat treatment at 1200 ° C. improves the oxide film breakdown voltage, but is not complete. In addition, the heat treatment at a temperature lower than 1200 ° C. has almost no effect.
【００２１】この理由は、結晶育成時にすでに取り込ま
れている格子間酸素に起因した欠陥はかかる温度領域に
おいて消滅しない為である。The reason is that defects caused by interstitial oxygen already taken in during crystal growth do not disappear in such a temperature range.
【００２２】実施例１ 実験例２と同じ結晶成長速度で製造したシリコンウェー
ハについて１２８０℃（３０分）の熱処理を施した後Ｈ
Ｆで酸化膜を除去し清浄化した後乾燥酸素雰囲気中でゲ
ート酸化膜を２５ｎｍ形成してその酸化膜耐圧特性を測
定して、その結果を実験例３とともに図４に示した。図
４に示されるごとく、１２８０℃で３０分熱処理したウ
ェーハの酸化膜耐圧は上記した実験例３の各熱処理の場
合に比較して最も改善の度合いが高いことが分かる。Example 1 A silicon wafer manufactured at the same crystal growth rate as in Experimental Example 2 was subjected to a heat treatment at 1280 ° C. (30 minutes),
After removing the oxide film with F and cleaning it, a gate oxide film was formed in a dry oxygen atmosphere to a thickness of 25 nm, and the breakdown voltage characteristics of the oxide film were measured. The results are shown in FIG. As shown in FIG. 4, it can be seen that the oxide film breakdown voltage of the wafer heat-treated at 1280 ° C. for 30 minutes has the highest degree of improvement as compared with each of the heat treatments of Experimental Example 3 described above.
【００２３】実施例２ チョクラルスキー法により広範囲にわたる結晶成長速度
で製造したシリコンウェーハについて１２８０℃、１時
間の熱処理を施した後ＨＦで酸化膜を除去し清浄化した
後ウェット酸化（パイロジェニック法）によりゲート酸
化膜を２５ｎｍ形成してその酸化膜耐圧特性を測定し
て、その結果を図５に示した。図５の結果から明らかな
ように、本発明の半導体基板の処理方法を用いれば、結
晶成長速度にかかわらず酸化膜耐圧の良品率をほぼ１０
０％にできる。Example 2 A silicon wafer manufactured at a crystal growth rate over a wide range by the Czochralski method is subjected to a heat treatment at 1280 ° C. for 1 hour, an oxide film is removed with HF, and the silicon film is cleaned, followed by wet oxidation (pyrogenic method). ), A gate oxide film having a thickness of 25 nm was formed, and the breakdown voltage characteristics of the oxide film were measured. The results are shown in FIG. As is clear from the results of FIG. 5, the non-defective rate of oxide film breakdown voltage can be reduced to about 10 regardless of the crystal growth rate by using the semiconductor substrate processing method of the present invention.
0%.
【００２４】また、シリコン単結晶の格子間酸素濃度
は、本発明の高温領域の熱処理において、格子間酸素濃
度の相違による影響がないことが確認できた。本発明者
は本発明の高温領域の熱処理を施した後５０μｍポリッ
シュして格子間酸素の外方拡散が起きない領域の酸化膜
耐圧も調査したが劣化する傾向であることを確認した。Further, it was confirmed that the interstitial oxygen concentration of the silicon single crystal was not affected by the difference in the interstitial oxygen concentration in the heat treatment in the high temperature region of the present invention. The inventor has conducted a heat treatment in the high-temperature region of the present invention, polished 50 μm, and also examined the oxide film breakdown voltage in a region where interstitial oxygen does not diffuse outwardly.
【００２５】従って、本発明の高温領域の熱処理におい
ては、シリコンウェーハ表面近傍において格子間酸素の
外方拡散が生じそれに伴い格子間酸素起因の欠陥をほと
んど消滅させる効果がある。Therefore, in the heat treatment in the high temperature region according to the present invention, out-diffusion of interstitial oxygen occurs near the surface of the silicon wafer, which has the effect of almost eliminating defects caused by interstitial oxygen.
【００２６】[0026]
【発明の効果】本発明の高温域での熱処理を施すること
により、チョクラルスキー法により製造されたシリコン
単結晶ウェーハ中のフローパターン欠陥はほとんど消滅
しかつシリコンウェーハ表面の格子間酸素に起因した欠
陥密度も減少し、その後の熱酸化膜中に取り込まれる微
小欠陥はほとんど無い。従って、生産効率が悪いとされ
ていた結晶成長速度の遅いチョクラルスキー法による結
晶育成法を用いなくとも、広範囲にわたる結晶成長速度
で製造したシリコンウェーハに対して酸化膜耐圧特性の
優れたＭＯＳ型半導体デバイスを得ることが可能となっ
た。By performing the heat treatment in the high temperature range of the present invention, the flow pattern defects in the silicon single crystal wafer manufactured by the Czochralski method almost disappear and are caused by interstitial oxygen on the silicon wafer surface. The defect density also decreases, and there is almost no minute defect introduced into the thermal oxide film thereafter. Therefore, even without using the crystal growth method based on the Czochralski method, which has a low crystal growth rate, which is considered to be inferior in production efficiency, a MOS type with excellent oxide film breakdown voltage characteristics can be used for silicon wafers manufactured at a wide range of crystal growth rates. It has become possible to obtain semiconductor devices.
【図１】実験例１における結晶成長速度と酸化膜耐圧の
良品率の関係を示すグラフである。FIG. 1 is a graph showing the relationship between the crystal growth rate and the yield rate of oxide film breakdown voltage in Experimental Example 1.
【図２】実験例１におけるフローパターン欠陥と酸化膜
耐圧の良品率の関係を示すグラフである。FIG. 2 is a graph showing a relationship between a flow pattern defect and a yield rate of oxide film breakdown voltage in Experimental Example 1.
【図３】実験例２における熱処理とフローパターン欠陥
密度との関係を示すグラフである。FIG. 3 is a graph showing the relationship between heat treatment and flow pattern defect density in Experimental Example 2.
【図４】実験例３及び実施例１における熱処理温度と酸
化膜耐圧の良品率の関係を示すグラフである。FIG. 4 is a graph showing the relationship between the heat treatment temperature and the yield rate of oxide film breakdown voltage in Experimental Example 3 and Example 1.
【図５】実施例２における結晶成長速度と酸化膜耐圧の
良品率を示すグラフである。FIG. 5 is a graph showing the yield rate of crystal growth rate and oxide film breakdown voltage in Example 2.
Claims (2)
シリコン単結晶ウェーハを１２５０〜１３００℃の高温
領域で０．５〜４時間の熱処理を施し、この時に形成さ
れる酸化膜を除去し清浄化した後に熱酸化膜を形成する
ことを特徴とする半導体基板の処理方法。1. A silicon single crystal wafer manufactured by the Czochralski method is subjected to a heat treatment at a high temperature range of 1250-1300 ° C. for 0.5-4 hours to remove and clean an oxide film formed at this time. A method for treating a semiconductor substrate, comprising forming a thermal oxide film later.
囲気中で行うことを特徴とする半導体基板の処理方法。2. A method for treating a semiconductor substrate, wherein the heat treatment is performed in a dry oxygen or oxygen nitrogen atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10206292A JP2602598B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor substrate processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10206292A JP2602598B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor substrate processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05275299A JPH05275299A (en) | 1993-10-22 |
| JP2602598B2 true JP2602598B2 (en) | 1997-04-23 |
Family
ID=14317287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10206292A Expired - Lifetime JP2602598B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor substrate processing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2602598B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3385981B2 (en) | 1998-06-01 | 2003-03-10 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2000294549A (en) * | 1999-02-02 | 2000-10-20 | Nec Corp | Semiconductor device and manufacture of the same |
-
1992
- 1992-03-27 JP JP10206292A patent/JP2602598B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05275299A (en) | 1993-10-22 |
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