JPH01308051A - Internal wiring structure of semiconductor device - Google Patents
Internal wiring structure of semiconductor deviceInfo
- Publication number
- JPH01308051A JPH01308051A JP13905788A JP13905788A JPH01308051A JP H01308051 A JPH01308051 A JP H01308051A JP 13905788 A JP13905788 A JP 13905788A JP 13905788 A JP13905788 A JP 13905788A JP H01308051 A JPH01308051 A JP H01308051A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- hole
- contact
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 94
- 239000011229 interlayer Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 12
- 150000002739 metals Chemical class 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 241000282376 Panthera tigris Species 0.000 description 1
- 241000282330 Procyon lotor Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の内部配線構造、特に多層配線構造の改良に
関し
コンタクト窓部近傍における金属配線内の電流密度の増
大を抑えてこの部分におけるマイグレーシランによる断
線の発生を防止することを目的とし、
下層配線（２）と上層配線（６）との電気的接続が、該
上下層配線間の層間絶縁膜（３）に設けたスルーホール
（４）内に埋込まれた前記下層配線（２）及び上層配線
（６）と異なる種類の導電材料よりなる導電体層（５）
を介してなされる半導体装置の内部配線構造において、
該下層配線（２）及びに１層配線（６）の両方若しくは
何れか一方と該導電体層（５）との接触部分に、該導電
体層（５）と同種の導電材料よりなり、且つ該スルーホ
ール（４）の開口面積より広い面積を有する中間層（７
） （８）を介在せしめて構成する。[Detailed Description of the Invention] [Summary] Regarding the improvement of the internal wiring structure of a semiconductor device, especially the multilayer wiring structure, it is possible to suppress the increase in current density in the metal wiring in the vicinity of the contact window and to prevent wire breakage due to migration silane in this part. In order to prevent this, the electrical connection between the lower layer wiring (2) and the upper layer wiring (6) is buried in a through hole (4) provided in the interlayer insulating film (3) between the upper and lower layer wiring. a conductive layer (5) made of a different type of conductive material from the lower layer wiring (2) and the upper layer wiring (6);
In the internal wiring structure of a semiconductor device made through
A contact portion between both or either of the lower layer wiring (2) and the first layer wiring (6) and the conductor layer (5) is made of the same type of conductive material as the conductor layer (5), and An intermediate layer (7) having an area larger than the opening area of the through hole (4).
) Constructed by interposing (8).
本発明は半導体装置の内部配線構造、特に多層配線構造
の改良に関する。The present invention relates to improvements in internal wiring structures of semiconductor devices, particularly in multilayer wiring structures.
近年の半導体装置の高集積化に伴い、半導体装置の内部
配線は多層化されつつある。2. Description of the Related Art As semiconductor devices have become more highly integrated in recent years, the internal wiring of semiconductor devices has become multilayered.
配線を多層化する場合には、スルーホール部の平坦化を
図って該スルーホール部における上層配線の断線を防止
するために、高アスペクト比即ち深さと開口幅の比が大
きいスルーホールは、その開口面まで導電体で埋込む必
要がある。When multi-layering wiring, in order to flatten the through-hole part and prevent disconnection of the upper layer wiring in the through-hole part, through-holes with a high aspect ratio, that is, a large ratio of depth to opening width, should be It is necessary to fill the opening with conductor.
このため選択化学気相成長（ＣＶ Ｄ）によるタングス
テン（Ｗ＞またはタングステンシリサイド（ＷＳｉＸ）
によるスルーホールの埋込みが行われているが、Ｗまた
はＷ Ｓ ｉ Ｘよりなる埋込み層に接Ｕ７ているアル
ミニウム（八１）等よりなる配線部分は、該埋込み層側
にＡＩ等の配線金属の供給源がないためにエレクトロマ
イグレーションに対して弱いという問題があり、改善が
望まれている。For this purpose, tungsten (W>) or tungsten silicide (WSiX) is grown by selective chemical vapor deposition (CVD).
However, the wiring part made of aluminum (81) etc. that is in contact with the buried layer made of W or WSiX has a wiring metal such as AI on the side of the buried layer. There is a problem that it is vulnerable to electromigration due to the lack of a supply source, and improvements are desired.
第３図は上記スルーホールが配線金属と異なる導電体で
埋込まれてスルーホール部の平坦化が図られた従゛Ｙの
多層配線構造を示ず側断面図で、図中、１１は下層の絶
縁膜が形成された基板、１２はＡ１単体若しくはアルミ
ニウムーシリコン（Ａ Ｉ −Ｓ ｉ ） 合金等より
なる下層ＡＩ配配線１３は燐珪酸ガラス（ＰＳＧ）等よ
りなる層間絶縁膜、１４はスルーホール、１５は選択Ｃ
ＶＤ成長によるＷまたはＷ Ｓ ｉつよりなる埋込み導
電体層、１６はＡＩ単体若しくはＡｌ−５ｉ合金よりな
る」−層へ１配線を示す。FIG. 3 is a side cross-sectional view (not shown) of a multilayer wiring structure of Y in which the through-holes are filled with a conductor different from the wiring metal to flatten the through-hole parts, and in the figure, 11 is the lower layer. 12 is a substrate on which an insulating film is formed; 12 is a lower layer AI wiring made of A1 alone or an aluminum-silicon (AI-S i ) alloy, etc.; 13 is an interlayer insulating film made of phosphosilicate glass (PSG), etc.; 14 is a through layer; Hall, 15 is selection C
A buried conductor layer made of W or W S i by VD growth, and 16 indicate one wiring to a layer made of AI alone or an Al-5i alloy.
同図に示されるように従来構造においては、スルーホー
ル１４内に埋込まれた導電体層１５が微小なスルーボー
ル１４の開ｌ］面積と等しい面積で下層へ１配線１２及
び−ｆｘ層へ１配線１６に直に接し７て下層Ａ１配線１
２とに層重配線１５とのコンタクトがとられてなってい
た。As shown in the figure, in the conventional structure, the conductor layer 15 embedded in the through hole 14 is connected to the lower layer 1 wiring 12 and the -fx layer in an area equal to the opening area of the minute through ball 14. 1 wiring 16 directly in contact with 7 and lower layer A1 wiring 1
Contact with the layered wiring 15 was established between the two.
しかし上記従来構造においては、スルーホール１４内に
埋込まれた導電体層１５と下層Δｌ配線１２及び１・層
Ａ ｌ配線１６とがスルーホール１４の開口面積に等Ｕ
７い狭い面積で接触しているために、該上層ＡＩ配線１
６と下層Ａ１配線１２間に通電がなされた時、上記へ１
配線１２及び１６と導電体層１５との接触部近傍の電流
密度が非常に大きくなる。However, in the above conventional structure, the conductor layer 15 embedded in the through hole 14, the lower layer Δl wiring 12 and the 1 layer Al wiring 16 are equal to the opening area of the through hole 14.
Because of the contact in a narrow area of 7, the upper layer AI wiring 1
When electricity is applied between 6 and the lower layer A1 wiring 12, the above 1
The current density near the contact portions between the wirings 12 and 16 and the conductor layer 15 becomes extremely large.
そ、のため、この大電流密度の電流によって上記上層へ
１配線１６或いは下層ＡＩ配配線２における導電体層１
５との接触部近傍のＡＩ原子がマイグレーションを起こ
し易くなり、このマイグレーションが−に配接触部から
離れる方向に起こると、Ｗ芳しくはＷ Ｓ ｉ Ｘ等よ
りなる埋込み導電体層１５からはへ１原子の補給がない
ために、そのＡＩ配配線該導電体Ｎ４５との接触部近傍
において断線を生ずる可能性が高くなるという問題があ
った。Therefore, this high current density current causes the conductor layer 1 in the upper layer 1 wiring 16 or the lower layer AI wiring 2 to
When the AI atoms near the contact portion with 5 tend to migrate, and this migration occurs in the direction away from the contact portion with 5, the buried conductor layer 15 made of W or W Si Since there is no replenishment of atoms, there is a problem that there is a high possibility that a disconnection will occur near the contact portion of the AI wiring with the conductor N45.
そこで本発明は、スルーホール部近傍における金属配線
内の電流密度の増大を抑えてこの部分におけるマイグレ
ーションによる断線の発生を防止することを目的とする
。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to suppress the increase in current density in the metal wiring in the vicinity of the through-hole portion, thereby preventing the occurrence of disconnection due to migration in this portion.
（課題を解決するための手段〕
上記課題は、下層配線（２）と上層配線（６）との電気
的接続が、該上下層配線間の層間絶縁膜（３）に設けた
スルーホール（４）内に埋込まれた前記下層配線（２）
及び下層配線（６）と異なる種類の導電＋Ａ料よりなる
導電体層（５）を介してなされる半導体装置の内部配線
構造において、該下層配線（２）及び上層配線（６）の
両方若しくは何れか一方と該導電体層（５）との接触部
分に、該導電体層（５）と同種の導電材料よりなり、且
つ該スルーホール（４）の開口面積より広い面積を有す
る中間層（７）を介在せしめた本発明による半導体装置
の内部配線構造によって解決される。(Means for Solving the Problem) The above problem is such that the electrical connection between the lower layer wiring (2) and the upper layer wiring (6) is made through a through hole (4) provided in the interlayer insulating film (3) between the upper and lower layer wirings. ) The lower layer wiring (2) embedded in
In the internal wiring structure of a semiconductor device, which is formed through a conductive layer (5) made of a conductive +A material different from the lower layer wiring (6), both or either of the lower layer wiring (2) and the upper layer wiring (6) An intermediate layer (7) made of the same type of conductive material as the conductor layer (5) and having an area larger than the opening area of the through hole (4) is provided at the contact portion between one side and the conductor layer (5). ) is solved by the internal wiring structure of the semiconductor device according to the present invention.
即ち本発明の構造においては、スルーホール（４）内の
埋込み導電体層（５）と配線金属（２）及び（６）が接
触する部分に該埋込み導電体層（５）と同種の導電体に
よる中間層（７）を設ける。この中間層（７）は、接触
部における配線金属（２）及び（６）内の電流密度を小
さくするために、スルーホール（４）の開口面積よりも
広い面積にして接触面積を大きくし、１つ接触部の電位
を等しくするような構造を持つ。That is, in the structure of the present invention, the same type of conductor as the buried conductor layer (5) is placed in the portion where the buried conductor layer (5) in the through hole (4) contacts the wiring metals (2) and (6). An intermediate layer (7) is provided. In order to reduce the current density in the wiring metals (2) and (6) at the contact portion, this intermediate layer (7) is made larger in area than the opening area of the through hole (4) to increase the contact area. It has a structure that equalizes the potential of one contact part.
本発明の構造においては、■−記のように配線金属（２
）及び（６）とスルーホール埋込み導電体層（５）との
接触面積が中間層（７）を介して大きくとれるので、該
上層配線（６）と下層配線（２）間に通電Ｌ７た際、ス
ルーホール（４）近傍部における配線（２）及び（６）
内の電流密度は他領域と（Ｊぼ等しい程度に減少する。In the structure of the present invention, the wiring metal (2
) and (6) and the through-hole buried conductor layer (5) can be made large via the intermediate layer (7), so when current is applied between the upper layer wiring (6) and the lower layer wiring (2), , wiring (2) and (6) near the through hole (4)
The current density in the area decreases to about the same extent as the other area (J).
そのため、スルーホール近傍部における配線金属原子の
エレクトロマイグレーションが抑制され、該多層配線構
造における上層及び下層の配線の層間接続部におけろ断
線発生の確率は大幅に減少する。Therefore, electromigration of wiring metal atoms in the vicinity of the through hole is suppressed, and the probability of disconnection occurring at the interlayer connection between the upper and lower wiring in the multilayer wiring structure is significantly reduced.
以下本発明を、図示実施例により具体的に説明する。 The present invention will be specifically explained below with reference to illustrated embodiments.
第１図は本発明の一実施例の模式平面図（ａｌ及び模式
側断面図（ｂ）で、第２図は本発明の他の実施例の模式
平面図（ａｌ及び模式側断面図（ｂｌである。FIG. 1 is a schematic plan view (al and schematic side sectional view (b)) of one embodiment of the present invention, and FIG. 2 is a schematic plan view (al and schematic side sectional view (b)) of another embodiment of the present invention. It is.
全図を通じ同一対象物は同一符合で示す。Identical objects are indicated by the same reference numerals throughout the figures.
第１図において、■は上面に絶縁膜が形成されている基
板、２はＡｌｔｐ一体若しくは八１合金よりなる厚さ０
．５〜ｌｐｍ、幅０．６〜２ｐｍ程度の下層＾ｌ配線、
静は１〜４μｍ角程度の同配線のコンタクト用拡大部、
３はＰＳＧ等よりなる厚さ１μｍ程度の層間絶縁膜、４
は０．５〜２μｍ角程度のスルーホール、５はＷ若しく
はＷ Ｓ ｉ ｚよりなる埋込み導電層、６はＡｌｌ棒
体しくは＾１合金よりなる厚さ０．５〜１μｍ、幅０．
６〜２μｍ程度の十層へ１配線、６八は１〜４μｍ角程
度の同配線のコンタクト用拡大部、７は厚さ０．１〜０
．２μｍ程度のＷ若しくはＷＳｉＪよりなる１〜４ｔｔ
ｍ角程度の中間層を示す。In FIG. 1, ■ is a substrate on which an insulating film is formed, and 2 is a substrate made of Altp or 81 alloy with a thickness of 0.
．． 5~lpm, lower layer wiring with a width of about 0.6~2pm,
For static, the enlarged part for contact of the same wiring is about 1 to 4 μm square,
3 is an interlayer insulating film with a thickness of about 1 μm made of PSG or the like; 4
5 is a buried conductive layer made of W or W S i z, and 6 is an Al rod or ^1 alloy with a thickness of 0.5 to 1 μm and a width of 0.
1 wiring in 10 layers of about 6 to 2 μm, 68 is an enlarged part for contact of the same wiring of about 1 to 4 μm square, 7 is 0.1 to 0 thick
．． 1 to 4 tt made of W or WSiJ of about 2 μm
It shows an intermediate layer of about m square.
例えばこの図に示すように本発明に係るＡＩ多層配線構
造は、下層ＡＩ配配線及びＬ層＾１配線６とスルーホー
ル４内の埋込み導電層５との接触部のそれぞれに、該ス
ルーホール４内の埋込み導電層５と同種の導電材料であ
るＷ若しくはＷ Ｓ ｉ ｚ層よりなるスルーホール４
より広い面積例えば配線のコンタクト用拡大部２八、Ｅ
ＲＡとほぼ等しい面積の中間層７及び８を設け、これに
よってスルーホール４部における＾１配線２及び６とＷ
若しくはＷ Ｓ ｉ Ｚよりなる埋込み導電Ｍ５との接
触面積を拡大して該スルーホール４部近傍のへ１配ｖＡ
２及び６内の電流密度の増大を抑え、＾ｌのエレクトロ
マイグレーションを防止する。For example, as shown in this figure, the AI multilayer wiring structure according to the present invention has a through hole 4 at each contact portion between the lower layer AI wiring and the L layer^1 wiring 6 and the buried conductive layer 5 in the through hole 4. The through hole 4 is made of a W or W Si z layer made of the same type of conductive material as the buried conductive layer 5 inside.
Wider area, e.g. enlarged area 28, E for wiring contacts
Intermediate layers 7 and 8 with approximately the same area as RA are provided, and thereby ^1 wirings 2 and 6 and W in the through hole 4 section are provided.
Or, by expanding the contact area with the buried conductive M5 made of W Si Z, one distribution vA is made in the vicinity of the four through holes.
2 and 6 to suppress the increase in current density and prevent electromigration of ^l.
なおこの構造は、形成に際して中間層７及び８のパター
ニングをＡＩ配線２及び６のパターニングと別個に行う
必要がある。Note that when forming this structure, it is necessary to pattern the intermediate layers 7 and 8 separately from the patterning of the AI wirings 2 and 6.
第２図に示す他の実施例においては、コンタクト用拡大
部加を含む下層へ１配線２の全面上、及びコンタクト用
拡大部６八を含むＬ層重配線６の下面全体にスルーホー
ル４内の埋込み導電層５と同種導電材料であろＷ若しく
はＷＳｉｚ ｓよりなる中間層７が配設される。この構
造は中間層７と下層＾１配線２、及び上層へ１配線６と
中間層８が、それぞれ同時にパターニングできるので、
前記実施例よりも製造の効率がよい。またこの構造は７
ンタクト窓４近傍領域の旧のエレクトロマイグレーショ
ンを防止する他に、＾■配線２及び６全域のエレクトロ
マイグレーション防止する効果もある。In another embodiment shown in FIG. 2, the through hole 4 is formed on the entire surface of the wiring 2 in the lower layer including the enlarged contact portion 68, and on the entire lower surface of the L layer heavy interconnect 6 including the contact enlarged portion 68. An intermediate layer 7 made of the same type of conductive material as the buried conductive layer 5, such as W or WSizs, is provided. In this structure, the intermediate layer 7, the lower layer ^1 wiring 2, and the upper layer 1 wiring 6 and the intermediate layer 8 can be patterned simultaneously.
The manufacturing efficiency is better than that of the previous embodiment. Also, this structure is 7
In addition to preventing electromigration in the area near the contact window 4, there is also the effect of preventing electromigration in the entire area of the wirings 2 and 6.
なお中間層を設けるのは、電流の向きによりエレクトロ
マイグレーションの発生し易い何れか一方の側みであっ
ても良い。Note that the intermediate layer may be provided on either side where electromigration is likely to occur depending on the direction of the current.
また埋込み導電層には、上記実施例に示される以外の高
融点金属若しくは高融点金属シリサイドも用いられる。Further, a refractory metal or a refractory metal silicide other than those shown in the above embodiments may also be used for the buried conductive layer.
また本発明は、配線材料に銅若しくは銅合金を用いる際
にも適用される。The present invention is also applicable when copper or copper alloy is used as the wiring material.
以上説明のように本発明によれば、下層配線と上層配線
との電気的接続が、該上下層配線間の層間絶縁膜に設け
たスルーホール内に埋込まれたＷ或いはＷ Ｓ ｉ ２
等の°下層及び上層の配線材料以外の導電層を介してな
される半導体装置の内部配線構造に、打いて、スルーホ
ール内に埋込まれた導電層に接する部分の配線内部の電
流密度を減少できるので、この部分におけろ配線材料の
エレクトロマイグレーションによる断線が防止され、該
多層配線の信頼性が向上する。As described above, according to the present invention, the electrical connection between the lower layer wiring and the upper layer wiring is made using the W or W Si 2 embedded in the through hole provided in the interlayer insulating film between the upper and lower layer wiring.
etc. into the internal wiring structure of the semiconductor device, which is made through conductive layers other than the lower and upper wiring materials, to reduce the current density inside the wiring in the part that contacts the conductive layer embedded in the through hole. Therefore, disconnection due to electromigration of the wiring material in this portion is prevented, and the reliability of the multilayer wiring is improved.
第１図は本発明の一実施例の模式平面図（ａｌ及び模式
側断面図（ｔ＋１、
第２図は本発明の他の実施例の模式平面図（ａｌ及び模
式側断面図（ｂｌ、
第３図は従来構造の模式側断面図
である。
図において、
１は基板、
２は下層へ１配線、
２Ａはコンタクト用拡大部、
３は層間絶縁膜、
４はスルーホール、
５はＷ若しくはＷ Ｓ ｉ ２よりなる埋込み導電層、
６は上層へｌ配線、
６Ａはコンタクト用拡大部、
７はＷ若り、 ＜はＷ Ｓ ｉ ２層よりなる中間層を
示す。
（υ）＋ １ 図
（ｂ） （口・］ ビ町 宜 Ｄコ
本心’月の−ｒ′プ西、４列の狸弐図
ｇ ブ 、Ｓ
（θ）−Ｆ−面 図
（１０） イ只′Ｊ ゴブＴ 面 ｆｆ本本
発明リイ已の寅万色４列６り不贋へ５弓第 ２ 呂FIG. 1 is a schematic plan view (al) and a schematic side sectional view (t+1) of one embodiment of the present invention, and FIG. 2 is a schematic plan view (al and a schematic side sectional view (t+1) of another embodiment of the invention. Figure 3 is a schematic side sectional view of a conventional structure. In the figure, 1 is a substrate, 2 is one wiring to the lower layer, 2A is an enlarged part for contact, 3 is an interlayer insulating film, 4 is a through hole, and 5 is W or W. a buried conductive layer made of S i 2;
6 indicates an interconnection to the upper layer, 6A indicates an enlarged contact area, 7 indicates a W layer, and < indicates an intermediate layer consisting of two W Si layers. (υ) + 1 Figure (b) (mouth・) Bi-machi yi D Ko Honshin'Moon's-r' Pu West, 4 rows of raccoon 2 diagram g Bu, S (θ)-F- side Figure (10) It's just 'J gob T side ff this invention rii's tiger million colors 4 rows 6 ri fake 5 bow 2nd ro
Claims (1)
該上下層配線間の層間絶縁膜（３）に設けたスルーホー
ル（４）内に埋込まれた前記下層配線（２）及び上層配
線（６）と異なる種類の導電材料よりなる導電体層（５
）を介してなされる半導体装置の内部配線構造において
、 該下層配線（２）及び上層配線（６）の両方若しくは何
れか一方と該導電体層（５）との接触部分に、該導電体
層（５）と同種の導電材料よりなり、且つ該スルーホー
ル（４）の開口面積より広い面積を有する中間層（７）
（８）を介在せしめたことを特徴とする半導体装置の内
部配線構造。[Claims] The electrical connection between the lower layer wiring (2) and the upper layer wiring (6) is
a conductor layer (made of a conductive material of a different type from the lower layer wiring (2) and the upper layer wiring (6) embedded in the through hole (4) provided in the interlayer insulating film (3) between the upper and lower layer wirings); 5
), in which the conductor layer (5) is in contact with the conductor layer (5) and both or either of the lower layer interconnect (2) and the upper layer interconnect (6). An intermediate layer (7) made of the same type of conductive material as (5) and having an area larger than the opening area of the through hole (4).
An internal wiring structure of a semiconductor device characterized by interposing (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13905788A JPH01308051A (en) | 1988-06-06 | 1988-06-06 | Internal wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13905788A JPH01308051A (en) | 1988-06-06 | 1988-06-06 | Internal wiring structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01308051A true JPH01308051A (en) | 1989-12-12 |
Family
ID=15236479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13905788A Pending JPH01308051A (en) | 1988-06-06 | 1988-06-06 | Internal wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01308051A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0442951A (en) * | 1990-06-07 | 1992-02-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5939789A (en) * | 1994-02-28 | 1999-08-17 | Hitachi, Ltd. | Multilayer substrates methods for manufacturing multilayer substrates and electronic devices |
| US6566755B1 (en) * | 1993-12-29 | 2003-05-20 | Intel Corporation | Method of forming a high surface area interconnection structure |
-
1988
- 1988-06-06 JP JP13905788A patent/JPH01308051A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0442951A (en) * | 1990-06-07 | 1992-02-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US6566755B1 (en) * | 1993-12-29 | 2003-05-20 | Intel Corporation | Method of forming a high surface area interconnection structure |
| US6787444B2 (en) | 1993-12-29 | 2004-09-07 | Intel Corporation | Interconnection structures and methods of fabrication |
| US5939789A (en) * | 1994-02-28 | 1999-08-17 | Hitachi, Ltd. | Multilayer substrates methods for manufacturing multilayer substrates and electronic devices |
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