JPH01302795A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPH01302795A JPH01302795A JP32064888A JP32064888A JPH01302795A JP H01302795 A JPH01302795 A JP H01302795A JP 32064888 A JP32064888 A JP 32064888A JP 32064888 A JP32064888 A JP 32064888A JP H01302795 A JPH01302795 A JP H01302795A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- copper
- solder resist
- plating
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 40
- 238000007747 plating Methods 0.000 claims abstract description 39
- 229910052802 copper Inorganic materials 0.000 claims abstract description 33
- 239000010949 copper Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 17
- 239000000126 substance Substances 0.000 abstract description 12
- 239000011889 copper foil Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000008139 complexing agent Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高密度化に最適なプリント回路板の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a printed circuit board that is optimal for high density.
プリント回路板を製造するには、従来、１８〜３５μｍ
の＠苗土に３０μｍ前後の電気銅めっきを析出させ、ド
ライフィルムを用いたテンティング法または孔埋めによ
る印刷法により回路形成後エツチングにて回路を独立さ
せていた。To manufacture printed circuit boards, traditionally 18-35 μm
Electrolytic copper plating with a thickness of around 30 μm was deposited on seedling soil, and circuits were formed using a tenting method using a dry film or a printing method by filling holes, and then etched to make the circuits independent.
しかし、高密度のプリント回路板に上記従来技術を適用
した場合１次のような問題が生じる。プリント回路板を
高密度化すると必然的にスルーホール孔径が小さくなる
が、この場合、エツチングレジストを形成する際の位置
ずれが問題となる。However, when the above-mentioned conventional technology is applied to a high-density printed circuit board, the following problem occurs. When the density of a printed circuit board is increased, the diameter of the through hole inevitably becomes smaller, but in this case, positional deviation when forming an etching resist becomes a problem.
エツチングレジストを形成する前にスルーホールにめっ
きをした場合、位置ずれを起こすとスルーホール内にエ
ラチン・ダ液が入り込み、スルーホール内のめっき及び
銅箔層が侵食されるのである。If the through holes are plated before forming the etching resist, if misalignment occurs, the eratin da solution will enter the through holes, corroding the plating and copper foil layer inside the through holes.
この状況を第１１図に示す。第１１図において（ａ）は
、エツチング中のスルーホール部断面図、（ｂ）は、エ
ツチング後の同断面図であり、ドライフィルム５の左方
向のずれにより、スルーホール内にエツチング液１２が
浸入し、スルーホール内のめっき層４及び銅箔層１が侵
食されている。This situation is shown in FIG. In FIG. 11, (a) is a cross-sectional view of the through-hole during etching, and (b) is the same cross-sectional view after etching. Due to the leftward shift of the dry film 5, the etching liquid 12 leaks into the through-hole. The plating layer 4 and copper foil layer 1 inside the through hole are being eroded.
しかし、だからといってめっきをエツチング後に行なう
と１回路部分は、第１２図のようになり、ライン幅の増
大につながる。第１２図においては、エツチングにより
独立した銅張り層板の銅箔１の側面にもめっき層１３が
付着し、ライン幅が増加している。However, if plating is performed after etching, one circuit portion will become as shown in FIG. 12, leading to an increase in line width. In FIG. 12, the plating layer 13 is also attached to the side surface of the copper foil 1 of the independent copper-clad laminate by etching, and the line width is increased.
一方、第８図にＡで示すように電気めっきでは、めっき
厚バラツキが大きく（第８図中、Ａは、電気めっきによ
る銅めっき厚と厚さのバラツキの関係、Ｂは、化学めっ
きによる銅めっき厚と厚さのバラツキの関係を示す）、
それが第１０図に示す銅厚と最小ライン幅の関係図中の
、最小ライン幅のバラツキの増加となってしまう（第１
０図は、エツチングレジストにドライフィルムを用い、
アルカリ型のエツチング液を使用したときの銅厚と最小
ライン幅の関係を示す）。さらに、高密度化が要求され
てくると必然的にスルーホール孔径も小さくなり、相対
的な板厚が増加することとなる。電気めっきを用いる場
合、均一電着性が悪く、孔径が小さくなるにつれスルー
ホール内のめっきが薄くなり、スルーホール強度の劣化
となる。そのため、従来の電気めっきによるプリント回
路板の製造方法では、スルーホールの孔径は、０．６ｍ
が限度であった。その関係を第９図に示す。第９図にお
いて、Ａ及びＢは、第８図におけると同様に、それぞれ
電気めっき及び化学めっきについての銅めっき厚と厚さ
のバラツキの関係を示す。従って、必然的に高密度のプ
リント回路板では、化学銅めっきを用いることとなるの
であるが、化学銅めっきは、めっき膜の形成に時間を要
するので、効率的に行なうことが必要である。On the other hand, as shown by A in Fig. 8, there is a large variation in plating thickness in electroplating (in Fig. 8, A is the relationship between the copper plating thickness and thickness variation due to electroplating, and B is the relationship between copper plating thickness and thickness variation due to chemical plating. (shows the relationship between plating thickness and thickness variation),
This results in an increase in the variation in the minimum line width in the relationship diagram between copper thickness and minimum line width shown in Figure 10 (first
Figure 0 uses dry film as the etching resist.
(Shows the relationship between copper thickness and minimum line width when using an alkaline etching solution). Furthermore, as higher density is required, the diameter of the through-hole inevitably becomes smaller, and the relative thickness of the plate increases. When electroplating is used, uniform electrodeposition is poor, and as the hole diameter becomes smaller, the plating inside the through hole becomes thinner, resulting in deterioration of the through hole strength. Therefore, in the conventional manufacturing method of printed circuit boards using electroplating, the diameter of the through hole is 0.6 m.
was the limit. The relationship is shown in FIG. In FIG. 9, A and B indicate the relationship between copper plating thickness and thickness variation for electroplating and chemical plating, respectively, as in FIG. 8. Therefore, chemical copper plating is inevitably used for high-density printed circuit boards, but since chemical copper plating takes time to form a plating film, it is necessary to perform it efficiently.
しかし、上記従来技術に化学銅めっきを適用した場合、
スルーホール部の銅層を必要な厚さまで形成しようとす
ると、銅箔上には必要以上の化学銅めっきが形成され、
効率的でないばかりか、エツチング時における、銅箔上
の化学銅めっきの厚さが厚すぎ、良好な回路ラインを形
成することができない。However, when chemical copper plating is applied to the above conventional technology,
If you try to form the copper layer in the through-hole part to the required thickness, more chemical copper plating will be formed on the copper foil than necessary.
Not only is it not efficient, but the thickness of the chemical copper plating on the copper foil during etching is too thick, making it impossible to form good circuit lines.
そこで、これらの問題を解決する方法として、めっきを
スルーホール部及びランド部のみに限ることが考えられ
る。Therefore, as a method to solve these problems, it is conceivable to limit plating to only the through-hole portions and land portions.
しかし、露光法によりソルダーレジスト層を形成するこ
とによりスルーホール及びランド部のみにめっきする場
合に新たな問題が生ずる。以下このことについて説明す
る。However, a new problem arises when forming a solder resist layer using an exposure method and plating only the through holes and land portions. This will be explained below.
露光法によりソルダーレジスト層を形成するには、まず
未硬化のソルダーレジストを基板全面に塗布し、ソルダ
ーレジストの不要な部分に露光マスクを施し、次に紫外
光照射し、露光マスクのない部分を硬化させる方法が取
られる。To form a solder resist layer using the exposure method, first apply uncured solder resist to the entire surface of the substrate, apply an exposure mask to the unnecessary parts of the solder resist, and then irradiate the solder resist with ultraviolet light to remove the parts without the exposure mask. A method of hardening is used.
そこで問題となるのが、第１３図に示すような露光マス
ク１５のない部分からスルーホール内への紫外光１４の
漏れである。この漏れにより、スルーホール内に付着し
たソルダーレジスト１６をも硬化させてしまうのである
。これは、高密度のプリント回路板特有の問題である。The problem here is that ultraviolet light 14 leaks into the through-hole from the portion where the exposure mask 15 is not provided, as shown in FIG. This leakage also hardens the solder resist 16 adhering to the inside of the through hole. This is a problem unique to high density printed circuit boards.
上記問題を解決するため、本発明では、露光法によりソ
ルダーレジスト層を形成する前に、薄い銅層を予め形成
したのである。In order to solve the above problem, in the present invention, a thin copper layer is previously formed before forming a solder resist layer by an exposure method.
露光マスクのない部分からの紫外光の漏れは、予め形成
した薄い銅層によって遮断され、スルーホール内に付着
したソルダーレジストを硬化させることはない。Leakage of ultraviolet light from areas without an exposure mask is blocked by the thin copper layer formed in advance, and does not harden the solder resist adhered within the through-holes.
以下に、実施例を用いて本発明を一層詳しく説明するが
、それは例示にすぎず、本発明の枠を超えることなく、
いろいろな変形や改良があり得ることは、勿論である。The present invention will be explained in more detail below using examples, but these are merely illustrative and do not go beyond the scope of the present invention.
Of course, various modifications and improvements are possible.
第１図に示す樹脂板２の両面に１８μｍまたは３５μｍ
の銅箔を有する積層板にドリルまたはパンチングにてス
ルーホール孔３をあけ、第２図のようにする。孔あけ後
処理としてパリ除去を行なった後、表面及び孔内を含め
全面を脱脂、清浄化、触媒付与を施し、硫酸銅、錯化剤
ベースの還元性化学銅めっき浴に浸漬し、第３図のごと
く銅めっき膜４を２〜１０μｍ析出させる。この銅めっ
きが、後に紫外光遮断の役割をする。エツチング液のス
ルーホール内への浸入を防ぐためスルーホール孔３内に
アルカリ可溶型インク１１を挿入した後、そのものにド
ライフィルム５を用いた露光法にてテンティングを行な
い、第４図のように回路形成する。アンモニウム水、塩
化アンモニウムよりなるアルカリエツチング液にて回路
以外の銅を溶解除去し、ドライフィルム５を塩化メチレ
ン等を用いて剥離し、独立ライン６及びランド部７を形
成し、アルカリ可溶型インク１１を溶解除去し、第５図
に示すように回路を独立させる。エポキシ樹脂をベース
にした高耐薬品性のソルダーレジスト９をランド部７及
びスルーホール部８を除く全面に露光法により形成する
。この際、先に形成したスルーホール内の銅めっき層４
が第１３図における紫外光１４の遮断の役割をする。露
光マスク１５のない部分からの紫外光１４の漏れは、先
に形成した薄い銅めっき層４によって遮断され、スルー
ホール３内に付着したソルダーレジストを硬化させるこ
とはない。こうして、第６図のようにした後、露出して
いるランド部７及びスルーホール部８に再度硫酸網、錯
化剤ベースの化学銅めっき浴に浸漬する方法で、銅めっ
き膜１０を厚さ１５〜３０μｍ析出させ、第７図のごと
くなる。18 μm or 35 μm on both sides of the resin plate 2 shown in FIG.
A through-hole hole 3 is made by drilling or punching in a laminate having copper foil, as shown in FIG. After removing paris as a post-drilling treatment, the entire surface, including the surface and inside of the hole, is degreased, cleaned, and catalyzed, and then immersed in a reducing chemical copper plating bath based on copper sulfate and a complexing agent. As shown in the figure, a copper plating film 4 of 2 to 10 μm is deposited. This copper plating will later play a role in blocking ultraviolet light. After inserting the alkali-soluble ink 11 into the through-hole hole 3 to prevent the etching liquid from entering the through-hole, tenting is performed using an exposure method using a dry film 5, as shown in FIG. Form the circuit as follows. Copper other than the circuit is dissolved and removed using an alkaline etching liquid consisting of ammonium water and ammonium chloride, and the dry film 5 is peeled off using methylene chloride or the like to form independent lines 6 and land portions 7, and alkali-soluble ink is removed. 11 is dissolved and removed to make the circuit independent as shown in FIG. A highly chemically resistant solder resist 9 based on epoxy resin is formed on the entire surface except for the land portions 7 and through-hole portions 8 by an exposure method. At this time, the copper plating layer 4 in the previously formed through hole is
serves to block the ultraviolet light 14 in FIG. Leakage of the ultraviolet light 14 from the portions without the exposure mask 15 is blocked by the previously formed thin copper plating layer 4 and does not harden the solder resist adhered within the through holes 3. After completing the process as shown in FIG. 6, the exposed land portions 7 and through-hole portions 8 are again immersed in a chemical copper plating bath based on a sulfuric acid network and a complexing agent to coat the copper plating film 10 to a certain thickness. The film is deposited to a thickness of 15 to 30 μm, as shown in FIG.
本発明によれば、露光マスクのない部分からの紫外光の
漏れは、予め形成した薄い銅層によって遮断され、スル
ーホール内に付着したソルダーレジストを硬化させるこ
とはない。従って、良好なめっき層をランド部及びスル
ーホール部のみに形成することができる。このことによ
り、高密度なプリント回路板を効率良く製造することが
できるという効果がある。According to the present invention, leakage of ultraviolet light from areas without an exposure mask is blocked by the thin copper layer formed in advance, and the solder resist attached within the through-holes will not be hardened. Therefore, a good plating layer can be formed only on the land portions and through-hole portions. This has the effect that high-density printed circuit boards can be manufactured efficiently.
第１図から第７図までは本発明によるプリント回路板の
製造方法を示す断面図、第８図は、平均鋼めっき厚と銅
めっき厚バラツキの間の関係を示すダイヤグラム、第９
図は、孔径／板厚比と均一電着性の間の関係を示すダイ
ヤグラム、第１０図は、銅厚とエツチング後最小ライン
幅の間の関係を示すダイヤグラム、第１１図は、エツチ
ングレジストの位置ずれしたときの状態を示す図、第１
２図は、エツチング後に回路部分にめっきを行なったと
きの状態を示す図、第１３図は、光マスクのない部分か
らスルーホール内への紫外光の漏れの様子を示す図であ
る。
符号の説明
１・・・銅張り積層板の銅箔、
２・・・銅張り積層板の樹脂板、
３・・・スルーホール孔、
４・・・パネル化学銅めっき層、
５・・・ドライフィルム、 ６・・・独立ライン。
７・・・ランド部、 ８・・・スルーホール部
、９・・・ソルダーレジスト、１０・・・化学銅めっき
膜、１１・・アルカリ可溶型インク、
１２・・・エツチング液、１３・・・めっき層。
１４・・・紫外光、
１６・・・未硬化のソルダーレジスト、１７・・・露光
マスク。
第８１の 等ｑ０
茅１０″Ｉ］
を月／！（ツムターン
璃１１図（α）
１１１図（ｂ）1 to 7 are cross-sectional views showing the method of manufacturing a printed circuit board according to the present invention, FIG. 8 is a diagram showing the relationship between average steel plating thickness and copper plating thickness variation, and FIG.
Figure 10 is a diagram showing the relationship between the hole diameter/thickness ratio and uniform electrodepositivity, Figure 10 is a diagram showing the relationship between copper thickness and minimum line width after etching, and Figure 11 is a diagram showing the relationship between copper thickness and minimum line width after etching. Diagram showing the state when the position is shifted, 1st
FIG. 2 is a diagram showing the state when the circuit portion is plated after etching, and FIG. 13 is a diagram showing the leakage of ultraviolet light from the portion without the optical mask into the through hole. Explanation of symbols 1...Copper foil of copper-clad laminate, 2...Resin plate of copper-clad laminate, 3...Through hole, 4...Panel chemical copper plating layer, 5...Dry Film, 6...Independent line. 7... Land portion, 8... Through-hole portion, 9... Solder resist, 10... Chemical copper plating film, 11... Alkali-soluble ink, 12... Etching liquid, 13...・Plating layer. 14... Ultraviolet light, 16... Uncured solder resist, 17... Exposure mask. The 81st etc. q0 茅10″I] is the month/! (Zumturnri 11 figure (α) 111 figure (b)
Claims (1)
ホール部を除く領域に露光法によりめっきレジストを形
成し、該ランド部及び該スルーホール部を含む領域にめ
っきを形成する工程を有するプリント回路板の製造方法
において、前記めっきレジスト形成前に、該ランド部及
び該スルーホール部に前記めっきにより形成される銅層
よりも薄い銅層を形成することを特徴とするプリント回
路板の製造方法。1. Manufacture of a printed circuit board having a process of forming a plating resist by an exposure method on an area of a substrate having through-holes excluding the land part and the through-hole part, and forming plating in the area including the land part and the through-hole part. A method for manufacturing a printed circuit board, characterized in that, before forming the plating resist, a copper layer thinner than the copper layer formed by the plating is formed on the land portion and the through hole portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32064888A JPH01302795A (en) | 1988-12-21 | 1988-12-21 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32064888A JPH01302795A (en) | 1988-12-21 | 1988-12-21 | Manufacture of printed circuit board |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8484682A Division JPS58202589A (en) | 1982-05-21 | 1982-05-21 | Method of producing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01302795A true JPH01302795A (en) | 1989-12-06 |
| JPH05876B2 JPH05876B2 (en) | 1993-01-06 |
Family
ID=18123758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32064888A Granted JPH01302795A (en) | 1988-12-21 | 1988-12-21 | Manufacture of printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01302795A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS554956A (en) * | 1978-06-28 | 1980-01-14 | Oki Electric Ind Co Ltd | Method of manufacturing printed circuit board |
| JPS5518072A (en) * | 1978-07-26 | 1980-02-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device |
| JPS5752196A (en) * | 1980-09-16 | 1982-03-27 | Hitachi Ltd | Method of producing printed board |
| JPS58202589A (en) * | 1982-05-21 | 1983-11-25 | 株式会社日立製作所 | Method of producing printed circuit board |
-
1988
- 1988-12-21 JP JP32064888A patent/JPH01302795A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS554956A (en) * | 1978-06-28 | 1980-01-14 | Oki Electric Ind Co Ltd | Method of manufacturing printed circuit board |
| JPS5518072A (en) * | 1978-07-26 | 1980-02-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device |
| JPS5752196A (en) * | 1980-09-16 | 1982-03-27 | Hitachi Ltd | Method of producing printed board |
| JPS58202589A (en) * | 1982-05-21 | 1983-11-25 | 株式会社日立製作所 | Method of producing printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05876B2 (en) | 1993-01-06 |
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