JP3189399B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3189399B2 JP3189399B2 JP19303692A JP19303692A JP3189399B2 JP 3189399 B2 JP3189399 B2 JP 3189399B2 JP 19303692 A JP19303692 A JP 19303692A JP 19303692 A JP19303692 A JP 19303692A JP 3189399 B2 JP3189399 B2 JP 3189399B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- refractory metal
- metal nitride
- gate electrode
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本願の発明は、ゲート電極を有す
る半導体装置の製造方法に関するものである。The present invention relates to a relates to a method for manufacturing a semiconductor equipment having a gate electrode.
【０００２】[0002]
【従来の技術】半導体装置におけるゲート電極の材料と
しては、Ｗ、Ｍｏ、Ｔｉ等の高融点金属のシリサイド膜
を多結晶Ｓｉ膜上に積層させた高融点金属ポリサイド
や、不純物をドーピングした多結晶Ｓｉが、一般的に用
いられている。しかし、集積度が高くなってゲート電極
の線幅が細くなると、このゲート電極の電気抵抗が高く
なるので、半導体装置の高速動作のために、電気抵抗が
より低いゲート電極の材料が要求されている。2. Description of the Related Art As a material of a gate electrode in a semiconductor device, a refractory metal polycide in which a silicide film of a refractory metal such as W, Mo, Ti or the like is laminated on a polycrystalline Si film, or a polycrystalline material doped with impurities is used. Si is generally used. However, as the degree of integration increases and the line width of the gate electrode becomes narrower, the electrical resistance of the gate electrode becomes higher. For high-speed operation of the semiconductor device, a material for the gate electrode having a lower electrical resistance is required. I have.
【０００３】そこで、図２に示す様に、ゲート電極１１
をＷ膜１２で形成した第１従来例や、図３に示す様に、
不純物をドーピングした多結晶Ｓｉ膜１３とＴｉＮ膜１
４とＷ膜１５とを順次に積層させた三層膜でゲート電極
１１を形成した第２従来例等が提案されている。[0003] Therefore, as shown in FIG.
As shown in FIG. 3 or a first conventional example in which
Polycrystalline Si film 13 doped with impurities and TiN film 1
A second prior art example in which the gate electrode 11 is formed of a three-layer film in which the gate electrode 4 and the W film 15 are sequentially stacked has been proposed.
【０００４】[0004]
【発明が解決しようとする課題】ところが、図２に示し
た第１従来例では、Ｗ膜１２とゲート酸化膜であるＳｉ
Ｏ2 膜１６との密着性が悪く、Ｗ膜１２の耐酸化性も低
く、ＳｉＯ2 膜１６の膜質も劣化する。また、図３に示
した第２従来例では、Ｗ膜１５が層間絶縁膜１７と接し
ているので、今度はゲート電極１１と層間絶縁膜１７と
の密着性が悪く、ゲート電極１１が熱的に不安定で、熱
処理を受けると層間絶縁膜１７がゲート電極１１から剥
離し易い。従って、図２、３に示した第１及び第２従来
例の何れにおいても、信頼性が低かった。However, in the first prior art shown in FIG. 2, the W film 12 and the gate oxide film Si
The adhesion to the O 2 film 16 is poor, the oxidation resistance of the W film 12 is low, and the quality of the SiO 2 film 16 is also deteriorated. Further, in the second conventional example shown in FIG. 3, since the W film 15 is in contact with the interlayer insulating film 17, the adhesion between the gate electrode 11 and the interlayer insulating film 17 is poor, and the gate electrode 11 is thermally And the interlayer insulating film 17 is easily peeled off from the gate electrode 11 when subjected to a heat treatment. Therefore, the reliability was low in each of the first and second conventional examples shown in FIGS.
【０００５】[0005]
【課題を解決するための手段】本願の発明による半導体
装置の製造方法は、半導体膜２３と第１の高融点金属窒
化膜２４と高融点金属膜２５と第２の高融点金属窒化膜
２６と被覆膜２７とを順次に堆積させる工程と、前記被
覆膜２７と前記第２の高融点金属窒化膜２６と前記高融
点金属膜２５とをゲート電極１１のパターンに加工する
工程と、この加工の後に第３の高融点金属窒化膜３２を
全面に堆積させる工程と、前記第３及び第１の高融点金
属窒化膜３２、２４と前記被覆膜２７とのエッチング特
性が互いに異なる条件で前記第３及び第１の高融点金属
窒化膜３２、２４を異方性エッチングして、前記第３の
高融点金属窒化膜３２を前記パターンの側面にのみ残す
と共に前記第１の高融点金属窒化膜２４を前記高融点金
属膜２５の下面にのみ残す工程と、前記異方性エッチン
グの後に前記パターンをマスクにして前記半導体膜２３
をパターニングする工程とを有している。A method of manufacturing a semiconductor device according to the present invention comprises a semiconductor film 23, a first refractory metal nitride film 24, a refractory metal film 25, and a second refractory metal nitride film 26. A step of sequentially depositing a coating film 27, a step of processing the coating film 27, the second refractory metal nitride film 26, and the refractory metal film 25 into a pattern of the gate electrode 11, After the processing, a step of depositing a third refractory metal nitride film 32 on the entire surface, and under the condition that the etching characteristics of the third and first refractory metal nitride films 32 and 24 and the coating film 27 are different from each other. The third and first refractory metal nitride films 32 and 24 are anisotropically etched to leave the third refractory metal nitride film 32 only on the side surfaces of the pattern and to form the first refractory metal nitride film 32. The film 24 is placed on the lower surface of the refractory metal film 25. A step of leaving viewed, the pattern as a mask after said anisotropic etching the semiconductor film 23
Patterning step.
【０００６】[0006]
【作用】本願の発明による方法で製造された半導体装置
では、ゲート電極１１のうちで下層側の半導体膜２３が
ゲート絶縁膜１６と接しているのでゲート電極１１とゲ
ート絶縁膜１６との界面が安定であり、しかもゲート電
極１１のうちの上層側が高融点金属膜２５であるのでゲ
ート電極１１の電気抵抗が低いにも拘らず、高融点金属
膜２５の全面を高融点金属窒化膜２４、２６、３２が被
覆しているで、ゲート電極１１が熱的に安定で層間絶縁
膜１７、３４がゲート電極１１から剥離しにくい。In the semiconductor device manufactured by the method according to the invention of the present application , since the lower semiconductor film 23 of the gate electrode 11 is in contact with the gate insulating film 16, the interface between the gate electrode 11 and the gate insulating film 16 is reduced. Since the refractory metal film 25 is on the upper layer side of the gate electrode 11, the entire surface of the refractory metal film 25 is formed of the refractory metal nitride films 24 and 26 despite the low electrical resistance of the gate electrode 11. , 32 are covered, the gate electrode 11 is thermally stable, and the interlayer insulating films 17, 34 are not easily peeled off from the gate electrode 11.
【０００７】そして、本願の発明による半導体装置の製
造方法では、第１の高融点金属窒化膜２４で高融点金属
膜２５の下面を被覆し、第２の高融点金属窒化膜２６で
高融点金属膜２５の上面を被覆し、第３の高融点金属窒
化膜３２で高融点金属膜２５の両側面を被覆することが
できる。しかも、第３の高融点金属窒化膜３２を異方性
エッチングする際に、第２の高融点金属窒化膜２６の上
面を被覆膜２７で被覆しているので、第２の高融点金属
窒化膜２６も同時に除去されるのを防止している。In the method of manufacturing a semiconductor device according to the present invention , the lower surface of the refractory metal film 25 is covered with the first refractory metal nitride film 24 and the refractory metal nitride film 26 is covered with the second refractory metal nitride film 26. The upper surface of the film 25 can be covered, and both side surfaces of the refractory metal film 25 can be covered with the third refractory metal nitride film 32. Moreover, when the third refractory metal nitride film 32 is anisotropically etched, since the upper surface of the second refractory metal nitride film 26 is covered with the coating film 27, the second refractory metal nitride film 32 is covered. The film 26 is also prevented from being removed at the same time.
【０００８】[0008]
【実施例】以下、本願の発明の一実施例を、図１を参照
しながら説明する。なお、図２、３に示した第１及び第
２従来例と同一の構成部分には、同一の符号を付してあ
る。An embodiment of the present invention will be described below with reference to FIG. The same components as those of the first and second conventional examples shown in FIGS. 2 and 3 are denoted by the same reference numerals.
【０００９】本実施例では、図１（ａ）に示す様に、Ｐ
型のＳｉ基板２１の素子分離領域の表面に、ＬＯＣＯＳ
法等で厚いＳｉＯ2 膜２２をまず形成する。そして、素
子活性領域の表面にゲート酸化膜としてのＳｉＯ2 膜１
６を形成し、続けて、膜厚が数十〜数百ｎｍの多結晶Ｓ
ｉ膜２３を減圧ＣＶＤ法で堆積させる。堆積後の多結晶
Ｓｉ膜２３には不純物をドーピングするが、その一つの
方法として、ＰＯＣｌ3 雰囲気中で高温熱処理を施すこ
とによって、Ｐｈｏｓを１０19ｃｍ-3以上の濃度にドー
ピングする方法がある。In this embodiment, as shown in FIG.
LOCOS on the surface of the element isolation region of the Si substrate 21
First, a thick SiO 2 film 22 is formed by a method or the like. Then, an SiO 2 film 1 as a gate oxide film is formed on the surface of the element active region.
6 and then a polycrystalline S having a film thickness of several tens to several hundreds nm.
An i film 23 is deposited by a low pressure CVD method. The polycrystalline Si film 23 after the deposition is doped with impurities. As one of the methods, there is a method of doping Phos to a concentration of 10 19 cm −3 or more by performing a high-temperature heat treatment in a POCl 3 atmosphere. .
【００１０】また、後述する様に多結晶Ｓｉ膜２３上に
ＴｉＮ膜２４を堆積させた後、このＴｉＮ膜２４を通し
て、ＢまたはＰｈｏｓをやはり１０19ｃｍ-3以上の濃度
になる様にイオン注入法でドーピングしてもよい。更に
また、多結晶Ｓｉ膜２３を堆積させた後、多結晶Ｓｉ膜
２３の表面に薄いＳｉＯ2 膜（図示せず）を形成し、こ
のＳｉＯ2 膜を通して不純物をイオン注入し、熱処理を
施した後に、ＳｉＯ2膜を除去してもよい。After a TiN film 24 is deposited on the polycrystalline Si film 23 as described later, B or Phos is ion-implanted through the TiN film 24 so as to have a concentration of 10 19 cm -3 or more. It may be doped by a method. Furthermore, after depositing the polycrystalline Si film 23, a thin SiO 2 film (not shown) is formed on the surface of the polycrystalline Si film 23, impurities are ion-implanted through the SiO 2 film, and heat treatment is performed. Later, the SiO 2 film may be removed.
【００１１】多結晶Ｓｉ膜２３に不純物をドーピングし
た後、膜厚が数〜数十ｎｍのＴｉＮ膜２４をスパッタ法
かまたはＣＶＤ法で多結晶Ｓｉ膜２３上に堆積させる。
その後、膜厚が数十〜数百ｎｍのＷ膜２５をスパッタ法
かまたはＣＶＤ法でＴｉＮ膜２４上に堆積させ、更に膜
厚が数〜数十ｎｍのＴｉＮ膜２６をＴｉＮ膜２４と同様
の方法でＷ膜２５上に堆積させる。なお、Ｗ膜２５の代
わりに、Ｔｉ膜やＭｏ膜等を用いてもよい。After doping the polycrystalline Si film 23 with impurities, a TiN film 24 having a thickness of several to several tens nm is deposited on the polycrystalline Si film 23 by a sputtering method or a CVD method.
Thereafter, a W film 25 having a thickness of several tens to several hundreds nm is deposited on the TiN film 24 by a sputtering method or a CVD method, and a TiN film 26 having a thickness of several to several tens nm is formed in the same manner as the TiN film 24. Is deposited on the W film 25 by the method described above. Note that, instead of the W film 25, a Ti film, a Mo film, or the like may be used.
【００１２】そして、膜厚が数十〜数百ｎｍのＳｉＯ2
膜２７をＣＶＤ法でＴｉＮ膜２６上に堆積させた後、レ
ジスト３１をリソグラフィ法でゲート電極１１のパター
ンに加工する。次に、このレジスト３１をマスクにし
て、図１（ｂ）に示す様に、ＳｉＯ2 膜２７とＴｉＮ膜
２６とＷ膜２５とを連続的に異方性エッチングし、レジ
スト３１を除去した後、膜厚が数〜数十ｎｍのＴｉＮ膜
３２をスパッタ法かまたはＣＶＤ法で再び全面に堆積さ
せる。なお、ＴｉＮ膜２６、３２の代わりに、二層膜で
あるＴｉＮ／Ｔｉ膜を用いてもよい。Then, SiO 2 having a film thickness of several tens to several hundreds of nm
After depositing the film 27 on the TiN film 26 by the CVD method, the resist 31 is processed into a pattern of the gate electrode 11 by the lithography method. Next, using the resist 31 as a mask, as shown in FIG. 1B, the SiO 2 film 27, the TiN film 26, and the W film 25 are continuously anisotropically etched to remove the resist 31. Then, a TiN film 32 having a film thickness of several to several tens nm is deposited again on the entire surface by a sputtering method or a CVD method. Instead of the TiN films 26 and 32, a two-layer TiN / Ti film may be used.
【００１３】次に、ＴｉＮ膜３２の全面を異方性エッチ
ングして、図１（ｃ）に示す様に、Ｗ膜２５の側面にの
みＴｉＮ膜３２を側壁状に残す。そして、ＳｉＯ2 膜２
７をマスクにして、ＴｉＮ膜２４と多結晶Ｓｉ膜２３と
を連続的に異方性エッチングして、全面をＴｉＮ膜２
４、２６、３２に被覆されたＷ膜２５と多結晶Ｓｉ膜２
３とが組み合わされたゲート電極１１を完成させる。Next, the entire surface of the TiN film 32 is anisotropically etched to leave the TiN film 32 only on the side surface of the W film 25 in a side wall shape as shown in FIG. And the SiO 2 film 2
7 is used as a mask, the TiN film 24 and the polycrystalline Si film 23 are continuously anisotropically etched to form the entire surface of the TiN film 2.
W film 25 and polycrystalline Si film 2 coated on 4, 26 and 32
3 is completed.
【００１４】その後、ゲート電極１１とＳｉＯ2 膜２２
とをマスクにして、ＰｈｏｓまたはＡｓをＳｉ基板２１
にイオン注入して、濃度が１０17〜１０18ｃｍ-3である
Ｎ-型の拡散層３３を形成する。そして、ＳｉＯ2 膜ま
たは多結晶Ｓｉ膜で、ゲート電極１１の側面にＬＤＤス
ペーサ３４を形成する。更に、ゲート電極１１とＬＤＤ
スペーサ３４とＳｉＯ2 膜２２とをマスクにして、Ｐｈ
ｏｓまたはＡｓをＳｉ基板２１にイオン注入して、濃度
が１０19〜１０22ｃｍ-3であるＮ+ 型の拡散層３５を形
成する。Thereafter, the gate electrode 11 and the SiO 2 film 22
Is used as a mask, and Phos or As is
Then, an N − -type diffusion layer 33 having a concentration of 10 17 to 10 18 cm −3 is formed. Then, an LDD spacer 34 is formed on the side surface of the gate electrode 11 using a SiO 2 film or a polycrystalline Si film. Further, the gate electrode 11 and the LDD
Using the spacer 34 and the SiO 2 film 22 as a mask, Ph
Os or As is ion-implanted into the Si substrate 21 to form an N + type diffusion layer 35 having a concentration of 10 19 to 10 22 cm −3 .
【００１５】その後、不純物を含まないＳｉＯ2 膜、Ｐ
ＳＧ膜、ＢＰＳＧ膜、ＳｉＮ膜またはこれらを組み合わ
せた膜で層間絶縁膜１７を形成し、一方の拡散層３５に
達するコンタクト孔３６を層間絶縁膜１７等に開孔す
る。そして、多結晶Ｓｉ膜、Ｗ膜、Ｔｉ膜、ＴｉＮ膜ま
たはこれらを組み合わせた膜でコンタクト孔３６を埋め
込んで、プラグ３７を形成する。更に、Ｔｉ膜、ＴｉＮ
膜、ＡｌＳｉ膜、ＡｌＳｉＣｕ膜等の複合膜でＡｌ配線
４１を形成し、表面保護膜４２を堆積させて、ＬＤＤ構
造のＭＯＳトランジスタ４３を完成させる。Thereafter, an SiO 2 film containing no impurities, P
The interlayer insulating film 17 is formed of an SG film, a BPSG film, a SiN film or a combination thereof, and a contact hole 36 reaching one of the diffusion layers 35 is formed in the interlayer insulating film 17 or the like. Then, the plug 37 is formed by filling the contact hole 36 with a polycrystalline Si film, a W film, a Ti film, a TiN film, or a combination thereof. Furthermore, Ti film, TiN
An Al wiring 41 is formed of a composite film such as a film, an AlSi film, and an AlSiCu film, and a surface protection film 42 is deposited to complete a MOS transistor 43 having an LDD structure.
【００１６】以上の様にして製造したＭＯＳトランジス
タ４３では、層間絶縁膜１７及びＬＤＤスペーサ３４と
Ｗ膜２５との間にＴｉＮ膜２６、３２またはＴｉＮ／Ｔ
ｉ膜が介在しているので、ゲート電極１１が熱的に安定
で、層間絶縁膜１７及びＬＤＤスペーサ３４がゲート電
極１１から剥離しにくい。In the MOS transistor 43 manufactured as described above, the TiN films 26 and 32 or the TiN / T
Since the i film is interposed, the gate electrode 11 is thermally stable, and the interlayer insulating film 17 and the LDD spacer 34 are not easily separated from the gate electrode 11.
【００１７】[0017]
【発明の効果】本願の発明による半導体装置の製造方法
では、高融点金属膜の全面を高融点金属窒化膜で被覆す
ることができ、しかも第３の高融点金属窒化膜を異方性
エッチングする際に第２の高融点金属窒化膜も同時に除
去されるのを防止している。このため、ゲート電極とゲ
ート絶縁膜との界面が安定であり、しかもゲート電極の
電気抵抗が低いにも拘らず、ゲート電極が熱的に安定で
層間絶縁膜がゲート電極から剥離しにくいので、性能及
び信頼性の何れもが優れている半導体装置を安定的に製
造することができる。According to the method of manufacturing a semiconductor device according to the present invention, the entire surface of the refractory metal film can be covered with the refractory metal nitride film, and the third refractory metal nitride film is anisotropically etched. At this time, the second refractory metal nitride film is also prevented from being removed at the same time . Therefore, the gate electrode and gate
The interface with the gate insulating film is stable and the gate electrode
Despite the low electrical resistance, the gate electrode is thermally stable
Since the interlayer insulating film is difficult to peel off from the gate electrode,
A semiconductor device having both excellent reliability and reliability can be manufactured stably.
【図１】本願の発明の一実施例を工程順に示す側断面図
である。FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.
【図２】本願の発明の第１従来例の側断面図である。FIG. 2 is a side sectional view of a first conventional example of the present invention.
【図３】本願の発明の第２従来例の側断面図である。FIG. 3 is a side sectional view of a second conventional example of the present invention.
１１ ゲート電極 ２３ 多結晶Ｓｉ膜 ２４ ＴｉＮ膜 ２５ Ｗ膜 ２６ ＴｉＮ膜 ２７ ＳｉＯ2 膜 ３２ ＴｉＮ膜Reference Signs List 11 gate electrode 23 polycrystalline Si film 24 TiN film 25 W film 26 TiN film 27 SiO 2 film 32 TiN film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/28 301 H01L 29/43 H01L 21/336 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/78 H01L 21/28 301 H01L 29/43 H01L 21/336
Claims (1)
融点金属膜と第２の高融点金属窒化膜と被覆膜とを順次
に堆積させる工程と、 前記被覆膜と前記第２の高融点金属窒化膜と前記高融点
金属膜とをゲート電極のパターンに加工する工程と、 この加工の後に第３の高融点金属窒化膜を全面に堆積さ
せる工程と、 前記第３及び第１の高融点金属窒化膜と前記被覆膜との
エッチング特性が互いに異なる条件で前記第３及び第１
の高融点金属窒化膜を異方性エッチングして、前記第３
の高融点金属窒化膜を前記パターンの側面にのみ残すと
共に前記第１の高融点金属窒化膜を前記高融点金属膜の
下面にのみ残す工程と、 前記異方性エッチングの後に前記パターンをマスクにし
て前記半導体膜をパターニングする工程とを有する半導
体装置の製造方法。A step of sequentially depositing a semiconductor film, a first refractory metal nitride film, a refractory metal film, a second refractory metal nitride film, and a coating film; Processing the high-melting point metal nitride film and the high-melting point metal film into a gate electrode pattern; depositing a third high-melting point metal nitride film over the entire surface after the processing; 3 and 1 under conditions that the etching characteristics of the refractory metal nitride film and the coating film are different from each other.
Anisotropically etching the refractory metal nitride film of
Leaving the refractory metal nitride film only on the side surfaces of the pattern and leaving the first refractory metal nitride film only on the lower surface of the refractory metal film, using the pattern as a mask after the anisotropic etching. Patterning the semiconductor film by using the above method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19303692A JP3189399B2 (en) | 1992-06-26 | 1992-06-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19303692A JP3189399B2 (en) | 1992-06-26 | 1992-06-26 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0613605A JPH0613605A (en) | 1994-01-21 |
| JP3189399B2 true JP3189399B2 (en) | 2001-07-16 |
Family
ID=16301102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19303692A Expired - Fee Related JP3189399B2 (en) | 1992-06-26 | 1992-06-26 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3189399B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW444257B (en) | 1999-04-12 | 2001-07-01 | Semiconductor Energy Lab | Semiconductor device and method for fabricating the same |
-
1992
- 1992-06-26 JP JP19303692A patent/JP3189399B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0613605A (en) | 1994-01-21 |
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