JPH01293620A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01293620A JPH01293620A JP63126566A JP12656688A JPH01293620A JP H01293620 A JPH01293620 A JP H01293620A JP 63126566 A JP63126566 A JP 63126566A JP 12656688 A JP12656688 A JP 12656688A JP H01293620 A JPH01293620 A JP H01293620A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist film
- mask
- photomask
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 abstract 2
- 238000007781 pre-processing Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特にホトレジ
スト膜を用いたドライエツチングを含んだ半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including dry etching using a photoresist film.
半導体装置の配線を行う為のコンタクトホールを形成す
る際、配線材料の断線を予防するのに、コンタクトホー
ルの形状を口部が拡がったテーパー状にする方法が用い
られている。2. Description of the Related Art When forming a contact hole for wiring a semiconductor device, a method of forming the contact hole into a tapered shape with a widened opening is used to prevent disconnection of the wiring material.
第２図（ａ）〜（ｄ）は従来の半導体装置の製造方法の
一例を説明するための製造工程順に示した半導体チップ
の断面図である。第２図（ａ）に示すように、シリコン
基板１上に成長されたシリコン酸化膜２上にホトレジス
ト膜３を塗布し、プリベークを行う０次に第２図（ｂ）
に示すように、ホトマスク５ａを用いて所定のパターン
を露光する。次に第２図（ｃ）に示すように、ホトレジ
スト膜３を現像した後、ポストベークを行い、ホトレジ
スト膜３をたらす０次に第２図（ｄ）に示すように、ホ
トレジスト膜３とシリコン酸化膜２のエツチング速度が
ほぼ同じになるような条件下で、反応性イオンエツチン
グ法により酸化膜２をエツチングすることにより半導体
装置を製造していた。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps to explain an example of a conventional method for manufacturing a semiconductor device. As shown in FIG. 2(a), a photoresist film 3 is coated on the silicon oxide film 2 grown on the silicon substrate 1, and pre-baking is performed as shown in FIG. 2(b).
As shown in FIG. 2, a predetermined pattern is exposed using a photomask 5a. Next, as shown in FIG. 2(c), after developing the photoresist film 3, post-baking is performed to form a photoresist film 3. Next, as shown in FIG. 2(d), the photoresist film 3 and the silicon A semiconductor device has been manufactured by etching the oxide film 2 using a reactive ion etching method under conditions such that the etching rate of the oxide film 2 is approximately the same.
上述した従来のエツチング方法では、ポストベークを行
い、ホトレジスト膜３をたらすと、その形状がカマボッ
形になってしまい、このホトレジスト膜を用いてエツチ
ングしてもコンタクトホールの形状が充分なテーパー形
状にならず、配線の断線を防止する充分な効果が得られ
ないという欠点があった。In the conventional etching method described above, when post-baking is performed and the photoresist film 3 is deposited, the shape of the contact hole becomes a cylindrical shape, and even if this photoresist film is used for etching, the shape of the contact hole cannot be sufficiently tapered. However, there was a drawback that a sufficient effect of preventing wire breakage could not be obtained.
本発明の目的は、充分なテーパー状のコンタクトホール
を形成し、配線の断線を防止できる半導体装置の製造方
法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a sufficiently tapered contact hole and prevent disconnection of wiring.
本発明の半導体装置の製造方法は、半導体基板上の被エ
ツチング膜上にホトレジスト膜を塗布する工程と、第１
のマスクを用いて前記ホトレジスト膜の膜厚の途中まで
露光する工程と、光透過部分面積が前記第１のマスクよ
り小さなパターンを持った第２のマスクを用いて前記工
程により露光した領域のほぼ中心にマスクの位置合わせ
をして前記ホトレジスト膜の露光部分が前記被エツチン
グ膜に達するまで露光する工程と、前記露光された前記
ホトレジスト膜を現像後ポストベークを行う工程と、前
記ポストベークされた前記ホトレジスト膜をマスクとし
て前記被エツチング膜をドライエツチングする工程とを
含んで構成される。The method for manufacturing a semiconductor device of the present invention includes the steps of applying a photoresist film on a film to be etched on a semiconductor substrate;
A step of exposing the photoresist film to the middle of the film thickness using a mask, and a step of exposing almost the area exposed by the step using a second mask having a pattern whose light transmitting area is smaller than that of the first mask. a step of aligning a mask to the center and exposing the exposed portion of the photoresist film until it reaches the film to be etched; a step of post-baking the exposed photoresist film after development; The method includes the step of dry etching the film to be etched using the photoresist film as a mask.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの製造工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in order of manufacturing steps to explain one embodiment of the present invention.
第１図（ａ）に示すように、シリコン基板１上に成長さ
れたシリコン酸化膜２上にホトレジスト膜３を塗布し、
プリベークを行う。As shown in FIG. 1(a), a photoresist film 3 is coated on a silicon oxide film 2 grown on a silicon substrate 1,
Perform pre-bake.
次に第１図（ｂ）に示すように、ホトマスク５ａを用い
て所定のパターンをホトレジスト膜４の膜厚の途中まで
感光するように光を調整して露光する０次に第１図（ｃ
）に示すように、光透過部分面積がホトマスク５ａより
小さなパターンを持ったホトマスク５ｂを用いて、前工
程により露光した領域のほぼ中心にマスクの位置合わせ
をして、ホトレジスト膜３の露光部分がシリコン酸化膜
２に達するまで露光するを完全に露光する０次に第１図
（ｄ）に示すように、ホトレジスト膜３を現像した後、
ポストベークを行い、ホトレジスト膜３をたらす０本発
明において、ホトレジスト膜３は段差を持ち、従来のよ
うにカマボッ形にはならない０次に第１図（ｅ）に示す
ように、ホトレジスト膜３とシリコン酸化膜２のエツチ
ング速度がほぼ同じになるような条件下で、反応性イオ
ンエツチング法により酸化膜２をエツチングすることに
より、充分なテーパー状のコンタクトホールを形成する
ことができる。Next, as shown in FIG. 1(b), a predetermined pattern is exposed using a photomask 5a by adjusting the light so as to expose the photoresist film 4 to the middle of its thickness.
), using a photomask 5b having a pattern with a light transmitting area smaller than that of the photomask 5a, the mask is positioned approximately at the center of the area exposed in the previous step, so that the exposed portion of the photoresist film 3 is Completely expose until the silicon oxide film 2 is reached. After developing the photoresist film 3, as shown in FIG.
Post-baking is performed to form a photoresist film 3. In the present invention, the photoresist film 3 has a step and does not have a hollow shape unlike the conventional method.As shown in FIG. 1(e), the photoresist film 3 and By etching the oxide film 2 by reactive ion etching under conditions such that the etching rate of the silicon oxide film 2 is approximately the same, a sufficiently tapered contact hole can be formed.
以上説明したように、本発明は、第１のマスクを用いて
ホトレジスト膜の途中まで露光し、光透過部分面積が第
１のマスクより小さなパターンを持った第２のマスクを
用いてホトレジスト膜を完全に露光することにより、ホ
トレジスト膜は段差を持ち、これをマスクとして被エツ
チング膜をドライエツチングすることにより、充分なテ
ーパー状のコンタクトホールを形成することができるの
で、配線をする際、断線を防止する効果がある。As explained above, in the present invention, a first mask is used to expose the photoresist film halfway, and a second mask having a pattern with a smaller light-transmitting area than the first mask is used to expose the photoresist film. By completely exposing the photoresist film, the photoresist film has a step, and by using this as a mask and dry etching the film to be etched, it is possible to form a sufficiently tapered contact hole, so there is no disconnection when wiring. It has the effect of preventing
第１図（ａ）〜（ｅ）は本発明の一実施例を説明するた
めの製造工程順に示した半導体チップの断面図、第２図
（ａ）〜（ｄ）は従来の半導体装置の製造方法の一例を
説明するための製造工程順に示した半導体チップの断面
図である。
１・・・シリコン基板、２・・・シリコン酸化膜、３・
・・ホトレジスト膜、４・・・ホトレジスト感光部、５
ａ、５ｂ・・・ホトマスク、６・・・露光光。FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in order of manufacturing steps to explain one embodiment of the present invention, and FIGS. 2(a) to (d) are conventional manufacturing steps of a semiconductor device. FIG. 3 is a cross-sectional view of a semiconductor chip shown in the order of manufacturing steps for explaining an example of the method. 1... Silicon substrate, 2... Silicon oxide film, 3.
...Photoresist film, 4...Photoresist photosensitive area, 5
a, 5b...photomask, 6...exposure light.
Claims (1)
塗布する工程と、第１のマスクを用いて前記ホトレジス
ト膜の膜厚の途中まで露光する工程と、光透過部分面積
が前記第１のマスクより小さなパターンを持った第２の
マスクを用いて前記工程により露光した領域のほぼ中心
にマスクの位置合わせをして前記ホトレジスト膜の露光
部分が前記被エッチング膜に達するまで露光する工程と
、前記露光された前記ホトレジスト膜を現像後ポストベ
ークを行う工程と、前記ポストベークされた前記ホトレ
ジスト膜をマスクとして前記被エッチング膜をドライエ
ッチングする工程とを含むことを特徴とする半導体装置
の製造方法。a step of applying a photoresist film on a film to be etched on a semiconductor substrate; a step of exposing the photoresist film to the middle of its thickness using a first mask; aligning the mask to approximately the center of the area exposed in the step using a second mask having a pattern and exposing until the exposed portion of the photoresist film reaches the film to be etched; A method for manufacturing a semiconductor device, comprising the steps of post-baking the photoresist film after development, and dry etching the film to be etched using the post-baked photoresist film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63126566A JPH01293620A (en) | 1988-05-23 | 1988-05-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63126566A JPH01293620A (en) | 1988-05-23 | 1988-05-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01293620A true JPH01293620A (en) | 1989-11-27 |
Family
ID=14938333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63126566A Pending JPH01293620A (en) | 1988-05-23 | 1988-05-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01293620A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007059926A (en) * | 2006-09-27 | 2007-03-08 | Nec Kagoshima Ltd | Pattern-forming method and thin-film transistor manufacturing method |
| JP2007514201A (en) * | 2003-12-12 | 2007-05-31 | ヒューレット−パッカード デベロップメント カンパニー エル．ピー． | Method for forming a depression in the surface of a photoresist layer |
-
1988
- 1988-05-23 JP JP63126566A patent/JPH01293620A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007514201A (en) * | 2003-12-12 | 2007-05-31 | ヒューレット−パッカード デベロップメント カンパニー エル．ピー． | Method for forming a depression in the surface of a photoresist layer |
| JP2007059926A (en) * | 2006-09-27 | 2007-03-08 | Nec Kagoshima Ltd | Pattern-forming method and thin-film transistor manufacturing method |
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