JPH01283813A - Epitaxial growth device - Google Patents
Epitaxial growth deviceInfo
- Publication number
- JPH01283813A JPH01283813A JP11314088A JP11314088A JPH01283813A JP H01283813 A JPH01283813 A JP H01283813A JP 11314088 A JP11314088 A JP 11314088A JP 11314088 A JP11314088 A JP 11314088A JP H01283813 A JPH01283813 A JP H01283813A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- susceptor
- silicon epitaxial
- substrate
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 150000001875 compounds Chemical class 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 2
- 230000006698 induction Effects 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、単結晶シリコン層を成長させるエピタキシャ
ル成長装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an epitaxial growth apparatus for growing single crystal silicon layers.
従来の技術
シリコンエピタキシャル成長技術は、とくに埋込みコレ
クタ層を有するブレーナ型バイポーラデバイスでは必要
不可欠なものとなっている。BACKGROUND OF THE INVENTION Silicon epitaxial growth techniques have become indispensable, especially in Brehner-type bipolar devices with buried collector layers.
ところが、シリコンエピタキシャル成長時に発生するす
べり転位は、前記シリコンエピタキシャル成長層上に形
成される半導体装置の特性を著しく劣化させ、ひいては
半導体装置の歩留りを低下させる。However, slip dislocations generated during silicon epitaxial growth significantly deteriorate the characteristics of a semiconductor device formed on the silicon epitaxial growth layer, and further reduce the yield of the semiconductor device.
また、シリコンエピタキシャル成長層の比抵抗、および
成長層厚みのばらつきも半導体装置の特性、歩留りへの
影響が大きい。Furthermore, variations in the specific resistance of the silicon epitaxially grown layer and the thickness of the grown layer have a large influence on the characteristics and yield of the semiconductor device.
以下に高周波誘導加熱を用いたシリコンエピタキシャル
成長装置の従来の基板保持体（以下、サセプタと記す）
について説明する。Below is a conventional substrate holder (hereinafter referred to as a susceptor) for a silicon epitaxial growth apparatus using high-frequency induction heating.
I will explain about it.
第２図（ａ）は、半導体基板１と従来のサセプタ２との
加熱前の様子を示し、第２図（ｂ）は、半導体基板１と
従来のサセプタ２との加熱中の様子を示した各断面図で
ある。FIG. 2(a) shows the state of the semiconductor substrate 1 and the conventional susceptor 2 before heating, and FIG. 2(b) shows the state of the semiconductor substrate 1 and the conventional susceptor 2 during heating. FIG. 3 is a cross-sectional view.
第２図（ａ） 、 （ｂ）において、３は石英絶縁板、
４は高周波誘導コイルである。In FIGS. 2(a) and (b), 3 is a quartz insulating plate;
4 is a high frequency induction coil.
高周波誘導加熱では、サセプタ２に流れる誘導電流でサ
セプタ２自体が加熱され、次にサセプタ２と接触してい
る半導体基板１の底面が加熱される。ところが、半導体
基板１の表面は反応ガスが流れているため、湿度が低く
なってしまう。In high-frequency induction heating, the susceptor 2 itself is heated by an induced current flowing through the susceptor 2, and then the bottom surface of the semiconductor substrate 1 that is in contact with the susceptor 2 is heated. However, since the reactive gas is flowing on the surface of the semiconductor substrate 1, the humidity becomes low.
従って、半導体基板１の表面と裏面とで温度差を生じ、
半導体基板１に反りが発生する。Therefore, a temperature difference occurs between the front and back surfaces of the semiconductor substrate 1,
Warpage occurs in the semiconductor substrate 1.
半導体基板１の周辺部は、前記反りによりサセプタ２か
ら離れ、さらに表面に流れる反応ガスにより過冷却され
、半導体基板面内にも温度差が生じ、反りは、ますます
増長される。The peripheral portion of the semiconductor substrate 1 is separated from the susceptor 2 due to the warpage, and is further supercooled by the reaction gas flowing to the surface, causing a temperature difference within the surface of the semiconductor substrate, and the warpage further increases.
この時の各部の温度関係を式で表わすと、Ｔ１ζＴ２ζ
Ｔ３＞Ｔ４＞’ｒｓとなる。ただし、Ｔ１はサセプタ２
の内部の温度、Ｔ２はサセプタ２表面の温度、Ｔ３は半
導体基板１あ裏面の温度、Ｔ４は半導体基板１の表面の
温度、Ｔ ５は半導体基板１の周辺部の温度である。Expressing the temperature relationship of each part at this time using an equation, T1ζT2ζ
T3>T4>'rs. However, T1 is susceptor 2
T2 is the temperature of the surface of the susceptor 2, T3 is the temperature of the back surface of the semiconductor substrate 1, T4 is the temperature of the surface of the semiconductor substrate 1, and T5 is the temperature of the peripheral portion of the semiconductor substrate 1.
従って、反りが発生するということは、半導体基板１に
応力が加わっており、前記応力により半導体基板１にす
べり転位が発生する。Therefore, the occurrence of warpage means that stress is applied to the semiconductor substrate 1, and the stress causes slip dislocations to occur in the semiconductor substrate 1.
また、このように反ったシリコン基板上にエピタキシャ
ル成長により単結晶シリコン層が形成された場合、一連
のエピタキシャル成長過程が終了し、半導体基板１の冷
却の際、反った半導体基板１がもとにもどろうとするた
め、同半導体基板上にエピタキシャル成長した単結晶シ
リコン層に応力が加わり、その結果シリコンエピタキシ
ャル層にすべり転位が発生する。In addition, when a single crystal silicon layer is formed by epitaxial growth on a silicon substrate that is warped in this way, the series of epitaxial growth processes is completed, and when the semiconductor substrate 1 is cooled, the warped semiconductor substrate 1 may return to its original state. Therefore, stress is applied to the single crystal silicon layer epitaxially grown on the semiconductor substrate, and as a result, slip dislocations occur in the silicon epitaxial layer.
また、シリコンエピタキシャル成長層の比抵抗、厚みは
、基板温度の高低に太き（左右される。したがって、前
出のすべり転位発生過程途中のように、基板面内に温度
差（温度のばらつき）があると、シリコンエピタキシャ
ル層の比抵抗、厚みに半導体基板１の面内ばらつきが生
じる。In addition, the resistivity and thickness of the silicon epitaxial growth layer vary depending on the substrate temperature. Therefore, as in the middle of the slip dislocation generation process mentioned above, there is a temperature difference (temperature variation) within the substrate surface. If so, variations in the specific resistance and thickness of the silicon epitaxial layer occur within the plane of the semiconductor substrate 1.
発明が解決しようとする課題
本発明は、前途のようなすべり転位の発生や、シリコン
エピタキシャル層の比抵抗および厚みのばらつき増大を
抑制できるエピタキシャル成長装置を提供することを目
的とする。Problems to be Solved by the Invention It is an object of the present invention to provide an epitaxial growth apparatus that can suppress the occurrence of slip dislocations and increase in variations in resistivity and thickness of a silicon epitaxial layer.
課題を解決するための手段
この目的を達成するために本発明は、サセプタの主表面
に、底面が球面と平面の合成形状を成した半導体基板と
同等以上の大きさの凹形ポケットをそなえた構成である
。Means for Solving the Problems In order to achieve this object, the present invention provides a concave pocket on the main surface of the susceptor, the bottom surface of which has a composite shape of a spherical surface and a flat surface, and whose size is equal to or larger than that of a semiconductor substrate. It is the composition.
作用
前記形状のポケットを有するサセプタを用いることによ
って、前途のようなすべり転位の発生や、シリコンエピ
タキシャル層の比抵抗及び厚みのばらつき増大を抑制で
きるものである。Effect: By using a susceptor having pockets having the shape described above, it is possible to suppress the occurrence of slip dislocations and increase in variations in resistivity and thickness of the silicon epitaxial layer.
実施例
本発明の一実施例について、図面を参照しながら説明す
る。Embodiment An embodiment of the present invention will be described with reference to the drawings.
第１図（ａ）は、半導体基板と本発明の一実施例におけ
るサセプタの加熱前の様子を示し、第１図（ｂ）は、半
導体基板と本発明の一実施例におけるサセプタの加熱中
の様子を示した断面である。FIG. 1(a) shows the semiconductor substrate and the susceptor in one embodiment of the present invention before heating, and FIG. 1(b) shows the semiconductor substrate and the susceptor in one embodiment of the present invention during heating. This is a cross section showing the situation.
第１図（ａ） 、 （ｂ）において、１は半導体基板、
２はサセプタ、３は石英絶縁板、４は高周波誘導コイル
である。In FIGS. 1(a) and 1(b), 1 is a semiconductor substrate;
2 is a susceptor, 3 is a quartz insulating plate, and 4 is a high frequency induction coil.
このようなサセプタ２を用いた場合の半導体基板１の加
熱過程は、前途のサセプタ２にポケットが無い場合と同
じ（、半導体基板ｌの表面と裏面との温度差により、半
導体基板１に反りが発生する。The heating process of the semiconductor substrate 1 when using such a susceptor 2 is the same as when the susceptor 2 does not have a pocket (the semiconductor substrate 1 may be warped due to the temperature difference between the front and back surfaces of the semiconductor substrate l). Occur.
しかし、サセプタ２に施したポケットは、半導体基板１
が反った状態で、半導体基板１の周辺部と中心部とが接
触する様になっている。However, the pocket made in the susceptor 2 is
In the warped state, the peripheral portion and center portion of the semiconductor substrate 1 come into contact with each other.
従って半導体基板１の面内の温度は均一になり、同基板
面内の温度差による反りは緩和される。Therefore, the temperature within the plane of the semiconductor substrate 1 becomes uniform, and warpage due to temperature differences within the plane of the substrate is alleviated.
この時の各部の温度関係を式で表わすとＴ Ｉ’ｉＴ２
ζＴ３＞Ｔ４ζＴ５となる。但し、Ｔ１〜Ｔ５は前途と
同じである。The temperature relationship of each part at this time can be expressed by the formula T I'iT2
ζT3>T4ζT5. However, T1 to T5 are the same as before.
このような作用により、半導体基板１に発生する反り、
つまり半導体基板１に加わる応力は、ポケットの無いサ
セプタを用いた場合より小さくなり、半導体基板１のす
べり転位の発生は抑制され、また、シリコンエピタキシ
ャル層成長後の半導体冷却過程では、加熱過程で生じた
反りが小さいため、シリコンエピタキシャル層のすべり
転位の発生は、ポケットの無いサセプタ２を用いた場合
より抑制できる。Due to such an action, warpage that occurs in the semiconductor substrate 1,
In other words, the stress applied to the semiconductor substrate 1 is smaller than when a susceptor without pockets is used, and the occurrence of slip dislocations in the semiconductor substrate 1 is suppressed. Since the warpage is small, the occurrence of slip dislocations in the silicon epitaxial layer can be suppressed more than when a susceptor 2 without pockets is used.
また、前記作用により半導体基板１の面内に生じる温度
差は小さくなるため、シリコンエピタキシャル層の比抵
抗および厚みのばらつきも小さくなる。Moreover, since the temperature difference generated within the plane of the semiconductor substrate 1 is reduced by the above-mentioned action, variations in resistivity and thickness of the silicon epitaxial layer are also reduced.
発明の効果
以上のように本発明によれば、サセプタの主表面に、底
面が球面と平面の合成形状を成している半導体基板１と
同様以上の凹状ポケットを設けたことにより、半導体基
板の反りによるすべり転位、シリコンエピタキシャル層
の比抵抗および厚みのばらつきを抑制でき、半導体装置
の歩留り向上を実現できる。Effects of the Invention As described above, according to the present invention, by providing a concave pocket on the main surface of the susceptor with a concave pocket similar to or larger than that of the semiconductor substrate 1 whose bottom surface has a composite shape of a spherical surface and a flat surface, the semiconductor substrate can be improved. It is possible to suppress slip dislocations caused by warpage and variations in the resistivity and thickness of the silicon epitaxial layer, thereby improving the yield of semiconductor devices.
第１図（ａ） 、 （ｂ）は本発明の一実施例における
サセプタと半導体基板との加熱前および加熱中の様子を
示す各断面図、第２図（ａ） 、 （ｂ）は従来のサセ
プタと半導体基板との加熱前および加熱中の様子を示す
各断面図である。
１・・・・・・半導体基板、２・・・・・・サセプタ、
３・・・・・・石英絶縁膜、４・・・・・・高周波誘導
コイル。
代理人の氏名 弁理士 中尾敏男 ほか１名第１図FIGS. 1(a) and (b) are cross-sectional views showing the state of a susceptor and a semiconductor substrate before and during heating in an embodiment of the present invention, and FIGS. 2(a) and (b) are sectional views of a conventional susceptor and a semiconductor substrate. FIG. 3 is a cross-sectional view showing the susceptor and the semiconductor substrate before and during heating; 1... Semiconductor substrate, 2... Susceptor,
3...Quartz insulation film, 4...High frequency induction coil. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1
Claims (1)
保持体を加熱する加熱部とを備え、前記基板保持体の主
表面に、前記半導体基板の直径と同等以上の大きさの凹
状ポケットを設け、前記凹状ポケットの底面形状が、球
面と平面の合成形状で成ることを特徴とするエピタキシ
ャル成長装置。The method includes a flat substrate holder that holds a semiconductor substrate, and a heating section that heats the substrate holder, and a concave pocket having a size equal to or larger than the diameter of the semiconductor substrate is provided on the main surface of the substrate holder. . An epitaxial growth apparatus, wherein the bottom surface shape of the concave pocket is a composite shape of a spherical surface and a flat surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11314088A JPH01283813A (en) | 1988-05-10 | 1988-05-10 | Epitaxial growth device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11314088A JPH01283813A (en) | 1988-05-10 | 1988-05-10 | Epitaxial growth device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01283813A true JPH01283813A (en) | 1989-11-15 |
Family
ID=14604579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11314088A Pending JPH01283813A (en) | 1988-05-10 | 1988-05-10 | Epitaxial growth device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01283813A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6740367B2 (en) | 1999-03-18 | 2004-05-25 | Asm Japan K.K. | Plasma CVD film-forming device |
| US6761771B2 (en) * | 2000-10-19 | 2004-07-13 | Asm Japan K.K. | Semiconductor substrate-supporting apparatus |
| JP4772918B1 (en) * | 2010-12-21 | 2011-09-14 | エー・イー・テック株式会社 | Method and apparatus for manufacturing gallium nitride (GaN) free-standing substrate |
| JP2012131692A (en) * | 2011-04-28 | 2012-07-12 | Aetech Corp | METHOD AND APPARATUS FOR MANUFACTURING GALLIUM NITRIDE (GaN) SELF-SUPPORTING SUBSTRATE |
-
1988
- 1988-05-10 JP JP11314088A patent/JPH01283813A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6740367B2 (en) | 1999-03-18 | 2004-05-25 | Asm Japan K.K. | Plasma CVD film-forming device |
| US6761771B2 (en) * | 2000-10-19 | 2004-07-13 | Asm Japan K.K. | Semiconductor substrate-supporting apparatus |
| JP4772918B1 (en) * | 2010-12-21 | 2011-09-14 | エー・イー・テック株式会社 | Method and apparatus for manufacturing gallium nitride (GaN) free-standing substrate |
| WO2012086212A1 (en) * | 2010-12-21 | 2012-06-28 | エー・イー・テック株式会社 | METHOD AND DEVICE FOR MANUFACTURING SELF-SUPPORTING GALLIUM NITRIDE (GaN) SUBSTRATE |
| JP2012131662A (en) * | 2010-12-21 | 2012-07-12 | Aetech Corp | METHOD AND APPARATUS FOR MANUFACTURING GALLIUM NITRIDE (GaN) SELF-SUPPORTING SUBSTRATE |
| JP2012131692A (en) * | 2011-04-28 | 2012-07-12 | Aetech Corp | METHOD AND APPARATUS FOR MANUFACTURING GALLIUM NITRIDE (GaN) SELF-SUPPORTING SUBSTRATE |
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