JPH01276655A - Transfer mold type integrated circuit - Google Patents
Transfer mold type integrated circuitInfo
- Publication number
- JPH01276655A JPH01276655A JP63105254A JP10525488A JPH01276655A JP H01276655 A JPH01276655 A JP H01276655A JP 63105254 A JP63105254 A JP 63105254A JP 10525488 A JP10525488 A JP 10525488A JP H01276655 A JPH01276655 A JP H01276655A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- integrated circuit
- parts
- electronic components
- transfer mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000465 moulding Methods 0.000 abstract description 5
- 230000005856 abnormality Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本発明は、電子部品とリードフレームが合成樹脂で一体
的にモールドされたトランスファーモールド型集積回路
の構造に関するものである。The present invention relates to the structure of a transfer mold integrated circuit in which electronic components and a lead frame are integrally molded with synthetic resin.
第４図に従来のトランスファーモールド型集積回路の内
部構造を示す。この集積回路は、複数の電子部品２をリ
ードフレームｌに接合し、成形体３でモールドして一体
的に形成したものである。
リードフレームｌは回路パターンである。これは例えば
鉄ニツケル合金の薄板をエツチングまたは型を用いて切
断して成形される。電子部品２は、例えばＩＣやトラン
ジスタ、ダイオード等のペアチップ半導体４．チップコ
ンデンサやチップ抵抗等のチップ型部品５およびコイル
や水晶１辰動子等の端子付部品６である。成形体３には
エポキシ系の合成樹脂が使用されている。
この集積回路を製造するには、電子部品２とリードフレ
ームｌをボンディングワイヤ、溶接、はんだ付、導電接
着剤等で接合した後、型を使用して成形体３を成形する
。最後に成形体３外部のリードフレーム１を加工して完
成する。第５図はトランスファーモールド型集積回路の
外観側面図である。FIG. 4 shows the internal structure of a conventional transfer mold integrated circuit. This integrated circuit is integrally formed by bonding a plurality of electronic components 2 to a lead frame 1 and molding them with a molded body 3. The lead frame l is a circuit pattern. This is formed, for example, by etching or cutting a thin plate of iron-nickel alloy using a die. The electronic component 2 is, for example, a paired chip semiconductor 4 such as an IC, a transistor, or a diode. These are chip-type parts 5 such as chip capacitors and chip resistors, and parts 6 with terminals such as coils and crystal 1-drive elements. The molded body 3 is made of epoxy-based synthetic resin. To manufacture this integrated circuit, the electronic component 2 and the lead frame 1 are joined together using bonding wire, welding, soldering, conductive adhesive, etc., and then a molded body 3 is formed using a mold. Finally, the lead frame 1 outside the molded body 3 is processed and completed. FIG. 5 is an external side view of the transfer molded integrated circuit.
このトランスファーモールド型集積回路の各構成要素は
夫々熱膨張率が異っている５そのため、動作時の温度変
化によって各構成要素間に相対的な寸法差が生じ、電子
部品２に応力が加わって破損したり、電気的特性が変化
するという問題があった。電子部品２の中でも本体が直
接リードフレーム１に接続しているチップ型部品５は応
力による影響を受は易い。
本発明は前記の課題を解決するためなされたもので、熱
膨張に伴う破損や特性異常が生じない高信頼性のトラン
スファーモールド型集積回路を提供することを目的とす
る。Each component of this transfer molded integrated circuit has a different coefficient of thermal expansion5. Therefore, relative dimensional differences occur between each component due to temperature changes during operation, and stress is applied to the electronic component 2. There were problems with damage and changes in electrical characteristics. Among the electronic components 2, the chip type component 5 whose main body is directly connected to the lead frame 1 is easily affected by stress. The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a highly reliable transfer molded integrated circuit that does not suffer from damage or characteristic abnormalities due to thermal expansion.
前記の目的を達成するための本発明のトランスファーモ
ールド型集積回路を、実施例に対応する第１図を用いて
詳細に説明する。
同図に示すように本発明のトランスファーモールド型集
積回路は、リードフレームｌの成形体３内にある部分が
電子部品２と接続する近傍で他の部分より狭い断面を有
する部分７になっている。A transfer mold type integrated circuit of the present invention for achieving the above object will be explained in detail using FIG. 1 corresponding to an embodiment. As shown in the figure, in the transfer molded integrated circuit of the present invention, a portion of the lead frame l inside the molded body 3 is a portion 7 that has a narrower cross section than other portions near where it connects to the electronic component 2. .
この集積回路は、温度変化によって各構成要素間に相対
的な寸法差が生じてもリードフレームｌの狭幅部７によ
って応力が緩和され、電子部品２に歪が伝わらない。In this integrated circuit, even if a relative dimensional difference occurs between each component due to a temperature change, stress is relaxed by the narrow portion 7 of the lead frame 1, and no strain is transmitted to the electronic component 2.
以下、本発明を適用するトランスファーモールド型集積
回路の実施例を詳細に説明する。
第１図は本発明を適用するトランスファーモールド型集
積回路の一実施例の内部構成平面図である。
この集積回路は、リードフレーム１とそれに接合された
複数の電子部品２とを成形体３で一体的にモールドした
ものである。電子部品２としては、ペアチップ半導体４
、チップ型部品５、端子付部品６が用いられている。リ
ードフレーム１に電子部品２が接合した接合部８近傍は
両縁が切り欠かれ、他の部分より幅が狭い狭幅部７が形
成されている。同図の構成中、リードフレームｌの材質
、電子部品２、成形体３、集積回路の製法および外観は
、第４図および第５図に示した従来のトランスファーモ
ールド型集積回路と同一で既に説明しであるため、それ
らの説明は省略する。
この集積回路は内部温度が変化すると、電子部品２等の
各構成要素が夫々不均一に膨張または収縮する。各構成
要素間に相対的な寸法差が生じた場合でも、それらの寸
法差はリードフレーム１の狭幅部７が歪むことによって
吸収、緩和される。
よって、電子部品２が応力を受けて破損したり特性が変
化することはない。
第２図および第３図にトランスファーモールド型集積回
路の別な実施例を示す。
第２図に示す集積回路は、第１図に示した実施例の狭幅
部７をクランク形にしたものである。狭幅部７は電子部
品２の幅方向に延びた狭幅部７ａと、長平方向に延びた
狭幅部７ｂとで構成される。この狭幅部７は、第１図の
実施例に比べて全長が長くなることに加え、電子部品２
の幅方向と平行に延びた狭幅部７ａを有することによっ
て、より大きな応力緩和効果を得られる。
第３図に示す集積回路は、狭幅部７をコの字形に折り曲
げてリードフレームｌの平面から浮かせ、立体的に成形
したものである。狭幅部７はリードフレーム１の平面か
ら立ち上がる狭幅部７ｃと、電子部品２の長手方向に延
びた狭幅部７ｄとで構成される。この集積回路も同様に
大きな応力緩和効果を得ることが出来る。
なお本発明の集積回路は、リードフレーム１が狭幅部７
を有していれば、これらの実施例で示した他にも種々の
形状で実施することが可能である。Embodiments of a transfer mold integrated circuit to which the present invention is applied will be described in detail below. FIG. 1 is a plan view of the internal configuration of an embodiment of a transfer mold type integrated circuit to which the present invention is applied. This integrated circuit is made by integrally molding a lead frame 1 and a plurality of electronic components 2 bonded thereto with a molded body 3. As the electronic component 2, a pair chip semiconductor 4 is used.
, a chip-type component 5, and a component with a terminal 6 are used. In the vicinity of the joint 8 where the electronic component 2 is joined to the lead frame 1, both edges are cut out to form a narrow part 7 that is narrower than the other parts. In the configuration shown in the figure, the material of the lead frame 1, the electronic component 2, the molded body 3, and the manufacturing method and appearance of the integrated circuit are the same as those of the conventional transfer mold integrated circuit shown in FIGS. 4 and 5, and have already been described. Therefore, their explanation will be omitted. When the internal temperature of this integrated circuit changes, each component, such as the electronic component 2, expands or contracts non-uniformly. Even when relative dimensional differences occur between the respective components, these dimensional differences are absorbed and alleviated by distortion of the narrow width portion 7 of the lead frame 1. Therefore, the electronic component 2 will not be damaged or its characteristics will change due to stress. FIGS. 2 and 3 show another embodiment of a transfer molded integrated circuit. In the integrated circuit shown in FIG. 2, the narrow portion 7 of the embodiment shown in FIG. 1 is shaped like a crank. The narrow portion 7 includes a narrow portion 7a extending in the width direction of the electronic component 2 and a narrow portion 7b extending in the longitudinal direction. This narrow portion 7 has a longer overall length than the embodiment shown in FIG.
By having the narrow portion 7a extending parallel to the width direction of the tube, a greater stress relaxation effect can be obtained. The integrated circuit shown in FIG. 3 is three-dimensionally formed by bending the narrow portion 7 into a U-shape and lifting it off the plane of the lead frame l. The narrow portion 7 is composed of a narrow portion 7 c rising from the plane of the lead frame 1 and a narrow portion 7 d extending in the longitudinal direction of the electronic component 2 . This integrated circuit can also obtain a large stress relaxation effect. Note that in the integrated circuit of the present invention, the lead frame 1 has a narrow portion 7.
If it has, it can be implemented in various shapes other than those shown in these embodiments.
以上詳細に説明したように、本発明のトランスファーモ
ールド型集積回路は温度変化によって各構成要素に相対
的な寸法差が生じても、電子部品に応力が加わることが
ない、そのため温度変化による破損や特性異常が発生せ
ず、高信頼性を確保することが出来る。As explained in detail above, the transfer molded integrated circuit of the present invention does not apply stress to electronic components even if relative dimensional differences occur in each component due to temperature changes. Characteristic abnormalities do not occur and high reliability can be ensured.
第１図は本発明を適用するトランスファーモールド型集
積回路の一実施例を示す内部構成平面図、第２図、第３
図は別な実施例のリードフレ−ムの狭幅部を示す部分拡
大斜視図、第４図は従来のトランスファーモールド型集
積回路の内部構成平面図、第５図はその外観側面図であ
る。
１・・・リードフレーム ２−・・電子部品３・・・成
形体 ４・・・ベアチップ半導体５・・・チッ
プ型部品 ６・・・端子付部品７・７ａ・７ｂ・７Ｃ
・７ｄ・・・狭幅部８・・・接合部
第３図FIG. 1 is a plan view of the internal configuration of an embodiment of a transfer molded integrated circuit to which the present invention is applied, FIGS.
The figure is a partially enlarged perspective view showing a narrow portion of a lead frame of another embodiment, FIG. 4 is a plan view of the internal structure of a conventional transfer mold type integrated circuit, and FIG. 5 is a side view of its appearance. 1...Lead frame 2-...Electronic component 3...Molded body 4...Bare chip semiconductor 5...Chip type component 6...Component with terminal 7, 7a, 7b, 7C
・7d...Narrow width part 8...Joint part Fig. 3
Claims (1)
して一体的にモールドされ、成形体外にリードフレーム
が延長しているトランスファーモールド型集積回路にお
いて、前記リードフレームの成形体内にある部分が電子
部品と接続する近傍で他の部分より狭い断面を有する部
分になっていることを特徴とするトランスファーモール
ド型集積回路。1. In a transfer mold integrated circuit in which a lead frame is connected to at least one electronic component and integrally molded, and the lead frame extends outside the molded body, a portion of the lead frame inside the molded body is connected to the electronic component. 1. A transfer mold integrated circuit characterized by a portion having a narrower cross section than other portions near the connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63105254A JPH01276655A (en) | 1988-04-27 | 1988-04-27 | Transfer mold type integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63105254A JPH01276655A (en) | 1988-04-27 | 1988-04-27 | Transfer mold type integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01276655A true JPH01276655A (en) | 1989-11-07 |
Family
ID=14402517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63105254A Pending JPH01276655A (en) | 1988-04-27 | 1988-04-27 | Transfer mold type integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01276655A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208017B1 (en) | 1994-10-07 | 2001-03-27 | Nec Corporation | Semiconductor device with lead-on-chip structure |
| JP2014093353A (en) * | 2012-11-01 | 2014-05-19 | Denso Corp | Semiconductor device and semiconductor device manufacturing method |
| DE102015215786A1 (en) | 2014-10-16 | 2016-04-21 | Mitsubishi Electric Corporation | Semiconductor device |
| EP2894952A4 (en) * | 2012-09-07 | 2017-01-25 | Mitsubishi Electric Corporation | Power semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4985961A (en) * | 1972-12-22 | 1974-08-17 | ||
| JPS5124864B1 (en) * | 1970-06-29 | 1976-07-27 |
-
1988
- 1988-04-27 JP JP63105254A patent/JPH01276655A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5124864B1 (en) * | 1970-06-29 | 1976-07-27 | ||
| JPS4985961A (en) * | 1972-12-22 | 1974-08-17 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208017B1 (en) | 1994-10-07 | 2001-03-27 | Nec Corporation | Semiconductor device with lead-on-chip structure |
| EP2894952A4 (en) * | 2012-09-07 | 2017-01-25 | Mitsubishi Electric Corporation | Power semiconductor device |
| US9620444B2 (en) | 2012-09-07 | 2017-04-11 | Mitsubishi Electric Corporation | Power semiconductor device |
| JP2014093353A (en) * | 2012-11-01 | 2014-05-19 | Denso Corp | Semiconductor device and semiconductor device manufacturing method |
| DE102015215786A1 (en) | 2014-10-16 | 2016-04-21 | Mitsubishi Electric Corporation | Semiconductor device |
| US9917064B2 (en) | 2014-10-16 | 2018-03-13 | Mitsubishi Electric Corporation | Semiconductor device with a plate-shaped lead terminal |
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