JPH01264233A - Electrode structure of hybrid integrated circuit - Google Patents
Electrode structure of hybrid integrated circuitInfo
- Publication number
- JPH01264233A JPH01264233A JP9131188A JP9131188A JPH01264233A JP H01264233 A JPH01264233 A JP H01264233A JP 9131188 A JP9131188 A JP 9131188A JP 9131188 A JP9131188 A JP 9131188A JP H01264233 A JPH01264233 A JP H01264233A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- glass substrate
- solder connection
- solder
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 48
- 239000011521 glass Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 6
- 239000011651 chromium Substances 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052802 copper Inorganic materials 0.000 claims abstract description 5
- 239000010949 copper Substances 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000006185 dispersion Substances 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 238000004299 exfoliation Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 229910001120 nichrome Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
Landscapes
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ガラス基板上に回路部品を半田接続により実
装するのに好適な混成集積回路の電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode structure of a hybrid integrated circuit suitable for mounting circuit components on a glass substrate by solder connection.
混成集積回路、特にガラス基板上に半導体ＩＣやＦＰＣ
（可撓性プリント配線板）等の回路部品を半田接続によ
り実装するものにおいては、研究実用化報告第１８巻第
１号（１９６９年）、第１８゛３頁〜第２０３頁に論じ
られているように１半田接続部の構成法により信頼性が
大きく左右される。この論文には、ガラス基板上に形成
する半田接続用薄膜を２重膜構成として、半田への溶は
込みＫよる薄膜の消失現象を防止した研究成果が報遺さ
れている。Hybrid integrated circuits, especially semiconductor ICs and FPCs on glass substrates
(Flexible printed wiring boards) and other circuit components mounted by solder connection are discussed in Research and Practical Application Report Vol. As shown in Figure 1, reliability is greatly influenced by the method of configuring the solder joints. This paper reports the results of a study in which a thin film for solder connection formed on a glass substrate had a double-layer structure to prevent the thin film from disappearing due to penetration into the solder.
上記従来技術では、ガラス基板上に形成された配線層に
半田接続用電極層を介して半導体ＩＣやＦＰＣ等の回路
部品を実装する際の熱歪応力による配線層およびガラス
基板の破断については配慮されておらず、ガラス基板の
耐引張応力が大きくないため、半田付は時の被接続部品
とガラス基板との熱膨張差による熱歪応力が接続部に加
わると、配線層の断線や半田接続用電極層の周辺におけ
るガラス基板のクラック、剥離が生じる問題がありた。In the above conventional technology, consideration is given to the breakage of the wiring layer and glass substrate due to thermal strain stress when mounting circuit components such as semiconductor ICs and FPCs on the wiring layer formed on the glass substrate via the electrode layer for solder connection. Since the tensile stress resistance of the glass substrate is not high, when soldering is performed, thermal strain stress due to the difference in thermal expansion between the connected components and the glass substrate is applied to the connection part, causing disconnection of the wiring layer and solder connection. There was a problem that cracks and peeling of the glass substrate occurred around the electrode layer.
これらの従来技術における問題点を第２図を用いてさら
に詳しく説明する。The problems with these conventional techniques will be explained in more detail with reference to FIG.
第２図は、ファクシミリにおける密着形読取センナを最
も膜層構成を少なくして実現するための一例としてガラ
ス基板上に半導体ＩＣを半田ボールにより実装した場合
を示すもので、ガラス基板１上にクロム等の配線層２が
形成され、その上に例えば、第１層がニッケル鋼、第２
層が金よりなる２重膜構成の半田接続用電極層３が形成
されている。この電極層５の上に半導体ＩＣ（図示せず
）を置き、半田４により加熱接続すると、接続後の放置
あるいは温度サイクル試験において、クラックＣが発生
し、配線層２が断線したシ、ひどい場合は接続部がガラ
ス基板１から剥離することがある。このクラックＣは、
第２図（Ａ）の平面図に示すように、半田接続用電極層
３の周辺でガラス基板ＩＫ引張応力が加わる部分から発
生し、徐々に内部、全周へと進行する。したがって、そ
の応力は非常に狭い面積に集中して加わり、この応力が
ガラス基板の耐引張応力強度（通常２〜３ Ｋｆ／ｄ
”）を越えることＫより、クラックが発生するものと見
られる。この応力は、温度サイクル試験時でなくても、
回路部品実装時、半田の固相線温度（１８３℃）でのガ
ラス基板と回路部品との熱膨張差から生じる歪により発
生している。Fig. 2 shows a case where a semiconductor IC is mounted on a glass substrate using solder balls as an example of realizing a contact type reading sensor for facsimile with the smallest number of film layers. A wiring layer 2 such as
A solder connection electrode layer 3 having a double film structure made of gold is formed. When a semiconductor IC (not shown) is placed on this electrode layer 5 and heat-connected using the solder 4, cracks C occur when left after connection or during a temperature cycle test, and the wiring layer 2 is disconnected. In some cases, the connecting portion may peel off from the glass substrate 1. This crack C is
As shown in the plan view of FIG. 2(A), the stress is generated from the portion where the tensile stress of the glass substrate IK is applied around the electrode layer 3 for solder connection, and gradually progresses to the inside and the entire circumference. Therefore, the stress is concentrated in a very narrow area, and this stress increases the tensile stress resistance of the glass substrate (usually 2 to 3 Kf/d
”), cracks are expected to occur.This stress can be applied even if it is not during the temperature cycle test.
This is caused by distortion caused by the difference in thermal expansion between the glass substrate and the circuit component at the solidus temperature of the solder (183° C.) during circuit component mounting.
との熱歪応力によるクラックを防止する庭めＫは、第３
図に示すように種々の材料を用いた構成が考えられる。Niwame K, which prevents cracks due to thermal strain stress, is the third
As shown in the figure, configurations using various materials are possible.
第５図（Ａ）は、配線層２と半田接続用電極層３０周辺
部との間１ｃ ＳｉＯ□あるいは５ｉｓＮ４等のシリコ
ン化合物の層５を置き、これらの層で熱歪応力の大部分
を受けようとするものである。まな、第３図の）は、８
１０□等のシリコン化合物の層５の上に歪を吸収する低
ヤング率のポリイミド系樹脂（Ｐｉｑ）の層６をさらに
積層したものである。これらは、高い接続信頼性が得ら
れるものの、形成工程が繁雑となって製品コストを増加
させ、好ましくない。In FIG. 5(A), a layer 5 of a silicon compound such as 1c SiO□ or 5isN4 is placed between the wiring layer 2 and the periphery of the solder connection electrode layer 30, and these layers receive most of the thermal strain stress. This is what we are trying to do. Mana, in Figure 3) is 8
A layer 6 of a polyimide resin (Piq) having a low Young's modulus that absorbs strain is further laminated on a layer 5 of a silicon compound such as 10□. Although these can provide high connection reliability, the formation process is complicated and the product cost increases, which is not preferable.
本発明の目的は、より少ない工程で、ガラス基板と被接
続部品との熱膨張差による半田接続部の熱歪応力をでき
る限シ広い面積で受けるようｋすることにより、ガラス
基板に加わる単位面積当りの応力を低減して、配線層や
ガラス基板のクラックあるいは剥離を防止するととＫあ
る。An object of the present invention is to make the solder connection part receive thermal strain stress caused by the difference in thermal expansion between the glass substrate and the connected component over as wide an area as possible, with fewer steps, thereby reducing the unit area applied to the glass substrate. It is said that it reduces the stress caused by contact and prevents cracking or peeling of wiring layers and glass substrates.
上記目的は、ガラス基板上に形成された配線層と半田接
続用電極層との間に１熱歪に対する内部応力が比較的小
さく、かつ半田の付着しない金属層を電極層の半田接続
面より広く配置することＫより達成される。The above purpose is to have a relatively small internal stress for one thermal strain between the wiring layer formed on the glass substrate and the electrode layer for solder connection, and to spread the metal layer to which no solder adheres wider than the solder connection surface of the electrode layer. This is achieved by arranging K.
本発明による電極構造では、ガラス基板と被接続部品と
の熱膨張差により半田接続用電極層の周辺部に生じる応
力を、該電極層と配線層との間に配置した金属層の表面
で一旦受ける。その後、応力は前記金属層の膜平面およ
び膜厚方向に広が）ながら配線層とガラス基板に伝わる
ため、ガラス基板には熱歪応力が直接伝わらず、前記金
属１内での応力分散効果により、単位面積当りの応力値
が低下する。これによりて、ガラス基板への応力集中を
なくし、ガラス基板に伝わる応力値を耐引張応力強度以
下に押えることができ、クラックや剥離を防止できる。In the electrode structure according to the present invention, the stress generated in the periphery of the solder connection electrode layer due to the difference in thermal expansion between the glass substrate and the connected component is temporarily applied to the surface of the metal layer disposed between the electrode layer and the wiring layer. receive. Thereafter, the stress spreads in the film plane and film thickness direction of the metal layer) and is transmitted to the wiring layer and the glass substrate, so thermal strain stress is not directly transmitted to the glass substrate, but due to the stress dispersion effect within the metal 1. , the stress value per unit area decreases. This eliminates stress concentration on the glass substrate, suppresses the stress value transmitted to the glass substrate below the tensile stress strength, and prevents cracks and peeling.
以下、本発明の実施例を第１因により説明する。 Hereinafter, embodiments of the present invention will be explained based on the first factor.
第１図η）は平面図、第１図（Ｂ）はその断面図である
０本実施例では、ガラス基板１上にスパッタリングによ
ってクロム（膜厚α１μｍ）よりなる配線層２を形成し
、その上に応力分散用金属層７゜８と半田接続用電極層
３をスパッタリングにより順次積層した。この場合、金
属層７には銅（膜厚α５〜１．０μｍ）を用い、金属層
８にはクロム（膜厚α１μｍ）を用いた。半田接続用電
極層５は、第２因に示した従来例と同様、半田の拡散防
止のため第１層にニッケル鋼（膜厚［１７ａｍ ）を用
い、第２層に半田接続性の良い金（膜厚（Ｌ２μｍ）を
用いた２重膜構成とし、これら電極層３に半導体ＩＣ−
？ＦＰＣ等の回路部品（図示せず）を半田４により接続
した。半田４は、この場合、被接続部品側にあらかじめ
半田ボールとしてつけられているものを用いたが、半田
槽へのデイツプ等により基板側の電極面につけることも
可能である。Fig. 1 (η) is a plan view, and Fig. 1 (B) is a cross-sectional view. A metal layer 7.8 for stress dispersion and an electrode layer 3 for solder connection were successively laminated thereon by sputtering. In this case, copper (thickness α5 to 1.0 μm) was used for the metal layer 7, and chromium (thickness α1 μm) was used for the metal layer 8. The electrode layer 5 for solder connection uses nickel steel (thickness: 17 am) for the first layer to prevent solder diffusion, and gold with good solder connection for the second layer, as in the conventional example shown in the second factor. (A double film structure using a film thickness (L2 μm) is used, and these electrode layers 3 have a semiconductor IC-
? Circuit components such as FPC (not shown) were connected using solder 4. In this case, the solder 4 was previously applied as a solder ball to the connected component side, but it is also possible to apply it to the electrode surface of the board side by dipping it into a solder bath or the like.
応力分散用金属層７を形成する材料としては、熱歪に対
する内部応力が比較的小さい、延性に富むものが良く、
例えば銅あるいはアルミニウム等のような、導電材とし
て通常使われている加工性の良い廉価な材料でよい０本
実施例のように、金属層７に銅を用いる場合には、その
上に半田の流れを防止するためのクロム等の金属層８を
薄く積層する。また、金属層７は、形成時にその膜自体
に生じる内部応力が大きいと、その応力で端部がめくれ
るような恐れがあるので、成膜後の内部応力が小さい材
料を選定することが望ましい。The material for forming the stress dispersion metal layer 7 is preferably one that has relatively low internal stress against thermal strain and is highly ductile.
For example, if copper is used for the metal layer 7 as in this embodiment, solder may be applied on top of it. A thin metal layer 8 of chromium or the like is laminated to prevent flow. Further, if the metal layer 7 has a large internal stress generated in the film itself during formation, there is a risk that the stress may cause the end portion to turn over, so it is desirable to select a material with low internal stress after the film is formed.
実験によれば、金属層７，８は応力分散効果を得るため
に電極層３の半田接続面より少なくとも１０μｍ以上広
くすることが望ましく、本実施例では、金属層７，８の
電極層３周辺部からの広げ幅ｄを最小部で１５μｍとし
た。According to experiments, it is desirable that the metal layers 7 and 8 be at least 10 μm wider than the solder connection surface of the electrode layer 3 in order to obtain a stress dispersion effect. The widening width d from the part was set to 15 μm at the minimum part.
以上の構成によって、熱歪による応力を金属層７．８で
分散させ、配線層２やガラス基板１のクラック、剥離を
防止することができた。With the above configuration, stress due to thermal strain was dispersed in the metal layer 7.8, and cracking and peeling of the wiring layer 2 and the glass substrate 1 could be prevented.
本実施例は、応力分散用金属層７．８を銅／クロムとし
、半田接続用電極層３をニッケル銅／金の２重膜構成と
した例であるが、応力分散用金属層７．８をアルミニウ
ムの単一膜とし、半田接続用電極層３をニクロム／金の
２重膜構成とした場合も同様の効果が得られた。In this example, the stress dispersion metal layer 7.8 is made of copper/chromium, and the solder connection electrode layer 3 has a double film structure of nickel copper/gold. A similar effect was obtained when the electrode layer 3 for solder connection was made of a double film structure of nichrome/gold.
このように各層には種々の材料を使用することができる
が、材料の種類によって成膜・パターン形状を配慮する
必要がある０例えば、応力分散用金属層７にアルミニウ
ムを用い、半田接続用電極層５にニクロム／金を用いる
場合には、金属層８は不要であるが、金属層７に用いる
アルミニウムの酸化防止のため、半田接続用電極層３の
第１層ニクロム膜を、金属膜７および配線層２を覆うよ
うなパターン形状とし、さらに半田の付着範囲が第２層
の金の上だけに限定されるように、電極層３のその他の
部分には酸化あるいは腐食処理を施して半田の付着が悪
い紐取に変えるなどの配慮が必要である。In this way, various materials can be used for each layer, but it is necessary to consider the film formation and pattern shape depending on the type of material. When using nichrome/gold for the layer 5, the metal layer 8 is not necessary, but in order to prevent oxidation of the aluminum used for the metal layer 7, the first layer nichrome film of the electrode layer 3 for solder connection is replaced with the metal layer 7. The pattern shape is such that it covers the wiring layer 2, and the other parts of the electrode layer 3 are subjected to oxidation or corrosion treatment so that the solder can be applied only to the second layer of gold. Consideration needs to be taken, such as changing to a cord handle that does not adhere well.
以上述べた実施例は、層構成が複雑なように見えるが、
第１図の実施例においても、金属層７゜８の成膜は、複
数ターゲットを持つスパッタ装置を用いて複数層同時に
行うことができ、結果として金属層７．８の形成プロセ
スが１回追加されるだけである。Although the embodiment described above seems to have a complicated layer structure,
In the embodiment shown in FIG. 1 as well, the metal layer 7.8 can be formed simultaneously using a sputtering device with multiple targets, and as a result, one additional step is required to form the metal layer 7.8. It is only done.
本発明によれば、ガラス基板上の半田接続部に加わる熱
歪応力が、配線層と半田接続用電極層との間に配置した
金属層により分散されてガラス基板に伝わるため、配線
層の断線やガラス基板のクラック、剥離を発生すること
なく、廉価で信頼性の高い半田接続ができるという効果
がある。According to the present invention, the thermal distortion stress applied to the solder connection portion on the glass substrate is dispersed by the metal layer disposed between the wiring layer and the electrode layer for solder connection and transmitted to the glass substrate, so that the wiring layer is disconnected. This has the effect of enabling low-cost and highly reliable solder connections without causing cracks or peeling of glass substrates.
第１図は本発明の一実施例を示す図で、（Ａ）は平面図
、（Ｂ）はその断面図、第２図は従来技術による電極構
造のクラック発生状態を示す図で、（Ａ）は平面図、（
Ｂ）はその断面図、第３１／（Ａ） 、 （Ｂ）は従来
技術による電極構造の他の例を示す断面図である。
１・・・・・・ガラス基板
２・・・・・・配線層
３・・・・・・半田接続用電極層
７．８・・・・・・応力分散用金属層。
第 １（￥］
１−・・汀゛ラス蘂末更 ４．−千日ｚ、−ｂ
ａＪ ７．ｇ−・Ａ・カ桶境釦Ｉ３・−千囮釈吐
用用
第２図
第３図FIG. 1 is a diagram showing an embodiment of the present invention, (A) is a plan view, (B) is a cross-sectional view thereof, and FIG. ) is a plan view, (
B) is a cross-sectional view thereof, and No. 31 (A) and (B) are cross-sectional views showing other examples of electrode structures according to the prior art. 1... Glass substrate 2... Wiring layer 3... Electrode layer for solder connection 7. 8... Metal layer for stress dispersion. 1st (￥) 1-... 汀゛悛衂螻 4.-1000 days z, -b
aJ 7. g-・A・Ka-Oke boundary button I3・--For 1000 decoys Shaketsu Figure 2 Figure 3
Claims (1)
する混成集積回路において、前記配線層と半田接続用電
極層との間に、熱歪に対する内部応力が比較的小さく、
かつ半田の付着しない金属層を電極層の半田接続面より
広く配置したことを特徴とする混成集積回路の電極構造
。 ２、前記金属層を、第１層が銅、第２層がクロムよりな
る２重膜構成としたことを特徴とする請求項、記載の混
成集積回路の電極構造。 ３、前記金属層をアルミニウムの単一膜で構成したこと
を特徴とする請求項、記載の混成集積回路の電極構造。 ４、前記金属層を、電極層の半田接続面より少なくとも
１０μｍ以上広くしたことを特徴とする請求項１、２ま
たは３記載の混成集積回路の電極構造。[Claims] 1. In a hybrid integrated circuit having a wiring layer and a solder connection electrode layer on a glass substrate, internal stress due to thermal strain is relatively small between the wiring layer and the solder connection electrode layer. ,
An electrode structure for a hybrid integrated circuit, characterized in that the metal layer to which solder does not adhere is arranged wider than the solder connection surface of the electrode layer. 2. The electrode structure of a hybrid integrated circuit according to claim 1, wherein the metal layer has a double film structure in which the first layer is made of copper and the second layer is made of chromium. 3. The electrode structure of a hybrid integrated circuit according to claim 1, wherein the metal layer is composed of a single aluminum film. 4. The electrode structure of a hybrid integrated circuit according to claim 1, 2 or 3, wherein the metal layer is wider than the solder connection surface of the electrode layer by at least 10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9131188A JPH01264233A (en) | 1988-04-15 | 1988-04-15 | Electrode structure of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9131188A JPH01264233A (en) | 1988-04-15 | 1988-04-15 | Electrode structure of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01264233A true JPH01264233A (en) | 1989-10-20 |
Family
ID=14022924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9131188A Pending JPH01264233A (en) | 1988-04-15 | 1988-04-15 | Electrode structure of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01264233A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209793A (en) * | 1989-10-18 | 1991-09-12 | Nippondenso Co Ltd | Solder connecting structure for glass board |
| US6596621B1 (en) | 2002-05-17 | 2003-07-22 | International Business Machines Corporation | Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate |
| WO2013004515A1 (en) * | 2011-07-01 | 2013-01-10 | Tyco Electronics Amp Gmbh | Electrical contact coating |
-
1988
- 1988-04-15 JP JP9131188A patent/JPH01264233A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209793A (en) * | 1989-10-18 | 1991-09-12 | Nippondenso Co Ltd | Solder connecting structure for glass board |
| US6596621B1 (en) | 2002-05-17 | 2003-07-22 | International Business Machines Corporation | Method of forming a lead-free tin-silver-copper based solder alloy on an electronic substrate |
| WO2013004515A1 (en) * | 2011-07-01 | 2013-01-10 | Tyco Electronics Amp Gmbh | Electrical contact coating |
| CN103781940A (en) * | 2011-07-01 | 2014-05-07 | 泰科电子Amp有限责任公司 | Electrical contact coating |
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