JPS63274199A - Formation of multilayer interconnection - Google Patents
Formation of multilayer interconnectionInfo
- Publication number
- JPS63274199A JPS63274199A JP10898787A JP10898787A JPS63274199A JP S63274199 A JPS63274199 A JP S63274199A JP 10898787 A JP10898787 A JP 10898787A JP 10898787 A JP10898787 A JP 10898787A JP S63274199 A JPS63274199 A JP S63274199A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- multilayer
- polyimide
- multilayer interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 229920001721 polyimide Polymers 0.000 claims abstract description 34
- 239000009719 polyimide resin Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 6
- 238000010030 laminating Methods 0.000 claims abstract description 6
- 150000002739 metals Chemical class 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 13
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 4
- 239000010949 copper Substances 0.000 abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052802 copper Inorganic materials 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000000919 ceramic Substances 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 150000003949 imides Chemical class 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 27
- 239000010409 thin film Substances 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229920006015 heat resistant resin Polymers 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000007906 compression Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、配線用導体と絶縁性の耐熱性樹脂とにより基
板上にｍ成され、電子計算機のモジュール用などに応用
される多層配線の形成方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to multilayer wiring, which is formed on a substrate by a wiring conductor and an insulating heat-resistant resin, and is applied to computer modules. Regarding the forming method.
モジュール用の多層配線基板としては、金属とポリイミ
ドを用いた薄膜多層配線、及びセラミック多層配線が知
られている。ポリイミドを用いた薄膜多層配線では、第
一層目の配線を形成した後に、ポリイミドを塗布、キュ
アした後に第２層配線を形成するというように、下１ｆ
ｊから順に上層を形成していく、いわゆる逐次積層法で
ある。薄膜多層配線では、配線導体のパターンニングに
ホトリングラフ技術を用いるために、配線幅１０μｍツ
クフィルムを積層し、圧力をかけ加熱することにより一
括積層する０加熱中にセラミック及び配線導体は焼結し
、その際に界面での接着が起る。As multilayer wiring boards for modules, thin film multilayer wiring using metal and polyimide and ceramic multilayer wiring are known. In thin film multilayer wiring using polyimide, after forming the first layer wiring, polyimide is applied and cured, and then the second layer wiring is formed.
This is a so-called sequential lamination method in which upper layers are formed in order from j. In thin-film multilayer wiring, in order to use photolithography technology for patterning the wiring conductor, the wiring width 10 μm thick film is laminated, and the ceramic and wiring conductor are sintered during heating, which is laminated all at once by applying pressure and heating. At this time, adhesion occurs at the interface.
セラミックの焼結温度は１０００℃程度と高いために配
線導体としてはＷなどの高融点金属が用いられる。した
がって、パターニングにはホトリングラフ技術が使用で
きないために配線幅は１００μｍ程度が限界となる。Since the sintering temperature of ceramic is as high as about 1000° C., a high melting point metal such as W is used as the wiring conductor. Therefore, since photolithographic technology cannot be used for patterning, the wiring width is limited to about 100 μm.
モジュール基板用の多層配線では、配線幅の微細化と多
層化が求められている。In multilayer wiring for module boards, miniaturization of wiring width and multilayering are required.
薄膜多層配線では、ホトリングラフ技術を用いるために
微細化はできるが、多層化した場合にはパターン精度が
悪くなり微細化は難しくなる。また、逐次積層のため、
歩留りを良くすることが難しい〇
一方、セラミック多層基板では、微細配線の形成が難し
く、また、配線導体として抵抗の高いＷなどしか使用で
きないという欠点がある０本発明は、上記問題点を解決
することを基本的な目的として、配線幅が小さく、かつ
積層数の多い多層配線を容易かつ確実に行え、かつ作業
効率の良好な多層配線の形成方法を提供することにある
０
〔問題点を解決するための手段〕
本発明を概説すれば、本発明は多層配線の形成方法に関
する発明であって、配線用導体と絶縁性の耐熱性ポリイ
ミド樹脂からなる多層配線の形成方法において、配線形
成されたポリイミドフィルムを一括積層する工程、及び
積層体を加熱圧着する工程の各工程を包含することを特
徴とする。Thin-film multilayer interconnects can be miniaturized using photolithography technology, but when multilayered, pattern accuracy deteriorates and miniaturization becomes difficult. In addition, because of sequential lamination,
It is difficult to improve the yield.On the other hand, ceramic multilayer substrates have the disadvantage that it is difficult to form fine wiring, and only high-resistance W or the like can be used as the wiring conductor.The present invention solves the above problems. The basic objective is to provide a method for forming multilayer wiring with a small wiring width and a large number of laminated layers easily and reliably, and with good work efficiency. Means for Solving the Problem] To summarize the present invention, the present invention relates to a method for forming a multilayer wiring, and is an invention that relates to a method for forming a multilayer wiring, which includes a wiring conductor and an insulating heat-resistant polyimide resin. The method is characterized in that it includes the steps of laminating polyimide films together and heat-pressing the laminate.
セラミック多層基板では、配線の形成された、薄いセラ
ミックシートを積層して多層にしたが、本発明では、配
線の形成されたポリイミドフィルムを積層することで多
層配線を形成する０ポリイミドフイルム上に配線を形成
したのでは、上下の配線の導通がとれないために、配線
はポリイミド内に形成されており、積層した時に、上下
配線の導通がとれるようになっている。積層界面の接着
は、加熱して圧力を加えて行うが、焼結するわけではな
いので、セラミック基板のような高温高圧は不要である
。ポリイミドは、加熱前は粘性のある液体であるが、高
温に加熱するにつれてイミド化反応が進行し、耐熱性樹
脂となる０ベ一ク温度が２００℃程度のときは、ポリイ
ミドは固化しフィルムとなるがイミド化は、はとんど進
行していない。このような状態のフィルムを密着して４
００℃程度に加熱すると１０（ｌイミド化し、高分子化
が完結する０ポリイミドフイルムは密着しているため界
面を介してもイミド化が起り、ポリイミド同士の界面は
強固に接着する。一方、配線導体同士の接着は拡散接合
によって行う。配線導体表面に化学反応しやすい金属を
薄くコーティングしておけば、界面における反応が促進
されて強い接合が形成されるので、より好ましい。In ceramic multilayer boards, thin ceramic sheets with wiring formed thereon are laminated to form a multilayer. However, in the present invention, wiring is formed on a polyimide film that forms a multilayer wiring by laminating polyimide films on which wiring is formed. If the layers are formed, conduction between the upper and lower wires cannot be achieved, so the wires are formed in polyimide so that when stacked, the upper and lower wires can be electrically connected. Adhesion at the laminated interface is performed by heating and applying pressure, but since sintering is not performed, high temperature and high pressure like ceramic substrates are not required. Polyimide is a viscous liquid before heating, but as it is heated to a high temperature, the imidization reaction progresses, and when the zero bake temperature is about 200°C, which becomes a heat-resistant resin, the polyimide solidifies and becomes a film. However, imidization has hardly progressed. Hold the film in this condition closely and
When heated to about 00°C, 10(l) imidizes and completes polymerization.Since polyimide films are in close contact, imidization occurs even through the interface, and the interface between polyimides is strongly bonded.On the other hand, wiring The conductors are bonded to each other by diffusion bonding.It is more preferable to thinly coat the surface of the wiring conductor with a metal that easily reacts chemically, since this will promote the reaction at the interface and form a strong bond.
４００℃程度で接合できるので、配線導体としては、銅
、アルミニウムなどの抵抗の低い配線材料を利用するこ
とができる０したがって、配線のパターニングは、ホト
リックラフ技術を使うことができるために１０μｍ程度
の微細配線の形成が可能となる０また、加熱における収
縮も少ない次めに寸法のずれも、セラミック多層基板に
比較して少なく、精度の高い微細配線の形成が可能であ
る０
フィルム形成の方法はいろいろあるが例えば、ポリイミ
ドフィルムにドライエツチングによジ配線パターンを形
成したのちに、Ｃｕ選択めっきによって、配線を形成す
ることなどがある０このようにして、配線形成されたポ
リイミドフィルムを基板からはがし、真空吸着により平
坦化したのちに、位置合せをして、下のポリイミドフィ
ルム上に重ねる。軽く圧着して仮接着し次後、更に次の
フィルムを同様にして積層していく。すべてのフィルム
が積層し終わったら、加圧して４００℃で加熱する。４
００℃でポリイミドは完全にイミド化し、同時に、界面
の接合も行われる。Since bonding can be performed at approximately 400°C, low resistance wiring materials such as copper and aluminum can be used as wiring conductors. Therefore, wiring patterning can be performed using photo-rough technology, so fine patterns of around 10 μm can be used. It is possible to form wiring lines.In addition, there is less shrinkage when heated.Secondly, there is less dimensional deviation compared to ceramic multilayer substrates, and it is possible to form fine wiring lines with high precision.There are various methods of film formation. However, for example, after forming a wiring pattern on a polyimide film by dry etching, wiring may be formed by selective Cu plating. In this way, the polyimide film on which the wiring has been formed is peeled off from the substrate, After flattening it by vacuum suction, it is aligned and stacked on the polyimide film below. After applying light pressure and temporary adhesion, the next film is laminated in the same manner. After all the films have been laminated, pressure is applied and heated at 400°C. 4
At 00°C, the polyimide is completely imidized, and at the same time, the interface is bonded.
以下、本発明を実施例により更に具体的に説明するが、
本発明蝶これら実施例に駆足されない。Hereinafter, the present invention will be explained in more detail with reference to Examples.
The present invention is not inspired by these examples.
実施例１
〔多層配線の形成〕
第１−１図に、本発明による多層配線の形成方法の１例
を概略工程図として示す。第１−２図は、その（′ｂ）
工程における丸印で囲んだ部分の拡大断面図である。各
図において、符号１はポリイミド樹脂、２は銅配線、５
は配線フィルム、４は多層フィルム、５は加圧荷重、６
は高周波誘導加熱ヒーター、７は銅配線間の拡散接合、
８はポリイミド樹脂間のイミド化反応による接合、９は
多層配線フィルム、１０はセラミック多層基板、１１は
はんだ、１２はＬＳＩを意味する。Example 1 [Formation of Multilayer Wiring] FIG. 1-1 shows a schematic process diagram of one example of a method for forming a multilayer wiring according to the present invention. Figure 1-2 shows its ('b)
It is an enlarged sectional view of the part surrounded by the circle mark in a process. In each figure, numeral 1 is polyimide resin, 2 is copper wiring, 5 is
is a wiring film, 4 is a multilayer film, 5 is a pressurized load, 6
is a high-frequency induction heater, 7 is a diffusion bond between copper wiring,
Reference numeral 8 indicates a bond formed by an imidization reaction between polyimide resins, 9 indicates a multilayer wiring film, 10 indicates a ceramic multilayer substrate, 11 indicates solder, and 12 indicates an LSI.
第１図に示すように、ポリイミド樹脂１中に、表面に金
薄膜が形成されている銅配ｆｆＭ２が形成されている配
線フィルム３（膜厚２０μｍ、１０１００Ｘ１０Ｑｖを
積層して得られる多層フィルム４を荷重５により加圧（
１０ｋｌｉｌ）して、ヒーター６により加熱（３５０℃
×５０分）することにより、銅配線と銅配線間±７は、
金属間の拡散接合で、またポリイミド同±８は、イミド
化による反応接置で結合させ、多層配線フィルム９を形
成する。As shown in FIG. 1, a multilayer film 4 obtained by laminating a wiring film 3 (film thickness 20 μm, 10100×10Qv) in which a copper wiring ffM2 with a thin gold film on the surface is formed in a polyimide resin 1 is used. Pressurized by load 5 (
10 kli) and heated with heater 6 (350℃
×50 minutes), the distance between copper wirings is ±7.
The multilayer wiring film 9 is formed by diffusion bonding between metals and by bonding the polyimide layers by reaction bonding through imidization.
更にこの多層配線フィルム？ｔ−セラミック基板１０に
搭載し、はんだ１１によりＬＳＩｆ２と接続し、多層配
線基板を完成させる０
〔配線フィルムの作製〕
第２図に、上記で用いたポリイミド樹脂便用の配線フィ
ルムの作製方法の１例を概略工程図として示す。第２図
において、符号１３はガラス基板、１４は銅薄膜、１５
はポリイミド樹脂薄膜、１６はスルーホールパターン、
１７は銅配線パターン、１８は金配線パターン、１９は
配線フィルム、２０は真空吸着治具、２１は２枚合せ配
線フィルムを意味する。Furthermore, this multilayer wiring film? It is mounted on a T-ceramic substrate 10 and connected to LSIf2 using solder 11 to complete a multilayer wiring board. One example is shown as a schematic process diagram. In FIG. 2, reference numeral 13 is a glass substrate, 14 is a copper thin film, and 15 is a glass substrate.
is a polyimide resin thin film, 16 is a through-hole pattern,
17 is a copper wiring pattern, 18 is a gold wiring pattern, 19 is a wiring film, 20 is a vacuum suction jig, and 21 is a two-layer wiring film.
第２図に示すように、ガラス基板１３（厚さ１６ｍ、１
００Ｘ１００■）上に銅薄膜１４（膜厚ａ１噛）を蒸着
した後、ポリイミド樹脂スを塗布し、２００℃、１時間
の加熱処理を行い、ポリイミド樹脂薄膜１５（膜厚２０
μｍ）を形成する。As shown in FIG. 2, a glass substrate 13 (16 m thick, 1
After depositing a copper thin film 14 (thickness A1) on a thin copper film 14 (film thickness A1), a polyimide resin was applied and heat-treated at 200°C for 1 hour to form a polyimide resin thin film 15 (thickness 20 cm).
μm).
次にポリイミド膜をホトエツチングにより、スルーホー
ルパターン１６を形成する。続いて、このスルーホール
部に電解銅めっき法により、銅配線パターン１７（膜厚
２１μｍ）、金配線パターン１８（膜厚α１μｍ）
ｔ−積層する。次に、ウェットエツチングにより、この
配線フィルム１９を基板より分離する。同様のプロセス
で得られた２枚の配線フィルムを、真空吸着板に互いに
吸着させ、配線パターンの整合を行い、加圧し密着し、
２枚を組合せた配線フィルム２１ｔ−作製する。Next, a through hole pattern 16 is formed by photoetching the polyimide film. Subsequently, a copper wiring pattern 17 (thickness: 21 μm) and a gold wiring pattern 18 (thickness α: 1 μm) were formed on this through-hole portion by electrolytic copper plating.
t-Layer. Next, this wiring film 19 is separated from the substrate by wet etching. Two wiring films obtained by the same process are adsorbed to each other on a vacuum suction plate, the wiring patterns are aligned, and pressure is applied to make them stick together.
A wiring film 21t is prepared by combining two sheets.
以上説明したように、本発明によれば配綜幅が小さく、
かつ積膚数の多い多層配線を比較的簡単なプロセスで形
成できる。各層の配線パターンを独立して形成できるた
め、逐次積層法に比較して不良の発生率を低減できる。As explained above, according to the present invention, the heald width is small;
Moreover, multilayer wiring with a large number of layers can be formed by a relatively simple process. Since the wiring patterns for each layer can be formed independently, the incidence of defects can be reduced compared to the sequential lamination method.
また、配線のバターニングはホトリノグラフ技術を利用
することができるために、１０μｍ程度の微細配線の形
成が可能である。更に、加熱圧着の温度は４００℃程度
でよいため、銅、アルミニウムなどの抵抗の低い金ｌ！
４を配線導体として用いることができる。本発明による
多層配線はＬＳＩ実装基板などに応用することがでさ、
電気信号の伝播速度の高速化に寄与することができる０Further, since patterning of wiring can utilize photorinographic technology, it is possible to form fine wiring of about 10 μm. Furthermore, since the temperature of heat-compression bonding only needs to be around 400°C, low-resistance metals such as copper and aluminum can be used!
4 can be used as a wiring conductor. The multilayer wiring according to the present invention can be applied to LSI mounting boards, etc.
0 that can contribute to increasing the propagation speed of electrical signals
第１−１図は本発明による多層配線の形成方法の１９＋
＋を示す概略工程図、第１−２図は第１−１図の（切工
程における丸印で囲んだ部分の拡大断面図、第２図は本
発明方法で用いるポリイミド樹脂使用の配線フィルムの
作製方法の１例を示す概略工程図である。
１・・・ポリイミド樹脂、２・・・銅配線、３・・・配
線フィルム、４・・・多層フィルム、５・・・加圧荷重
、６・・・高周波誘導加熱ヒーター、７・・・銅配線間
の拡散接合、８・・・ポリイミド樹脂間のイミド化反応
による接合、９・・・多層配線フィルム、１０・・・セ
ラミック多層基板、１１・・・はんだ、１２・・・ＬＳ
Ｉ、１５・・・ガラス基板、１４・・・銅薄膜、１５・
・・ポリイミド樹脂薄膜、１６−・・スルーホールパタ
ーン、１７・・・銅配線パターン、１８・・・金配線パ
ターン、１９・・・配線フィルム、 ２０−・・真空吸
着治具、２１・・・２枚合せ配線フィルムFigure 1-1 shows 19+ of the method for forming multilayer wiring according to the present invention.
1-2 is an enlarged sectional view of the part surrounded by a circle in the cutting process of FIG. 1-1, and FIG. It is a schematic process diagram showing one example of a production method. 1... Polyimide resin, 2... Copper wiring, 3... Wiring film, 4... Multilayer film, 5... Pressure load, 6... ... High frequency induction heater, 7... Diffusion bonding between copper wiring, 8... Bonding by imidization reaction between polyimide resins, 9... Multilayer wiring film, 10... Ceramic multilayer board, 11 ...Solder, 12...LS
I, 15... Glass substrate, 14... Copper thin film, 15.
...Polyimide resin thin film, 16-...Through hole pattern, 17...Copper wiring pattern, 18...Gold wiring pattern, 19...Wiring film, 20-...Vacuum suction jig, 21... 2-ply wiring film
Claims (1)
る多層配線の形成方法において、配線形成されたポリイ
ミドフィルムを一括積層する工程、及び積層体を加熱圧
着する工程の各工程を包含することを特徴とする多層配
線の形成方法。 ２、該ポリイミドフィルムは、イミド化が完結しない状
態で該一括積層され、積層後の加熱により完全にイミド
化される特許請求の範囲第１項記載の多層配線の形成方
法。 ３、該ポリイミドフィルム中に形成される配線導体の端
面には、金属同士の拡散反応を促進するために、配線導
体と異なる金属がコーティングされている特許請求の範
囲第１項又は第２項記載の多層配線の形成方法。[Scope of Claims] 1. In a method for forming a multilayer wiring made of a wiring conductor and an insulating heat-resistant polyimide resin, each of the steps of laminating the polyimide films on which the wiring has been formed at once and heat-pressing the laminate 1. A method for forming a multilayer interconnection comprising steps. 2. The method for forming a multilayer wiring according to claim 1, wherein the polyimide films are laminated at once without completion of imidization, and are completely imidized by heating after lamination. 3. The end face of the wiring conductor formed in the polyimide film is coated with a metal different from that of the wiring conductor in order to promote a diffusion reaction between metals. A method for forming multilayer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10898787A JPS63274199A (en) | 1987-05-06 | 1987-05-06 | Formation of multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10898787A JPS63274199A (en) | 1987-05-06 | 1987-05-06 | Formation of multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63274199A true JPS63274199A (en) | 1988-11-11 |
Family
ID=14498715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10898787A Pending JPS63274199A (en) | 1987-05-06 | 1987-05-06 | Formation of multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63274199A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03204994A (en) * | 1989-10-03 | 1991-09-06 | Nec Corp | Manufacture of polyimide multilayer wiring board |
| US5274912A (en) * | 1992-09-01 | 1994-01-04 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
| US5440805A (en) * | 1992-03-09 | 1995-08-15 | Rogers Corporation | Method of manufacturing a multilayer circuit |
| JP2001043961A (en) * | 1999-07-28 | 2001-02-16 | Keihin Sokki Kk | Heater device for semiconductor wafer and its manufacture |
| US6274404B1 (en) | 1998-09-25 | 2001-08-14 | Nec Corporation | Multilayered wiring structure and method of manufacturing the same |
| JP2004327948A (en) * | 2003-04-24 | 2004-11-18 | Sanei Kagaku Kk | Multilayer circuit board and method of fabricating the same |
-
1987
- 1987-05-06 JP JP10898787A patent/JPS63274199A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03204994A (en) * | 1989-10-03 | 1991-09-06 | Nec Corp | Manufacture of polyimide multilayer wiring board |
| US5440805A (en) * | 1992-03-09 | 1995-08-15 | Rogers Corporation | Method of manufacturing a multilayer circuit |
| US5274912A (en) * | 1992-09-01 | 1994-01-04 | Rogers Corporation | Method of manufacturing a multilayer circuit board |
| US6274404B1 (en) | 1998-09-25 | 2001-08-14 | Nec Corporation | Multilayered wiring structure and method of manufacturing the same |
| US6351026B2 (en) | 1998-09-25 | 2002-02-26 | Nec Corporation | Multilayered wiring structure and method of manufacturing the same |
| JP2001043961A (en) * | 1999-07-28 | 2001-02-16 | Keihin Sokki Kk | Heater device for semiconductor wafer and its manufacture |
| JP2004327948A (en) * | 2003-04-24 | 2004-11-18 | Sanei Kagaku Kk | Multilayer circuit board and method of fabricating the same |
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