JPH01205558A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH01205558A JPH01205558A JP3107888A JP3107888A JPH01205558A JP H01205558 A JPH01205558 A JP H01205558A JP 3107888 A JP3107888 A JP 3107888A JP 3107888 A JP3107888 A JP 3107888A JP H01205558 A JPH01205558 A JP H01205558A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- substrate
- hybrid integrated
- semiconductor integrated
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000919 ceramic Substances 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 229910052878 cordierite Inorganic materials 0.000 claims abstract description 6
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical group [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野］
本発明は半導体集積回路素子をバンプ電極を介して搭載
した混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit in which semiconductor integrated circuit elements are mounted via bump electrodes.
［従来の技術］
従来の混成集積回路においては、アルミナ（Ａ！２２０
２）を主成分とするセラミック基板上に厚膜印刷技術又
は薄膜パターン形成技術により導体配線層が形成されて
配線基板が構成されている。そして、この配線基板上に
半導体集積回路素子を導電性ペース１−又は絶縁性ペー
スト等のダイボンディンク剤を使用して搭載し、更に、
半導体集積回路素子電極と配線基板電極とをワイヤボン
デインクにより接続している。[Prior Art] In conventional hybrid integrated circuits, alumina (A!220
A conductor wiring layer is formed on a ceramic substrate mainly composed of 2) by thick film printing technology or thin film pattern forming technology to constitute a wiring board. Then, a semiconductor integrated circuit element is mounted on this wiring board using a die bonding agent such as a conductive paste 1- or an insulating paste, and further,
The semiconductor integrated circuit element electrode and the wiring board electrode are connected by wire bonding ink.
しかしなから、この従来の混成集積回路は、半導体集積
回路素子と配線基板とをワイヤポンチインクにより電気
的に接続しているために、配線基板上の半導体集積回路
素子搭載部の周辺にワイヤポンディング用の電極を配置
する必要がある。このノコめ、半導体集積回路素子の実
装効率か低いという欠点かある。However, in this conventional hybrid integrated circuit, since the semiconductor integrated circuit element and the wiring board are electrically connected by wire punch ink, the wire punch is placed around the semiconductor integrated circuit element mounting area on the wiring board. It is necessary to arrange electrodes for The disadvantage of this saw is that the mounting efficiency of semiconductor integrated circuit elements is low.
そこで、上記欠点を改良するために、第３図に示すよう
に、フリップチップ実装方式の混成集積回路か開発され
ている。このフリップチップ実装方式においては、アル
ミナセラミック基板上に導体配線層（図示せず）が形成
されてなる配線基板１２上に、半田を半球状に盛り上げ
て端子電極（以下、バンプ電極という）１３を形成し、
このバンプ電極１３を介して半導体集積回路素子１１と
配線基板１２との間を電気的に溶融接続している。In order to improve the above-mentioned drawbacks, a flip-chip mounting type hybrid integrated circuit has been developed as shown in FIG. In this flip-chip mounting method, terminal electrodes (hereinafter referred to as bump electrodes) 13 are formed by hemispherically hemispherically mounding solder on a wiring board 12 that is formed by forming a conductor wiring layer (not shown) on an alumina ceramic substrate. form,
The semiconductor integrated circuit element 11 and the wiring board 12 are electrically fused and connected via the bump electrodes 13.
このフリップチップ実装方式の混成集積回路においては
、ワイヤポンチインクによって集積回路素子を実装する
場合と比較して実装効率か」二がるという利点かある。This flip-chip mounting hybrid integrated circuit has an advantage in that the mounting efficiency is lower than when integrated circuit elements are mounted using wire punch and ink.
［発明か解決しようとする課題］
しかしなから、この従来のフリップチップ実装方式の混
成集積回路においては、接合部となるハンプ電４φ１３
かフレキシピリティに乏しいため、配線基板］２と半導
体集積回路素子１１との間の熱膨張係数の相異に起因す
る機械的ス１〜レスによって、接合不良か発生ずるとい
う欠点がある。[Problem to be solved by the invention] However, in this conventional flip-chip mounting type hybrid integrated circuit, the hump wire 4φ13
Due to the poor flexibility, there is a drawback that poor bonding may occur due to mechanical stress caused by the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor integrated circuit element 11.
本発明はかかる問題点に鑑みてなされたちのてあって、
ハング電極の接合不良が防止され、信頼性が向」ニした
混成集積回路を提供することを目的とする。The present invention was made in view of such problems, and
It is an object of the present invention to provide a hybrid integrated circuit in which poor connection of hanging electrodes is prevented and reliability is improved.
［課題を解決するための手段］
本発明に係る混成集積回路は、コーシェライ１へを主成
分とするセラミック基板上に導体配線層が形成された配
線基板と、この配線基板−ににバンプ電極を介して搭載
され電気的に接続された半導体集積回路素子とを有する
ことを特徴とする。[Means for Solving the Problems] A hybrid integrated circuit according to the present invention includes a wiring board in which a conductor wiring layer is formed on a ceramic substrate mainly composed of Kocherei 1, and bump electrodes on the wiring board. It is characterized by having a semiconductor integrated circuit element mounted through and electrically connected to the semiconductor integrated circuit element.
［作用］
本発明においては、配線基板Ｉ−にハンプ電極を介して
半導体集積回路素子を搭載したから、ワイヤポンチイン
ク用電極を配置する必要かないので、実装効率か向」ニ
して集積度が向上する。[Function] In the present invention, since the semiconductor integrated circuit element is mounted on the wiring board I- through the hump electrode, there is no need to arrange a wire punch ink electrode, so the degree of integration is reduced in terms of mounting efficiency. improves.
また、配線基板はシリコン（Ｓｉ）と同程度の熱膨張係
数を有するコーシェライｌ−（２Ｍｇ０２Ａ（１２０３
５Ｓ ｉ○２）を主成分とするセラミック基板」ユに導
体配線層を形成したちのであるから、熱ストレスに起因
するハンプ電極の接合不良が抑制される。このため、混
成集積回路の信頼性が向」−する。In addition, the wiring board is made of Kocherite l-(2Mg02A(1203), which has a coefficient of thermal expansion similar to that of silicon (Si).
Since the conductor wiring layer is formed on the ceramic substrate whose main component is 5S i○2), poor bonding of the hump electrodes due to thermal stress is suppressed. This improves the reliability of the hybrid integrated circuit.
［実施例］
次に、本発明の実施例について添付の図面を参照して説
明する。[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.
第１図（ａ）、（ｂ）は本発明の実施例に係る混成集積
回路の製造工程を示す断面図、第１図（ｃ）はこの混成
集積回路を示す断面図である。FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing process of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 1(c) is a cross-sectional view showing this hybrid integrated circuit.
第１図（ａ）に示すセラミック基板］−は以下のように
して製造される。先ず、Ｚｎ○−ＭｇＯ−Ａρ２０３−
８ｊＯ２系のセラミックスを主成分とする結晶化カラス
粉末に有機バインダーを加え、１〜クターブレード法に
より厚さか２００μｍのグリーンシー）・を作製する。The ceramic substrate shown in FIG. 1(a) is manufactured as follows. First, Zn○-MgO-Aρ203-
An organic binder is added to crystallized glass powder containing 8jO2-based ceramics as a main component, and a green sheet (green sea) with a thickness of about 200 μm is prepared by the 1 to 200 μm cutting method.
そして、このグリーンシートを積層した後、脱パインタ
′−を行い、常圧で９００ ’Ｃに加熱して焼成するこ
とにより、コージェライトセラミック基板１を得る。こ
のコージェライトセラミック基板１の熱膨張係数は約３
、０Ｘ ］、 ０−６７にである。After the green sheets are laminated, the green sheets are de-pintered, and the cordierite ceramic substrate 1 is obtained by heating and firing at 900'C at normal pressure. The coefficient of thermal expansion of this cordierite ceramic substrate 1 is approximately 3
, 0X ], 0-67.
第１１図（ｂ）はこのセラミック基板１上に公知の薄膜
パターン形成工程によりＴｉ−Ｐｄ−Ａｕ積層膜からな
る導体配線層２をパターン形成し、更に、５ｊ０２−３
ｉ３Ｎ４積層膜からなる保護絶縁層３をパターン形成し
て構成された配線基板４を示す。保護絶縁層３は配線層
２間の領域を埋めると共に、配線Ｍ２上の所定の領域に
開口部を有するように配線層２上に形成される。FIG. 11(b) shows that a conductor wiring layer 2 made of a Ti-Pd-Au laminated film is patterned on this ceramic substrate 1 by a known thin film patterning process, and then
A wiring board 4 constructed by patterning a protective insulating layer 3 made of an i3N4 laminated film is shown. The protective insulating layer 3 is formed on the wiring layer 2 so as to fill the area between the wiring layers 2 and to have an opening in a predetermined area on the wiring M2.
そして、第１図（Ｃ）に示すように、配線基板４のセラ
ミック基板１」二に形成された配線層２の保護絶縁層３
に覆われていない前記所定の領域にハンプ電極５を配設
し、このバンプ電極５を介して半導体集積回路素子６を
搭載すると共に、半導体集積回路素子６の各電極と配線
層２とを電気的に接続する。続いて、チップ部品の搭載
及び接続、外部端子の接続並びに外装樹脂による封止を
行って混成集積回路が得られる。As shown in FIG. 1(C), the protective insulating layer 3 of the wiring layer 2 formed on the ceramic substrate 1''2 of the wiring board 4
A hump electrode 5 is arranged in the predetermined area not covered by the bump electrode 5, and a semiconductor integrated circuit element 6 is mounted via the bump electrode 5, and each electrode of the semiconductor integrated circuit element 6 and the wiring layer 2 are electrically connected. Connect to Subsequently, a hybrid integrated circuit is obtained by mounting and connecting chip components, connecting external terminals, and sealing with an exterior resin.
このようにして構成された混成集積回路は、配線基板４
のセラミック基板１かコージェライト製であるから、そ
の熱膨張係数が３．０ＸＩＯ−６／にと半導体集積回路
素子６を構成するシリコン基板の熱膨張係数と略々等し
い。このため、混成集積回路に熱が印加されても、バン
プ電極５に熱ス１−レスか発生ずることはなく、バンプ
電極５の接合不良か防止される。The hybrid integrated circuit configured in this way has a wiring board 4
Since the ceramic substrate 1 is made of cordierite, its coefficient of thermal expansion is 3.0XIO-6/, which is approximately equal to the coefficient of thermal expansion of the silicon substrate constituting the semiconductor integrated circuit element 6. Therefore, even if heat is applied to the hybrid integrated circuit, thermal stress does not occur on the bump electrodes 5, and bonding failures of the bump electrodes 5 are prevented.
次に、本発明の実施例に係る混成集積回路を実際に製造
して、その熱ストレス負荷試験を実施した結果について
説明する。実施例１．２及び従来例に係る混成集積回路
の各要素の材質は下記第１表のとおりである。Next, a description will be given of the results of actually manufacturing a hybrid integrated circuit according to an embodiment of the present invention and conducting a thermal stress load test on the hybrid integrated circuit. The materials of each element of the hybrid integrated circuit according to Examples 1 and 2 and the conventional example are shown in Table 1 below.
第 １ 表
なお、従来例の９６％アルミナセラミック基板の熱膨張
係数は、８．０ｘｌＯ−６／にであった。Table 1 The thermal expansion coefficient of the conventional 96% alumina ceramic substrate was 8.0xlO-6/.
この実施例１，２及び比較例に係る混成集積回路に対し
、−５５°Ｃと１５０°Ｃとの間の温度ザイクルを与え
る評価試験を実施し、その特性を求めたところ、第２図
に示すような結果か得られた。The hybrid integrated circuits according to Examples 1 and 2 and the comparative example were subjected to an evaluation test in which a temperature cycle was applied between -55°C and 150°C, and their characteristics were determined, as shown in Figure 2. The results shown were obtained.
第２図は横軸に試験サイクル数（対数目盛）をとり、縦
軸に累積不良率をとって、熱サイクル数と不良率との関
係を示すグラフ図である。図中、Ａは本発明の実施例１
−２２に係る混成集積回路の試験結果を示し、Ｂは従来
例に係る混成集積回路の試験結果を示す。この第２図か
ら明らかなように、従来例の混成集積回路においては、
］、 ＯＯザイクルを超えると、不良か多発するのに対
し、本発明の実施例品は３００サイクルに至ってもなお
不良の発生は皆無である。このように、第２図には、本
実施例により、不良率改善の効果か著しいことか明確に
示されている。FIG. 2 is a graph showing the relationship between the number of thermal cycles and the failure rate, with the horizontal axis representing the number of test cycles (logarithmic scale) and the vertical axis representing the cumulative failure rate. In the figure, A is Example 1 of the present invention
22 shows the test results of the hybrid integrated circuit according to the conventional example, and B shows the test results of the hybrid integrated circuit according to the conventional example. As is clear from FIG. 2, in the conventional hybrid integrated circuit,
], If the cycle exceeds OO cycle, defects occur frequently, but the example product of the present invention has no defects even after 300 cycles. In this way, FIG. 2 clearly shows that the present example has a remarkable effect on improving the defective rate.
［発明の効果］
以上説明したように、本発明はコーシェライ１へを主成
分とするセラミック基板上に導体配線層が形成されてな
る配線基板上に、ハンプ電極を介して半導体集積回路素
子を搭載したから、セラミック基板は、半導体集積回路
素子の構成要素の基板シリコンと同等の熱膨張係数を有
するので、熱ストレスに起因するバンプ電極の接合不良
を回避し、ひいては、混成集積回路の信頼性を向」ニさ
せることかできる。[Effects of the Invention] As explained above, the present invention mounts a semiconductor integrated circuit element via a hump electrode on a wiring board in which a conductive wiring layer is formed on a ceramic substrate mainly composed of Kosherei 1. Therefore, since the ceramic substrate has a coefficient of thermal expansion equivalent to that of the substrate silicon, which is a component of a semiconductor integrated circuit element, it is possible to avoid poor bonding of bump electrodes due to thermal stress, and in turn improve the reliability of the hybrid integrated circuit. It is possible to make someone move towards you.
また、従来、−射的な混成集積回路で必要とされていた
半導体集積回路素子搭載部の周辺のワイヤホンディンク
用電極の配置が不要となるために、半導体集積回路素子
の実装効率の向」二による高集積化か可能であることは
勿論である。In addition, since it is no longer necessary to arrange electrodes for wire-phone dipping around the semiconductor integrated circuit element mounting area, which was conventionally required in optical hybrid integrated circuits, the mounting efficiency of semiconductor integrated circuit elements can be improved. Of course, it is possible to achieve high integration by using the second method.
第１図（ａ＞、（ｂ）は本発明の実施例に係る混成集積
回路の製造工程を示す断面図、第１図（Ｃ）は同しく製
造された混成集積回路を示す断面図、第２図は実施例］
、２及び比較例の混成集積回路の温度ザイクル試験結果
を示すグラフ図、第３図は従来のフリップチップ実装方
式の混晟集積回路を示す断面図である。
１；コージェライ１へセラミック基板、２；導体配線層
、３：保護絶縁層、４，１２．配線基板、５．１３；バ
ンプ電極、６．１１−；半導体集積回路素子、Ａ：実施
例１，２に係る混成集積回路の試験結果、Ｂ；従来例に
係る混成集積回路の試験結果FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing process of a hybrid integrated circuit according to an embodiment of the present invention, FIG. 1(C) is a cross-sectional view showing a similarly manufactured hybrid integrated circuit, and FIG. Figure 2 is an example]
, 2 and a comparative example, and FIG. 3 is a sectional view showing a conventional flip-chip mounting type hybrid integrated circuit. 1; Ceramic substrate for cordierai 1, 2; Conductor wiring layer, 3: Protective insulating layer, 4, 12. Wiring board, 5.13; Bump electrode, 6.11-; Semiconductor integrated circuit element, A: Test results of hybrid integrated circuits according to Examples 1 and 2, B: Test results of hybrid integrated circuit according to conventional example
Claims (1)
に導体配線層が形成された配線基板と、この配線基板上
にバンプ電極を介して搭載され電気的に接続された半導
体集積回路素子とを有することを特徴とする混成集積回
路。(1) It has a wiring board in which a conductor wiring layer is formed on a ceramic substrate whose main component is cordierite, and a semiconductor integrated circuit element mounted on the wiring board and electrically connected to it via bump electrodes. A hybrid integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3107888A JPH01205558A (en) | 1988-02-12 | 1988-02-12 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3107888A JPH01205558A (en) | 1988-02-12 | 1988-02-12 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01205558A true JPH01205558A (en) | 1989-08-17 |
Family
ID=12321395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3107888A Pending JPH01205558A (en) | 1988-02-12 | 1988-02-12 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01205558A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03259571A (en) * | 1990-03-08 | 1991-11-19 | Fujitsu Ltd | Photodetector |
-
1988
- 1988-02-12 JP JP3107888A patent/JPH01205558A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03259571A (en) * | 1990-03-08 | 1991-11-19 | Fujitsu Ltd | Photodetector |
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