JPH01214116A - Method of filling in contact hole - Google Patents
Method of filling in contact holeInfo
- Publication number
- JPH01214116A JPH01214116A JP4117088A JP4117088A JPH01214116A JP H01214116 A JPH01214116 A JP H01214116A JP 4117088 A JP4117088 A JP 4117088A JP 4117088 A JP4117088 A JP 4117088A JP H01214116 A JPH01214116 A JP H01214116A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- hole
- substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052986 germanium hydride Inorganic materials 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に、コンタ
クト孔の選択的埋込方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for selectively filling contact holes.
半導体基板内に設けられ極浅い拡散層とオーミックコン
タクトをとる場合、アロイスパイクを防止する方法とし
て、コンタクト孔に選択埋込な行う技術がある。When making ohmic contact with an extremely shallow diffusion layer provided in a semiconductor substrate, there is a technique for selectively filling contact holes as a method for preventing alloy spikes.
従来、コンタクト孔の選択的埋込には、熱化学気相成長
法によるタングステン(W)の選択成長。Conventionally, selective filling of contact holes involves selective growth of tungsten (W) by thermal chemical vapor deposition.
シリコン(Si )の選択エピタキシャル成長等が用い
られている。Selective epitaxial growth of silicon (Si) is used.
上述した従来の埋込方法には以下のような欠点がある。 The conventional embedding method described above has the following drawbacks.
1、熱化学気相成長法によるWの選択成長の場合。1. In case of selective growth of W by thermochemical vapor deposition method.
タングステン(W)の初期析出は、基板Stとの反応に
よって生じ、この化学反応は下記のように表わされる。The initial precipitation of tungsten (W) occurs through reaction with the substrate St, and this chemical reaction is expressed as follows.
この結果、拡散層の浸食が生じ、これがジャンクション
の電気特性に悪影響を与える。This results in erosion of the diffusion layer, which adversely affects the electrical properties of the junction.
2’、 Siの選択エピタキシャル成長の場合。2', In the case of selective epitaxial growth of Si.
プロセス温度が高い(≧950℃)ため、浅い拡散層が
必要とされる半導体装置には不適当である。また、形成
した膜の比抵抗が金属に比べて高く、コンタクト抵抗を
十分に下げることができない。Since the process temperature is high (≧950° C.), it is unsuitable for semiconductor devices that require a shallow diffusion layer. Furthermore, the specific resistance of the formed film is higher than that of metal, and the contact resistance cannot be lowered sufficiently.
本発明のコンタクト埋込法は、コンタクト孔底部に選択
的に半導体膜を形成する工程と、その半導体股上に選択
的に金属膜を形成する工程とを有している。The contact burying method of the present invention includes a step of selectively forming a semiconductor film at the bottom of a contact hole, and a step of selectively forming a metal film on the semiconductor ridge.
まず、1000人程度0半導体膜をコンタクト孔底部に
短時間で選択的に形成し、この半導体膜をバッファとし
て用いて金属膜を形成することにより、金属膜材料の拡
散層への浸入が防止され、高信頼度かつ低抵抗コンタク
トを実現しうる選択埋込方法を提供できる。First, by selectively forming a semiconductor film of about 1,000 nanometers at the bottom of the contact hole in a short time and using this semiconductor film as a buffer to form a metal film, it is possible to prevent the metal film material from penetrating into the diffusion layer. , it is possible to provide a selective embedding method that can realize highly reliable and low resistance contacts.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a) 、 (b)は本発明のコンタクト孔埋込
方法の第1の実施例を示す半導体装置の断面図である。FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor device showing a first embodiment of the contact hole filling method of the present invention.
本実施例は、シリコン(Si )基板1の主表面に形成
された絶縁膜(Si 02膜)2に部分的に設けられた
コンタクト孔3を以下の工程により埋込む。In this embodiment, a contact hole 3 partially formed in an insulating film (Si 02 film) 2 formed on the main surface of a silicon (Si 2 ) substrate 1 is filled by the following steps.
(1)コンタクト孔3の底部すなわち、拡散層5上に、
ゲルマニウム(Ge)膜4を熱化学気相成長法によって
選択形成する。このGeの選択形成には、GeHaとH
2を原料ガスとした熱化学気相成長法を用い、成長条件
は、例えば基板温度400℃、全圧2Torr、 Ge
H,aとhの分圧比を1:10.成膜時間10分とし、
約800人のGe膜をコンタクト孔3の底部に選択的に
堆積する(第1図(a))。(1) At the bottom of the contact hole 3, that is, on the diffusion layer 5,
A germanium (Ge) film 4 is selectively formed by thermal chemical vapor deposition. This selective formation of Ge requires GeHa and H
The growth conditions are, for example, a substrate temperature of 400° C., a total pressure of 2 Torr, and a total pressure of 2 Torr.
The partial pressure ratio of H, a and h is 1:10. The film formation time was 10 minutes,
About 800 Ge films are selectively deposited on the bottom of the contact hole 3 (FIG. 1(a)).
(2)次に、このGe膜膜上上、WFsとH2を用いた
熱化学気相成長法により、タングステン(W)膜6を堆
積する。この場合、成長条件を基板温度500℃、全圧
0.2 Torr、 WFs分圧2X10−4Tor
r、成膜時間10分とすると約8000人のW膜6が堆
積し、コンタクト孔3が埋込まれる(第1図(b))。(2) Next, a tungsten (W) film 6 is deposited on this Ge film by thermal chemical vapor deposition using WFs and H2. In this case, the growth conditions were as follows: substrate temperature 500°C, total pressure 0.2 Torr, WFs partial pressure 2X10-4 Torr.
If the deposition time is 10 minutes, approximately 8,000 W films 6 are deposited and the contact hole 3 is filled (FIG. 1(b)).
Ge膜膜上上のW膜6の堆積は堆積初期には次式(1)
、 (2) 、 (3)の反応により進行し、いった
ん緻密なW膜が形成されると、式(4)の反応が支配的
に進行する。The deposition of the W film 6 on the Ge film is performed by the following formula (1) at the initial stage of deposition.
, (2), and (3), and once a dense W film is formed, the reaction of formula (4) proceeds dominantly.
3/2Ge+WFa → W+3/2GeFa ↑
・(1)3Ge+WFe −) W+3Ge
F2−(2)2GeF2 −) GeHGeF
4 ↑ −(3)WF6+3H2→W+6HF
↑ ・・・(4)本実施例に示した成膜条件を用い
ると、Ge膜4は、W膜6の成長時に消費され、埋込み
終了時には、W膜6が拡散層5を極めてわずかに浸食し
た状態で終了する。このため、拡散層5はWと直接に接
触し、十分に低抵抗のオーミック特性が実現され、ジャ
ンクションリーク特性も良好となる。3/2Ge+WFa → W+3/2GeFa ↑
・(1)3Ge+WFe −) W+3Ge
F2-(2)2GeF2-) GeHGeF
4 ↑ −(3) WF6+3H2→W+6HF
↑ ...(4) Using the film forming conditions shown in this example, the Ge film 4 is consumed during the growth of the W film 6, and at the end of the embedding, the W film 6 erodes the diffusion layer 5 very slightly. It will end in this state. Therefore, the diffusion layer 5 is in direct contact with W, achieving sufficiently low resistance ohmic characteristics and good junction leak characteristics.
第2図(a) 、 (b)は本発明のコンタクト孔埋込
方法の第2の実施例を示す半導体装置の断面図である。FIGS. 2(a) and 2(b) are cross-sectional views of a semiconductor device showing a second embodiment of the contact hole filling method of the present invention.
本実施例は、コンタクト孔3の底部に設けられるGe膜
4の厚さを厚く(例えば、1000Å以上)し、W膜6
を形成後もGe膜4をバリア層として介在させるもので
ある。この場合、Ge膜4の介在によるコンタクト抵抗
を低減するために、W膜6形成前に、Ge膜膜内内■あ
るいはV属の不純物をイオン注入法により導入する(第
2図(a))。この後、W膜6を埋込む(第2図(b)
)。本実施例では、W膜6が拡散層5中にまったく侵入
せず、極めて良好なジャンクション特性が得られる。In this embodiment, the thickness of the Ge film 4 provided at the bottom of the contact hole 3 is increased (for example, 1000 Å or more), and the W film 6 is
Even after the formation of the Ge film 4, the Ge film 4 is interposed as a barrier layer. In this case, in order to reduce the contact resistance due to the interposition of the Ge film 4, impurities of the group III or V are introduced into the Ge film by ion implantation before forming the W film 6 (FIG. 2(a)). . After this, the W film 6 is embedded (Fig. 2(b)
). In this example, the W film 6 does not penetrate into the diffusion layer 5 at all, and extremely good junction characteristics can be obtained.
第3図(a) 、 (b)は本発明のコンタクト孔埋込
方法の第3の実施例を示す半導体装置の断面図である。FIGS. 3(a) and 3(b) are cross-sectional views of a semiconductor device showing a third embodiment of the contact hole filling method of the present invention.
本実施例は、コンタクト孔3の底部に設ける半導体層を
シリコン(Si)膜7としたものである。In this embodiment, the semiconductor layer provided at the bottom of the contact hole 3 is a silicon (Si) film 7.
すなわち、第3図(a)に示されるように、コンタクト
孔3の底部に&膜7を堆積する。この堆積は、例えば、
原料ガスとして5LH2C12,H2,HClヲ用い、
全圧50 Torr、 HCI!を1.QvolX、
5it−12cj!2を0.4vo1%、ウェハ温度
950℃の条件で行なわれ、約500人の選択エピタキ
シャルSi膜7が形成される(第3図(a))。次に、
W膜6を、前述の実施例と同様の条件で堆積する(第3
図(b))。本実施例では、拡散H5への浸食をほとん
ど生じさせずに、W膜6によるコンタクト孔埋込みを実
現できる。That is, as shown in FIG. 3(a), the & film 7 is deposited at the bottom of the contact hole 3. Then, as shown in FIG. This deposition can be caused by e.g.
Using 5LH2C12, H2, HCl as raw material gas,
Total pressure 50 Torr, HCI! 1. QvolX,
5it-12cj! 2 at 0.4 vol. 1% and a wafer temperature of 950° C., approximately 500 selective epitaxial Si films 7 are formed (FIG. 3(a)). next,
A W film 6 is deposited under the same conditions as in the previous example (third
Figure (b)). In this embodiment, the contact hole can be filled with the W film 6 without causing almost any erosion to the diffusion H5.
以上説明したように本発明は、半導体膜をバリヤ層とし
てコンタクト孔内へ金属膜を埋込むことにより、以下の
ような効果がある。As explained above, the present invention has the following effects by burying a metal film into a contact hole using a semiconductor film as a barrier layer.
1、 拡散層上に直接W膜を選択成長させる従来法(化
学気相成長法による選択W膜形成)と異なり、拡散層へ
の浸食が防止できるので、拡散層一基板間のリーク電流
特性を大幅に改善できる。1. Unlike the conventional method of selectively growing a W film directly on the diffusion layer (selective W film formation using chemical vapor deposition), erosion of the diffusion layer can be prevented, so the leakage current characteristics between the diffusion layer and the substrate can be reduced. It can be significantly improved.
2、 半導体膜を選択的にコンタクト孔内に埋込むだけ
の従来法(選択エピタキシャル法)と異なり、コンタク
ト埋込材料の大半あるいはすべてが金属膜であるため、
低抵抗コンタクトが実現できる。2. Unlike the conventional method (selective epitaxial method), which only selectively embeds a semiconductor film into the contact hole, most or all of the contact embedding material is a metal film.
A low resistance contact can be realized.
3、半導体膜としてGe膜を用いる場合は、プロセス温
度を低く維持できるため、浅接合デバイスへの適用が容
易である。3. When a Ge film is used as the semiconductor film, the process temperature can be kept low, making it easy to apply to shallow junction devices.
4、 半導体膜として3膜を用いる場合も、その成膜時
間が短い(1分以内)ため、従来の選択3エピタキシヤ
ル法による埋込にくらべ、拡散層への影響が少い。4. Even when 3 films are used as the semiconductor film, since the film formation time is short (within 1 minute), the effect on the diffusion layer is less than that of embedding by the conventional selective 3 epitaxial method.
第1図(a) 、 (b)は本発明のコンタクト孔埋込
方法の第1の実施例を示す半導体装置の断面図、第2図
(a) 、 (b)は本発明のコンタクト孔埋込方法の
第2の実施例を示す半導体装置の断面図、第3図(a)
、 (b)は本発明のコンタクト孔埋込方法の第3の
実施例を示す半導体装置の断面図である。
1・・・一基板、 2・・・8i 02膜3・・
・コンタクト孔、
4・・・Ge膜、 5・・・拡散層、6・・・
W膜、 7・・・Si膜。
特許出願人 日 本 電 気 株 式 台 71代 理
人 弁理士 内 原 晋(a)
(b)
第1図
(a)
(b)
第2図FIGS. 1(a) and (b) are cross-sectional views of a semiconductor device showing a first embodiment of the contact hole filling method of the present invention, and FIGS. FIG. 3(a) is a cross-sectional view of a semiconductor device showing a second embodiment of the embedding method.
, (b) is a sectional view of a semiconductor device showing a third embodiment of the contact hole filling method of the present invention. 1...One substrate, 2...8i 02 film 3...
・Contact hole, 4...Ge film, 5...diffusion layer, 6...
W film, 7...Si film. Patent applicant: Japan Electric Co., Ltd., 71st Attorney, Susumu Uchihara (a) (b) Figure 1 (a) (b) Figure 2
Claims (1)
タクト孔の底部に選択的に半導体膜を形成する工程と、 該半導体膜上に選択的に金属膜を形成する工程とを有す
ることを特徴とするコンタクト孔埋込方法。 2、半導体膜形成後該半導体膜中にIII属あるいはV属
の不純物を導入する工程を有する請求項1に記載のコン
タクト孔の埋込方法。[Claims] 1. A method for burying a contact hole in a semiconductor device, comprising the steps of selectively forming a semiconductor film at the bottom of the contact hole, and selectively forming a metal film on the semiconductor film. A contact hole embedding method characterized by comprising: 2. The contact hole filling method according to claim 1, further comprising the step of introducing group III or group V impurities into the semiconductor film after forming the semiconductor film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4117088A JPH01214116A (en) | 1988-02-23 | 1988-02-23 | Method of filling in contact hole |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4117088A JPH01214116A (en) | 1988-02-23 | 1988-02-23 | Method of filling in contact hole |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01214116A true JPH01214116A (en) | 1989-08-28 |
Family
ID=12600950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4117088A Pending JPH01214116A (en) | 1988-02-23 | 1988-02-23 | Method of filling in contact hole |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01214116A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0258217A (en) * | 1988-08-24 | 1990-02-27 | Nippon Telegr & Teleph Corp <Ntt> | Metallic film forming method |
EP0429950A2 (en) * | 1989-11-24 | 1991-06-05 | Gte Laboratories Incorporated | Junction field effect transistor and method of fabricating |
JPH03150875A (en) * | 1989-11-07 | 1991-06-27 | Nec Corp | Semiconductor device |
JPH03150874A (en) * | 1989-11-07 | 1991-06-27 | Nec Corp | Semiconductor device |
JPH0684827A (en) * | 1992-02-27 | 1994-03-25 | Internatl Business Mach Corp <Ibm> | Local interconnection provided with germanium layer |
-
1988
- 1988-02-23 JP JP4117088A patent/JPH01214116A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0258217A (en) * | 1988-08-24 | 1990-02-27 | Nippon Telegr & Teleph Corp <Ntt> | Metallic film forming method |
JPH03150875A (en) * | 1989-11-07 | 1991-06-27 | Nec Corp | Semiconductor device |
JPH03150874A (en) * | 1989-11-07 | 1991-06-27 | Nec Corp | Semiconductor device |
EP0429950A2 (en) * | 1989-11-24 | 1991-06-05 | Gte Laboratories Incorporated | Junction field effect transistor and method of fabricating |
EP0429950A3 (en) * | 1989-11-24 | 1993-08-11 | Gte Laboratories Incorporated | Junction field effect transistor and method of fabricating |
JPH0684827A (en) * | 1992-02-27 | 1994-03-25 | Internatl Business Mach Corp <Ibm> | Local interconnection provided with germanium layer |
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