JPH01187949A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01187949A JPH01187949A JP1311388A JP1311388A JPH01187949A JP H01187949 A JPH01187949 A JP H01187949A JP 1311388 A JP1311388 A JP 1311388A JP 1311388 A JP1311388 A JP 1311388A JP H01187949 A JPH01187949 A JP H01187949A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- contact window
- polyimide
- forming
- cover film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229920001721 polyimide Polymers 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 239000013039 cover film Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 18
- 239000009719 polyimide resin Substances 0.000 claims description 12
- 239000004642 Polyimide Substances 0.000 abstract description 28
- 229910052782 aluminium Inorganic materials 0.000 abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 16
- 239000010408 film Substances 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 16
- 229910052737 gold Inorganic materials 0.000 description 16
- 239000010931 gold Substances 0.000 description 16
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、バンプ電極を形成する際に半導体素子表面上
に形成するカバー膜のエツジ形状の製造方法に関し、
バリアメタル層のカバレジ不良を改善し、バンプ電極の
微細化を可能とし、さらにカバー膜のクランクの発生を
防止するポリイミド系樹脂のエツジ形状の製造方法を提
供することを課題とし、金属パッドが形成された半導体
基板上をカバー膜で被覆したのち前記金属パッドの所定
領域上に第１のコンタクト窓を形成する工程と、全面に
ポリイミド系樹脂層を形成したのち、前記第１のコンタ
クト窓内に第２のコンタクト窓を形成する工程と、全面
にバリアメタル層を形成する工程と、前記バリアメタル
層上の所定領域に金属バンプを形成する工程と、前記金
属バンプをマスクとして前記バリアメタル層をエツチン
グする工程を有することを特徴とする特
〔産業上の利用分野〕
本発明は、半導体装置の製造方法、特にバンプ電極を形
成する際に半導体素子表面上に形成するカバー膜のエツ
ジ形状の製造方法に関する。[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing an edge shape of a cover film formed on the surface of a semiconductor element when forming a bump electrode, which improves poor coverage of a barrier metal layer, and improves the coverage of a bump electrode. The objective was to provide a method for manufacturing polyimide resin with an edge shape that enables miniaturization of electrodes and also prevents the occurrence of cranking of the cover film.The semiconductor substrate on which metal pads are formed is covered with a cover film. a step of forming a first contact window on a predetermined region of the metal pad; and a step of forming a second contact window within the first contact window after forming a polyimide resin layer on the entire surface; A method characterized by comprising the steps of forming a barrier metal layer on the entire surface, forming metal bumps in a predetermined region on the barrier metal layer, and etching the barrier metal layer using the metal bumps as a mask. [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an edge shape of a cover film formed on the surface of a semiconductor element when forming a bump electrode.
高密度、多ピンＬＳＩ実装方式の１つとしてＴＡ Ｂ
（Ｔａｐｅ Ａｕｔｏｍａｔｅｄ Ｂｏｎｄｉｎｇ）の
技術開発が活発に行なわれている。ＴＡＢ方式はウェハ
ープロセスでアルミパッド上にメタル突起いわゆるバン
プを形成し、その上にリードをボンディングする方式で
ある。TA B is one of the high-density, multi-pin LSI mounting methods.
(Tape Automated Bonding) technology development is being actively carried out. The TAB method is a method in which metal protrusions, so-called bumps, are formed on aluminum pads using a wafer process, and leads are bonded onto the bumps.
第２図は、従来のバンプ電極の製造工程断面図を示して
いる。以下第２図を用いて従来のバンプ電極の製造工程
を説明する。FIG. 2 shows a cross-sectional view of the manufacturing process of a conventional bump electrode. The conventional manufacturing process of bump electrodes will be explained below with reference to FIG.
まず、第２図（ａ）に示すように、半導体素子が形成さ
れた半導体基板１上の所定領域にアルミパッド２を形成
する。次いで全面にＰＳＧ （リン珪酸ガラス）等から
なるカバー膜３をおよそ１μｍ形成したのち、前記アル
ミパッド２上のカバー膜を除去しコンタクト窓７を形成
する。次いで前記コンタクト窓部を含むカバー膜３上に
スパッタ法等の方法によりバリアメタル層４をスパッタ
する。First, as shown in FIG. 2(a), an aluminum pad 2 is formed in a predetermined area on a semiconductor substrate 1 on which a semiconductor element is formed. Next, a cover film 3 made of PSG (phosphosilicate glass) or the like is formed to a thickness of approximately 1 μm over the entire surface, and then the cover film on the aluminum pad 2 is removed to form a contact window 7. Next, a barrier metal layer 4 is sputtered onto the cover film 3 including the contact window portion by a method such as a sputtering method.
このバリアメタル層４は、のちに形成する金バンプとア
ルミパッド２が反応して高抵抗の生成物を生じるのを防
いだり、金バンプとの密着性を良くするために設けられ
、例えばチタンと白金の２層からなっている。This barrier metal layer 4 is provided to prevent the gold bumps that will be formed later from reacting with the aluminum pad 2 to produce high-resistance products, and to improve the adhesion with the gold bumps. It consists of two layers of platinum.
次に、第２図中）に示すように表面に厚さがおよそ２０
〜３０μｍのレジスト層６を形成したのち、フォトリソ
グラフィー技術によりアルミパッド２上を窓開けする。Next, as shown in Fig. 2, the surface has a thickness of approximately 20 mm.
After forming a resist layer 6 of ~30 μm, a window is opened on the aluminum pad 2 by photolithography.
次いで、前記バリアメタル層４をめっき電極として電気
めっきを行ない金バンプ５を厚さおよそ１５乃至３０μ
ｍ形成する。Next, electroplating is performed using the barrier metal layer 4 as a plating electrode to form the gold bumps 5 to a thickness of about 15 to 30 μm.
m form.
最後に、第２図（Ｃ１に示すように、レジスト層６を剥
離したのち、前記金バンプ５をマスクとしてバリアメタ
ル層４をエツチングする。エツチング液としては王水系
及びフン酸系のものを用いる。Finally, as shown in FIG. 2 (C1), after peeling off the resist layer 6, the barrier metal layer 4 is etched using the gold bumps 5 as a mask.Aqua regia or hydrofluoric acid is used as the etching solution. .
このような工程によりバンプ電極を形成することができ
る。Bump electrodes can be formed through such steps.
しかしながら、第２図に示されるような製造工程を経て
形成されるバンプ電極は、バリアメタル層４のエツチン
グを行なう際、エツチング液がカバー膜を通してアルミ
パッド２にまで浸み込んでしまい前記アルミパッド２が
腐食して断線してしまうので必ずしも満足のゆくもので
はなかった。However, when the bump electrode is formed through the manufacturing process shown in FIG. 2 corroded and broke, so it was not always satisfactory.
そこで、前記エツチング液がアルミバッド２まで達しな
いように、カバー膜３上にポリイミド等の樹脂を塗布・
形成したバンプ電極が、例えば特開昭５８−８９２４４
．特開昭５８−５０７５６において提案されている。Therefore, in order to prevent the etching solution from reaching the aluminum pad 2, a resin such as polyimide is coated on the cover film 3.
The formed bump electrode is, for example, disclosed in Japanese Patent Application Laid-Open No. 58-89244.
．． This was proposed in Japanese Patent Application Laid-Open No. 58-50756.
上記のように特開昭５７−８９％４４、特開昭５８−５
０７５６にはＰＳＧよりなるカバー膜３上にポリイミド
系樹脂が形成されたバンプ電極が示されている。しかし
ながら上記公知例には、前記ポリイミド系樹脂パターニ
ング後のエツジの様子は明確に示されていない。ポリイ
ミド系樹脂のエツジの形状がどのようになっているかと
いうことは、バンプ電極のサイズの微細化及びバリアメ
タル層４のカバレジに影響を与えるということがら考え
て重要である。As mentioned above, JP-A-57-89%44, JP-A-58-5
0756 shows a bump electrode in which a polyimide resin is formed on a cover film 3 made of PSG. However, the above-mentioned known examples do not clearly show the appearance of edges after patterning the polyimide resin. The shape of the edge of the polyimide resin is important since it affects the miniaturization of the bump electrode size and the coverage of the barrier metal layer 4.
すなわち、ポリイミド系樹脂のエツジの形状として、例
えば第３図（ａ）及び（ｂ）に示される構造のものが考
えられる。That is, as the shape of the edge of the polyimide resin, for example, structures shown in FIGS. 3(a) and 3(b) can be considered.
第３図（ａｌは、ポリイミド層８のエツジがカバー膜３
よりも外側に形成されている例を示している。FIG. 3 (al indicates that the edge of the polyimide layer 8 is the cover film 3)
The figure shows an example in which it is formed on the outside.
また第３図（ｂｌはポリイミド層８のエツジがカバー膜
３のエツジ上にある例を示している。第３図（ｂｌに示
すようなエツジ形状の場合、コンタクト窓部における段
差は、ポリイミド層８の厚さ分だけ高くなり、したがっ
てこのあと、コンタクト窓部を含むポリイミド層８上に
スパッタ法にてバリアメタル層４をスパッタする際、コ
ンタクト窓部におけるバリアメタル層のカバレジが悪く
なる。In addition, FIG. 3 (bl) shows an example in which the edge of the polyimide layer 8 is on the edge of the cover film 3. In the case of an edge shape as shown in FIG. Therefore, when the barrier metal layer 4 is subsequently sputtered by a sputtering method onto the polyimide layer 8 including the contact window portion, the coverage of the barrier metal layer at the contact window portion becomes poor.
（第３図（ｂ）、ｂ参照）このようにカバレジが悪いと
、バリアメタル層４が断線し、この断線部においてアル
ミパッド２と金バンプ５とが反応し高抵抗の生成物を生
じたりメツキ電極がとれなくなり十分に金バンプ５を形
成できな（なるおそれがある。また、ポリイミド層８は
、全面にポリイミドを塗布したのち前記ポリイミド上に
レジスト層を形成し、フォトリソグラフィー技術により
前記レジスト層を窓開けし、これをマスクとしてエツチ
ングを行なうことにより形成しているが、レジストの位
置合わせ余裕のため、ポリイミド層８のエツジをカバー
膜３のエツジ上に再現性良く形成することは困難である
。(See Figures 3(b) and b) If the coverage is poor in this way, the barrier metal layer 4 may be disconnected, and the aluminum pad 2 and gold bump 5 may react at this disconnection, producing products with high resistance. There is a possibility that the plating electrode cannot be removed and the gold bumps 5 cannot be formed sufficiently.Also, for the polyimide layer 8, after applying polyimide to the entire surface, a resist layer is formed on the polyimide, and the resist layer is formed using photolithography technology. Although it is formed by opening a window in the layer and performing etching using this as a mask, it is difficult to form the edge of the polyimide layer 8 on the edge of the cover film 3 with good reproducibility due to the alignment margin of the resist. It is.
第３図（ａｌに示すようなエツジ形状を形成するための
工程断面図を第４図に示す。第４図に示すようにコンタ
クト窓内を含むカバー膜３上にポリイミドを塗布すると
、断差部の上側と下側の部分では、ポリイミドの膜厚が
例えばｄｌ、 ａｘのように異なってしまう。次いで、
レジスト層９をマスクとして前記ポリイミドをエツチン
グする際、膜Ｋ ｄｔの部分を完全にエツチングしなけ
ればならないためエツチング時間が長くなり、レジスト
層９の下の領域へのサイドエツチング量が増加してしま
う。FIG. 4 shows a cross-sectional view of the process for forming an edge shape as shown in FIG. 3 (al). As shown in FIG. The polyimide film thickness differs between the upper and lower parts, for example, dl and ax.
When etching the polyimide using the resist layer 9 as a mask, the portion of the film K dt must be completely etched, which increases the etching time and increases the amount of side etching to the region below the resist layer 9. .
したがって第３図（ａ）のａの部分の長さが長くなり、
金バンプ５の大きさを微細化することが困難になカバー
膜３のうちＣに示す部分は、ポリイミド層８から露出し
てしまっている。このように、カバー膜３に露出部分が
あると、リードを金バンプ５に熱圧着する時などバンプ
電極に熱的な変化があるとクランクを生じるおそれもあ
る。特に前記Ｃに示す部分はバリアメタル層４を介して
金バンプ５と接続しており、他の領域にくらベクランク
の発生が多い。Therefore, the length of part a in Fig. 3(a) becomes longer,
The portion of the cover film 3 shown in C, where it is difficult to miniaturize the size of the gold bumps 5, is exposed from the polyimide layer 8. If there is an exposed portion of the cover film 3 in this way, there is a risk of cranking if there is a thermal change in the bump electrode, such as when a lead is thermocompression bonded to the gold bump 5. Particularly, the portion indicated by C above is connected to the gold bump 5 via the barrier metal layer 4, and there are many occurrences of blank cranks in other regions.
本発明は、バリアメタル層のカバレジ不良を改善し、バ
ンプ電極の微細化を可能とし、さらにカバー膜のクラン
クの発生を防止するポリイミド系樹脂層のエツジ形状の
製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing an edge shape of a polyimide resin layer that improves poor coverage of a barrier metal layer, enables miniaturization of bump electrodes, and prevents the occurrence of cranks in the cover film. do.
上記問題点にかんがみ、本発明ではアルミパッド２上の
コンタクト窓内にポリイミド層のエツジを入れることに
より上記問題点を解決した。In view of the above problems, the present invention solves the above problems by inserting an edge of the polyimide layer within the contact window on the aluminum pad 2.
すなわち、本発明は表面の所定領域に金属パッドが形成
された半導体基板上をカバー膜で被覆したのち、前記金
属パッドの所定領域上に第１のコンタクト窓を形成する
工程と、前記第１のコンタクト窓内を含む前記カバー膜
上にポリイミド樹脂層を形成したのち、前記第１のコン
タクト窓内に第２のコンタクト窓を形成する工程と、前
記第２のコンタクト窓内を含む前記ポリイミド系樹脂層
上にバリアメタル層を形成する工程と、前記バリアメタ
ル層上の所定領域に金属バンプを形成する工程と、前記
金属バンプをマスクとして前記バリアメタル層をエツチ
ングする工程を含むことを特徴としている。That is, the present invention includes the steps of: covering a semiconductor substrate on which a metal pad is formed in a predetermined region of the surface with a cover film, and then forming a first contact window on a predetermined region of the metal pad; forming a polyimide resin layer on the cover film including the inside of the contact window, and then forming a second contact window inside the first contact window; The method is characterized by comprising the steps of forming a barrier metal layer on the barrier metal layer, forming metal bumps in predetermined areas on the barrier metal layer, and etching the barrier metal layer using the metal bumps as a mask. .
本発明によれば、ポリイミド層のエツチングは第１図（
ｂ）に示すように膜厚ｄ３である部分のみをエツチング
するので、従来のように膜厚ｄｌ＋及びｄ！の両方をエ
ツチングする場合（第４図参照）にくらべてエツチング
の制御性が良くなる。また、ｄ。According to the present invention, the etching of the polyimide layer is performed as shown in FIG.
As shown in b), since only the portion with the film thickness d3 is etched, the film thicknesses dl+ and d! are the same as in the conventional method. The controllability of etching is improved compared to the case where both of the two are etched (see FIG. 4). Also, d.
＜ｄ、であるのでサイドエツチング量も従来にくらべ小
さくなる。さらに、サイドエツチングされても、このサ
イドエツチングがコンタクト窓内にとどまる場合には、
バンプ電極の大きさがこのサイドエツチングにより影響
されることはなく、バンプ電極の微細化が容易となる。<d, so the amount of side etching is also smaller than in the conventional case. Furthermore, even if side etching is performed, if this side etching remains within the contact window,
The size of the bump electrode is not affected by this side etching, making it easy to miniaturize the bump electrode.
また、アルミパッド上のコンタクト窓部は階段状になっ
ているためポリイミド層のコンタクト窓内におけるカバ
レジは改善される。Furthermore, since the contact window portion on the aluminum pad has a stepped shape, the coverage of the polyimide layer within the contact window is improved.
さらにカバー膜は、ポリイミド層に完全に包み込まれる
ので、バンプ電極に加わる熱ストレスによってカバー膜
にクランクが発生することを防止することができる。Furthermore, since the cover film is completely surrounded by the polyimide layer, it is possible to prevent cranking of the cover film due to thermal stress applied to the bump electrodes.
第１図は、本発明を説明するバンプ電極の製造工程断面
図を示している。以下第１図を用いて本発明の実施例に
ついて説明する。FIG. 1 shows a cross-sectional view of the manufacturing process of a bump electrode to explain the present invention. Embodiments of the present invention will be described below with reference to FIG.
第１図（ａｌに示すようにアルミパッド２を含む半導体
基板上に化学気相成長法等の方法によりＰＳＧ層１０を
約０．７μｍ、次いで窒化シリコン層１１を約０．３μ
ｍを形成する。窒化シリコン層１１ははカバー膜の耐湿
性を向上させるために設けられている。次いでフォトリ
ソグラフィー技術によりアルミパッド２上を窓開けし、
第１のコンタクト窓を形成する。As shown in FIG. 1 (al), a PSG layer 10 of about 0.7 μm is deposited on a semiconductor substrate including an aluminum pad 2 by a method such as chemical vapor deposition, and then a silicon nitride layer 11 is deposited with a thickness of about 0.3 μm.
form m. The silicon nitride layer 11 is provided to improve the moisture resistance of the cover film. Next, a window is opened on the aluminum pad 2 using photolithography technology,
forming a first contact window;
次に第１図（ｂｌに示すように、全面にポリイミドを塗
布し、厚さおよそ１乃至２μｍのポリイミド層８を形成
したのち、フォトグラフィー技術により、前記第１のコ
ンタクト窓内に第２のコンタクト窓を形成する。この工
程によりポリイミド層８はアルミパッド２上まで延在す
ることになる。尚、ポリイミド層８のエツチング方法と
しては、全面にレジストを塗布し、コンタクト窓部分を
窓開けしたのち３０℃ヒドラジンにてポリイミドを除去
する方法、全面にポジレジストを塗布し、コンタクト窓
部分を露光したあと現像液にて露光した部分のレジスト
層を剥離すると同時にその直下のポリイミド層も同時に
除去してしまう方法等がある。Next, as shown in FIG. 1 (bl), polyimide is applied to the entire surface to form a polyimide layer 8 with a thickness of about 1 to 2 μm, and then a second contact window is formed in the first contact window using a photography technique. A contact window is formed. Through this process, the polyimide layer 8 extends to the top of the aluminum pad 2. The etching method for the polyimide layer 8 is to apply a resist to the entire surface and open a window in the contact window area. Later, the polyimide was removed using hydrazine at 30°C. A positive resist was applied to the entire surface, the contact window was exposed, and then the resist layer in the exposed area was peeled off using a developer, and at the same time, the polyimide layer immediately below it was also removed. There are ways to do this.
次に第１図（Ｃ）に示すように、前記ポリイミド層８を
ベータしたのちスパッタ法等の方法にて全面にバリアメ
タル層４を形成する。このバリアメタル層４は例えば２
層構造となっており、下層メタルとしては、チタン、チ
タンナイトライド・クロム、上層メタルとしてはパラジ
ウム、白金、金等の貴金属を用いる。下層メタルは主に
アルミバッド２とのちに形成する金バンプとの反応を防
止するため、また上層メタルは主に金バンプとの密着性
を良くするために設ける。次いで、バリアメタルＮ４上
に厚さおよそ１５乃至３０μｍの厚いレジスト層６を形
成し、金バンプ形成領域を窓開けする。Next, as shown in FIG. 1C, after the polyimide layer 8 is betatized, a barrier metal layer 4 is formed on the entire surface by a method such as sputtering. This barrier metal layer 4 is, for example, 2
It has a layered structure, and the lower layer metal uses titanium, titanium nitride/chromium, and the upper layer metal uses noble metals such as palladium, platinum, and gold. The lower metal layer is provided mainly to prevent reaction between the aluminum pad 2 and the gold bumps that will be formed later, and the upper metal layer is provided mainly to improve adhesion with the gold bumps. Next, a thick resist layer 6 having a thickness of about 15 to 30 μm is formed on the barrier metal N4, and a window is opened in the gold bump formation region.
次に、第１図＜ｄ）に示すように、バリアメタル層４を
めっき電極として電気めっきを行ない金バンプ５を厚さ
約２５μｍ形成する。最後に、レジスト層６を剥離した
のち、前記金バンプ５をマスクとしてバリアメタル層４
をエツチングする。Next, as shown in FIG. 1<d), electroplating is performed using the barrier metal layer 4 as a plating electrode to form gold bumps 5 having a thickness of about 25 μm. Finally, after peeling off the resist layer 6, the barrier metal layer 4 is removed using the gold bumps 5 as a mask.
etching.
尚、エツチング液としては、王水素及びフッ酸系の公知
のものを使用する。このような工程を経ることによりバ
ンプ電極を完成することができる。As the etching solution, a known one based on hydrogen regia and hydrofluoric acid is used. Through these steps, a bump electrode can be completed.
本発明によれば（ポリイミド層のエツジをアルミバッド
上まで延在して設けるので、より微細なアメタル層４の
カバレジが改善される。さらに、カバー膜はポリイミド
層に完全に覆われるのでカバー膜のクランクの発生を防
止することができる。According to the present invention (because the edge of the polyimide layer is extended to the top of the aluminum pad, the coverage of the finer ametal layer 4 is improved.Furthermore, since the cover film is completely covered with the polyimide layer, the cover film This can prevent the occurrence of cranks.
第１図は本発明を説明するバンプ電極の製造工程断面図
、
第２図は、従来のバンプ電極の製造工程断面図、第３図
は、従来のポリイミド系樹脂のエツジ形状を示すバンプ
電極断面図、
第４図は従来のポリイミド系樹脂のバターニング工程を
示す半導体素子断面図をそれぞれ示している。
また、１は半導体基板、２はアルミバッド、３はカバー
膜、４はバリアメタル層、５は金バンプ。
６及び９はレジスト層、７はコンタクト窓、８はポリイ
ミド層、１０はＰＳＧ層、１１はＳＩＮ層をそれぞれ示
している。
へ／ヤ棒斗縁
〆ゝ＼ｌ
、々（楢４明ｆＬ梗すクハ・ンアＩへヒ＆偶堅面り稈（
汀面旧］′Ｘ／、引１林板
イ疋庫２ハ゛シフリ５才旧。舎シ弘１工、ｆ呈１饗へ鴬
２ 図Fig. 1 is a sectional view of the manufacturing process of a bump electrode explaining the present invention, Fig. 2 is a sectional view of the manufacturing process of a conventional bump electrode, and Fig. 3 is a sectional view of the bump electrode showing the edge shape of a conventional polyimide resin. FIG. 4 shows cross-sectional views of a semiconductor device showing a conventional patterning process of polyimide resin. Further, 1 is a semiconductor substrate, 2 is an aluminum pad, 3 is a cover film, 4 is a barrier metal layer, and 5 is a gold bump. 6 and 9 are resist layers, 7 is a contact window, 8 is a polyimide layer, 10 is a PSG layer, and 11 is a SIN layer, respectively. He/Yabo Toen 〆ゝ\l 、（Nara 4 Akira
[Tenmen old]' Figure 2
Claims (1)
いて、 表面の所定領域に金属パッドが形成された半導体基板上
をカバー膜で被覆したのち、前記金属パッドの所定領域
上に第１のコンタクト窓を形成する工程と、 前記第１のコンタクト窓内を含む前記カバー膜上にポリ
イミド系樹脂層を形成したのち、前記第一のコンタクト
窓内に第２のコンタクト窓を形成する工程と、 前記第２のコンタクト窓内を含む前記ポリイミド系樹脂
層上にバリアメタル層を形成する工程と、前記バリアメ
タル層上の所定領域に金属バンプを形成する工程と、 前記金属バンプをマスクとして前記バリアメタル層をエ
ッチングする工程を含むことを特徴とする半導体装置の
製造方法。[Claims] In a method of manufacturing a bump electrode formed on a semiconductor chip, a semiconductor substrate on which metal pads are formed on a predetermined region of the surface is covered with a cover film, and then a bump electrode is formed on a predetermined region of the metal pad. forming a polyimide resin layer on the cover film including the inside of the first contact window, and then forming a second contact window inside the first contact window. forming a barrier metal layer on the polyimide resin layer including the inside of the second contact window; forming metal bumps in predetermined areas on the barrier metal layer; and using the metal bumps as a mask. A method for manufacturing a semiconductor device, comprising the step of etching the barrier metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1311388A JPH01187949A (en) | 1988-01-22 | 1988-01-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1311388A JPH01187949A (en) | 1988-01-22 | 1988-01-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01187949A true JPH01187949A (en) | 1989-07-27 |
Family
ID=11824101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1311388A Pending JPH01187949A (en) | 1988-01-22 | 1988-01-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01187949A (en) |
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|---|---|---|---|---|
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| WO2008153128A1 (en) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | Semiconductor device |
| JP2008311530A (en) * | 2007-06-15 | 2008-12-25 | Rohm Co Ltd | Semiconductor device |
| JP2013091264A (en) * | 2011-10-26 | 2013-05-16 | Canon Inc | Liquid ejection head and method of manufacturing the same |
-
1988
- 1988-01-22 JP JP1311388A patent/JPH01187949A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5576748A (en) * | 1990-02-26 | 1996-11-19 | Canon Kabushiki Kaisha | Recording head with through-hole wiring connection which is disposed within the liquid chamber |
| US9053991B2 (en) | 2007-06-15 | 2015-06-09 | Rohm Co., Ltd. | Semiconductor device |
| JP2008311530A (en) * | 2007-06-15 | 2008-12-25 | Rohm Co Ltd | Semiconductor device |
| US8436467B2 (en) | 2007-06-15 | 2013-05-07 | Rohm Co., Ltd. | Semiconductor device |
| US8922010B2 (en) | 2007-06-15 | 2014-12-30 | Rohm Co., Ltd. | Semiconductor device |
| WO2008153128A1 (en) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | Semiconductor device |
| US9123628B2 (en) | 2007-06-15 | 2015-09-01 | Rohm Co., Ltd. | Semiconductor device |
| US9466583B2 (en) | 2007-06-15 | 2016-10-11 | Rohm Co., Ltd. | Semiconductor device |
| US9685419B2 (en) | 2007-06-15 | 2017-06-20 | Rohm Co., Ltd. | Semiconductor device |
| US10032739B2 (en) | 2007-06-15 | 2018-07-24 | Rohm Co., Ltd. | Semiconductor device |
| US10510700B2 (en) | 2007-06-15 | 2019-12-17 | Rohm Co., Ltd. | Semiconductor device |
| US11037897B2 (en) | 2007-06-15 | 2021-06-15 | Rohm Co., Ltd. | Semiconductor device |
| JP2013091264A (en) * | 2011-10-26 | 2013-05-16 | Canon Inc | Liquid ejection head and method of manufacturing the same |
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