JP3351878B2 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP3351878B2 JP3351878B2 JP28108093A JP28108093A JP3351878B2 JP 3351878 B2 JP3351878 B2 JP 3351878B2 JP 28108093 A JP28108093 A JP 28108093A JP 28108093 A JP28108093 A JP 28108093A JP 3351878 B2 JP3351878 B2 JP 3351878B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- solder
- film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1356—Disposition
- H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
- H01L2224/13565—Only outside the bonding interface of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Liquid Crystal (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置とその製造
方法とに関し、とくに突起電極を有する半導体装置とそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a bump electrode and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置を薄型で量産性良く、しかも
効率的にパッケージする従来の技術としては、半導体装
置の電極に対応したリードに一括接続、あるいは順次接
続するテープオートメイデッドボンディング方法（ＴＡ
Ｂ）が挙げられる。ＴＡＢ法によってパッケージ化され
た半導体装置は、ＴＣＰ（Ｔａｐｅ ＣａｒｒｉｅｒＰ
ａｃｋａｇｅ）と呼ばれる。2. Description of the Related Art As a conventional technique for efficiently packaging a semiconductor device in a thin, mass-productive, and efficient manner, a tape-automated bonding method (TA) in which leads are collectively connected or sequentially connected to leads corresponding to electrodes of the semiconductor device.
B). The semiconductor device packaged by the TAB method is a TCP (Tape Carrier P).
package).
【０００３】以下図６（ａ）、（ｂ）を用いて従来のＴ
ＡＢの実装構造およびその製造方法を説明する。図６
（ａ）は可撓性フィルムの半導体装置接続前の状態を示
す平面図であり、図６（ｂ）は可撓性フィルムに半導体
装置を接続した状態を示す断面図である。[0003] Referring to FIGS. 6A and 6B, a conventional T
The mounting structure of AB and its manufacturing method will be described. FIG.
FIG. 6A is a plan view showing a state before the semiconductor device is connected to the flexible film, and FIG. 6B is a cross-sectional view showing a state where the semiconductor device is connected to the flexible film.
【０００４】ＴＡＢは図６の（ａ）、（ｂ）に示すよう
に、２０〜７５μｍの厚さの可撓性フィルム２０１上
に、半導体装置１０１を収納するための半導体装置用穴
３０２と可撓性フィルム２０１を送るためのテープ送り
ガイド穴２０５を有する。可撓性フィルム２０１上には
電気回路用の銅からなる配線材料２０２をスパッタリン
グ法や真空蒸着法で形成する。この配線材料２０２は接
着剤を用いて可撓性フィルム２０１上に形成しても良
い。As shown in FIGS. 6A and 6B, a TAB is formed with a semiconductor device hole 302 for accommodating the semiconductor device 101 on a flexible film 201 having a thickness of 20 to 75 μm. It has a tape feed guide hole 205 for feeding the flexible film 201. On the flexible film 201, a wiring material 202 made of copper for an electric circuit is formed by a sputtering method or a vacuum evaporation method. This wiring material 202 may be formed on the flexible film 201 using an adhesive.
【０００５】可撓性フィルム２０１上に形成した配線材
料２０２は、図６（ｂ）に示すように、半導体装置用穴
３０２を形成した領域では、ひさし状に突き出したよう
な形状を有している。以下、半導体装置用穴３０２の領
域に対して、ひさし状に突き出た配線材料２０２を、イ
ンナーリード３０１と呼ぶ。銅からなるインナーリード
３０１表面は、メッキにより形成した錫（Ｓｎ）で被覆
されている。As shown in FIG. 6B, a wiring material 202 formed on a flexible film 201 has a shape like an eave in a region where a hole 302 for a semiconductor device is formed. I have. Hereinafter, the wiring material 202 that protrudes in an eave-like shape with respect to the region of the semiconductor device hole 302 is referred to as an inner lead 301. The surface of the inner lead 301 made of copper is covered with tin (Sn) formed by plating.
【０００６】半導体装置１０１には、５〜２０μｍの高
さの金（Ａｕ）で形成する突起電極１０７を設ける。そ
してこの突起電極１０７とインナーリード３０１表面に
形成した錫との金錫共晶を利用して、半導体装置１０１
をインナーリード３０１に電気的、機械的に接続してい
る。突起電極１０７はインナーリード３０１側に形成し
ても良く、この場合は半導体装置１０１のアルミ電極上
へ突起電極１０７を直接接続する。The semiconductor device 101 is provided with a protruding electrode 107 made of gold (Au) having a height of 5 to 20 μm. The semiconductor device 101 is formed by using a gold-tin eutectic of the protruding electrode 107 and tin formed on the surface of the inner lead 301.
Are electrically and mechanically connected to the inner lead 301. The projecting electrode 107 may be formed on the inner lead 301 side. In this case, the projecting electrode 107 is directly connected to the aluminum electrode of the semiconductor device 101.
【０００７】さらに可撓性フィルム２０１の半導体装置
用穴３０２と半導体装置１０１とインナーリード３０１
とは、絶縁樹脂２０４で覆い、図６（ｂ）に示す断面構
造が完成する。Further, the semiconductor device hole 302, the semiconductor device 101 and the inner lead 301 of the flexible film 201 are formed.
Means that the cross-sectional structure shown in FIG. 6B is completed.
【０００８】[0008]
【発明が解決しようとする課題】図６を用いて説明した
ＴＡＢの場合、ＴＡＢの可撓性フィルムの構造上、半導
体装置１０１の突起電極１０７は、半導体装置の外周領
域にしか形成できない。インナーリード３０１の接続可
能ピッチである最小８０μｍから計算すると、突起電極
数がフリップチップ実装の場合と同様に５００点以上に
なった場合、必要な半導体装置の外周長さは４０ｍｍ以
上となり半導体装置の大型化を招き、歩留まり低下やコ
スト増を招く。In the case of the TAB described with reference to FIG. 6, the projecting electrode 107 of the semiconductor device 101 can be formed only in the outer peripheral region of the semiconductor device due to the structure of the flexible film of the TAB. When calculated from the minimum connectable pitch of the inner lead 301 of 80 μm, when the number of protruding electrodes becomes 500 or more as in the case of flip-chip mounting, the required outer peripheral length of the semiconductor device becomes 40 mm or more, and This leads to an increase in size, a decrease in yield and an increase in cost.
【０００９】インナーリード３０１のピッチが８０μｍ
以下になった場合、図６（ｂ）に示したインナーリード
３０１の強度が低下し、折れ曲がる不良割合が増加す
る。The pitch of the inner leads 301 is 80 μm
In the case of the following, the strength of the inner lead 301 shown in FIG. 6B decreases, and the percentage of bent defects increases.
【００１０】半導体装置の突起電極をメッキ法で形成し
た場合は共通電極膜をエッチングするため、突起電極根
元が頂部に比較して細くなる。突起電極を微細接続対応
のため縮小し根元径が直径４０μｍを切ると、突起電極
の密着強度の低下を招く。When the protruding electrode of a semiconductor device is formed by plating, the common electrode film is etched, so that the base of the protruding electrode becomes narrower than the top. If the protruding electrode is reduced for fine connection and the root diameter is less than 40 μm, the adhesion strength of the protruding electrode is reduced.
【００１１】本発明の目的は上記課題を解決して、突起
電極形成後の半導体装置の検査が容易に行え、小型で多
接続点に対応でき、微細接続可能で量産性に優れた半導
体装置の実装構造およびその製造方法を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device which can be easily inspected after the formation of a bump electrode, is small in size, can cope with many connection points, can be finely connected, and is excellent in mass productivity. An object of the present invention is to provide a mounting structure and a manufacturing method thereof.
【００１２】[0012]
【課題を解決するための手段】上記目的を達成するため
に本発明においては、以下に記載の構成と工程とを採用
する。In order to achieve the above object, the present invention employs the following configuration and steps.
【００１３】本発明の半導体装置は、半導体装置に設け
る突起電極と、突起電極の根元部に設ける半田と、突起
電極が入る貫通穴を有し、配線材料を有する可撓性フィ
ルムと、半導体装置を覆う絶縁樹脂とを備え、突起電極
と配線材料とは半田で接続していることを特徴とする。A semiconductor device according to the present invention comprises: a protruding electrode provided on a semiconductor device; a solder provided on a root portion of the protruding electrode; a flexible film having a through hole into which the protruding electrode is inserted and having a wiring material; And a wiring material is connected by solder.
【００１４】本発明の半導体装置の製造方法は半導体装
置に根元部の周辺に半田を有する突起電極を形成する工
程と、半導体装置の上に突起電極の位置に対応した貫通
穴および配線材料を有する可撓性フィルムをかぶせて加
熱する工程と、可撓性フィルムと一体となった半導体装
置の検査を行う工程と、可撓性フィルムと半導体装置を
絶縁樹脂で覆う工程とを有することを特徴とする。According to the method of manufacturing a semiconductor device of the present invention, a step of forming a protruding electrode having solder around a base portion of a semiconductor device, and having a through hole and a wiring material corresponding to the position of the protruding electrode on the semiconductor device A step of covering with a flexible film and heating; a step of inspecting a semiconductor device integrated with the flexible film; and a step of covering the flexible film and the semiconductor device with an insulating resin. I do.
【００１５】[0015]
【実施例】本発明における実施例を図１、図２、図３を
用いて説明する。図１（ｆ）と図２は半導体装置の突起
電極の構造を示す断面図で、図１の（ａ）から（ｆ）は
図１（ｆ）の突起電極の製造方法を示す断面図である。
図３（ｃ）は半導体装置の実装構造を示す断面図であ
り、図３（ａ）から（ｃ）はその製造方法を説明するた
めの断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1 (f) and 2 are cross-sectional views showing the structure of the bump electrode of the semiconductor device, and FIGS. 1 (a) to 1 (f) are cross-sectional views showing a method of manufacturing the bump electrode of FIG. 1 (f). .
FIG. 3C is a cross-sectional view showing a mounting structure of the semiconductor device, and FIGS. 3A to 3C are cross-sectional views for explaining a manufacturing method thereof.
【００１６】以下図面を用いて本発明の実施例を説明す
る。まずはじめに半導体装置の突起電極の構造を説明す
る。An embodiment of the present invention will be described below with reference to the drawings. First, the structure of the bump electrode of the semiconductor device will be described.
【００１７】図１（ｆ）に示すように、本発明における
突起電極の構造はアルミ電極１０２上にＡｌ、Ｃｒ、Ｃ
ｕからなる共通電極膜１０４を有する。共通電極膜１０
４の周辺部に半田１０６を有し、共通電極膜１０４上と
半田１０６上とにＣｕとＡｕとからなる突起電極１０７
を有している。突起電極１０７の側壁は、半導体装置１
０１表面に対してほぼ垂直である。As shown in FIG. 1F, the structure of the protruding electrode according to the present invention is such that Al, Cr, C
It has a common electrode film 104 made of u. Common electrode film 10
4 has a solder 106 on the periphery thereof, and a projection electrode 107 made of Cu and Au on the common electrode film 104 and the solder 106.
have. The side wall of the projecting electrode 107 is
01 is almost perpendicular to the surface.
【００１８】図２に示した本発明における突起電極の構
造は、ＣｕとＡｕとからなる突起電極１０７の頂部がマ
ッシュルーム形状であることを特徴とし、その他の構成
は図１（ｆ）と同じである。The structure of the bump electrode of the present invention shown in FIG. 2 is characterized in that the top of the bump electrode 107 made of Cu and Au has a mushroom shape, and the other structure is the same as that of FIG. is there.
【００１９】つぎに本発明における突起電極の製造方法
を、図１（ａ）から（ｆ）を使って説明する。まず図１
（ａ）に示すように、半導体装置１０１上の保護膜１０
３と保護膜１０３が開口した部分のアルミ電極１０２上
との全面に共通電極膜１０４を形成する。保護膜１０３
は燐を含有したシリコン酸化膜、窒化シリコン膜などの
無機質膜や、ポリイミド樹脂などの有機質膜や、これら
の積層構造を用い、形成する膜厚は１〜５μｍである。
共通電極膜１０４はＡｌ、Ｃｒ、Ｃｕ、Ｎｉ、Ａｇ、Ｔ
ｉなどの金属多層膜からなり、真空蒸着、スパッタリン
グ、化学的気相成長法（ＣＶＤ）などの方法で形成す
る。共通電極膜１０４の厚さは総厚で１０μｍ以内で形
成する。Next, a method of manufacturing a bump electrode according to the present invention will be described with reference to FIGS. First, Figure 1
As shown in (a), the protective film 10 on the semiconductor device 101
A common electrode film 104 is formed on the entire surface of the aluminum electrode 102 at the portion where the third electrode 3 and the protective film 103 are opened. Protective film 103
Is formed using an inorganic film such as a silicon oxide film or a silicon nitride film containing phosphorus, an organic film such as a polyimide resin, or a laminated structure thereof, and has a thickness of 1 to 5 μm.
The common electrode film 104 is made of Al, Cr, Cu, Ni, Ag, T
i, and is formed by a method such as vacuum deposition, sputtering, or chemical vapor deposition (CVD). The total thickness of the common electrode film 104 is formed within 10 μm.
【００２０】つぎに図１（ｂ）に示すように、感光性樹
脂１０５を共通電極膜１０４上に全面に回転塗布により
形成する方法、またはフィルムタイプの感光性樹脂１０
５を張り付ける方法で形成し、所定のマスクを用いて露
光現像処理を行うフォトリソグラフィーにより共通電極
膜１０４上に感光性樹脂１０５を１〜１００μｍの厚さ
で形成する。Next, as shown in FIG. 1B, a method of forming a photosensitive resin 105 on the entire surface of the common electrode film 104 by spin coating, or a film type photosensitive resin
The photosensitive resin 105 is formed in a thickness of 1 to 100 μm on the common electrode film 104 by photolithography in which exposure and development processing is performed using a predetermined mask.
【００２１】つぎに図１（ｃ）に示すように、感光性樹
脂１０５の開口部分に、共通電極膜１０４をメッキ電極
として半田メッキを行なった後、感光性樹脂１０５を取
り除く。共通電極膜１０４上に形成した半田１０６はド
ーナツ状に閉じた形状で形成されていることが望まし
い。ドーナツ状に閉じていない場合でも突起電極の形成
および使用は可能であるが、後工程での共通電極膜エッ
チングの余裕度や突起電極の強度がドーナツ状に閉じた
場合の突起電極よりも劣る。Next, as shown in FIG. 1C, the opening of the photosensitive resin 105 is subjected to solder plating using the common electrode film 104 as a plating electrode, and then the photosensitive resin 105 is removed. It is desirable that the solder 106 formed on the common electrode film 104 be formed in a donut-shaped closed shape. Although it is possible to form and use the protruding electrode even when the protruding electrode is not closed in a donut shape, the margin of etching of the common electrode film and the strength of the protruding electrode in a later process are inferior to those of the protruding electrode when the donut is closed.
【００２２】この半田１０６はスクリーン印刷法で形成
しても良い。スクリーン印刷法で半田１０６を形成した
場合は感光性樹脂１０５の塗布および取り除く工程は不
要になる。The solder 106 may be formed by a screen printing method. When the solder 106 is formed by the screen printing method, the step of applying and removing the photosensitive resin 105 becomes unnecessary.
【００２３】つぎに図１（ｄ）に示すように、感光性樹
脂１０５を共通電極膜１０４上に全面に回転塗布する方
法、またはフィルムタイプの感光性樹脂１０５を張り付
ける方法で形成し、所定のマスクを用いて露光現像処理
を行うフォトリソグラフィーにより形成する。感光性樹
脂１０５は半田１０６の内側開口から外側開口の間に開
口部を形成し、膜厚は１０〜３００μｍで形成する。Next, as shown in FIG. 1D, the photosensitive resin 105 is formed by spin coating the entire surface of the common electrode film 104 or by sticking the film type photosensitive resin 105 thereon. It is formed by photolithography in which exposure and development processing is performed using the above mask. The photosensitive resin 105 forms an opening between the inner opening and the outer opening of the solder 106, and has a thickness of 10 to 300 μm.
【００２４】つぎに図１（ｅ）に示すように、感光性樹
脂１０５の開口部分に、共通電極膜１０４をメッキ電極
としてＣｕ、Ａｕ、Ａｇ、Ｎｉなどの金属をメッキして
突起電極１０７を形成し、感光性樹脂１０５を除去す
る。Next, as shown in FIG. 1E, the protruding electrode 107 is formed by plating a metal such as Cu, Au, Ag, or Ni on the opening of the photosensitive resin 105 by using the common electrode film 104 as a plating electrode. Then, the photosensitive resin 105 is removed.
【００２５】最後に、突起電極１０７と半田１０６とを
マスクとして共通電極膜１０４をエッチング除去し、図
１（ｆ）に示した根元に半田１０６を備える突起電極１
０７が得られる。Finally, the common electrode film 104 is removed by etching using the protruding electrode 107 and the solder 106 as a mask, and the protruding electrode 1 having the solder 106 at the root shown in FIG.
07 is obtained.
【００２６】図１（ｄ）において、感光性樹脂１０５の
開口部にメッキを行う際、感光性樹脂１０５上面よりも
高くメッキを行なった後、感光性樹脂１０５を除去して
共通電極膜１０４を突起電極１０７と半田１０６とをマ
スクとしてエッチング処理を行うと、図２に示した根元
に半田を備えたマッシュルーム形状の突起電極１０７が
得られる。In FIG. 1D, when plating the opening of the photosensitive resin 105, the plating is performed higher than the upper surface of the photosensitive resin 105, and then the photosensitive resin 105 is removed to form the common electrode film 104. When the etching process is performed using the projecting electrode 107 and the solder 106 as a mask, the mushroom-shaped projecting electrode 107 having the solder at the base shown in FIG. 2 is obtained.
【００２７】本発明における実施例の半導体装置の実装
構造は図３（ｃ）の断面図に示すように、可撓性フィル
ム２０１の配線材料２０２と突起電極１０７とは半田１
０６で接続している。半導体装置１０１の突起電極１０
７は可撓性フィルム２０１の貫通穴２０３中に有る。可
撓性フィルム２０１は配線材料２０２と共に半導体装置
１０１の外側に伸びている。半導体装置１０１と可撓性
フィルム２０１には絶縁樹脂２０４を設ける。As shown in the sectional view of FIG. 3C, the mounting structure of the semiconductor device according to the embodiment of the present invention is such that the wiring material 202 of the flexible film 201 and the protruding electrode 107 are solder 1
06. Protruding electrode 10 of semiconductor device 101
7 is in the through hole 203 of the flexible film 201. The flexible film 201 extends outside the semiconductor device 101 together with the wiring material 202. An insulating resin 204 is provided on the semiconductor device 101 and the flexible film 201.
【００２８】本発明における実施例の半導体装置の製造
方法は、図３（ａ）に示したように高さ１０〜１５０μ
ｍの突起電極１０７の根元周囲に、突起電極１０７の１
０分の１から４分の３の厚さの半田１０６を形成する。
その後、半導体装置１０１の突起電極１０７先端側か
ら、突起電極１０７の位置に対応した貫通穴２０３と配
線材料２０２とを有する厚さ１０〜１５０μｍの可撓性
フィルム２０１をかぶせる。The method for fabricating a semiconductor device according to the embodiment of the present invention uses a height of 10 to 150 μm as shown in FIG.
m around the base of the protruding electrode 107
The solder 106 having a thickness of 1/0 to 3/4 is formed.
Thereafter, a flexible film 201 having a thickness of 10 to 150 μm having a through hole 203 corresponding to the position of the projecting electrode 107 and a wiring material 202 is covered from the tip side of the projecting electrode 107 of the semiconductor device 101.
【００２９】配線材料２０２は主に銅、金などで形成
し、厚さは２〜４０μｍで形成するのが望ましい。貫通
穴２０３は突起電極１０７が通過できるように０．２μ
ｍ以上の隙間を設けておく。貫通穴２０３は配線材料２
０２形成後、直径１００μｍまではドリルで穴あけし、
１００μｍ以下では感光性樹脂をマスクとしてエッチン
グして形成する方法やレーザー光で蒸発させて形成す
る。The wiring material 202 is mainly formed of copper, gold or the like, and preferably has a thickness of 2 to 40 μm. The through hole 203 has a thickness of 0.2 μm so that the bump electrode 107 can pass therethrough.
A gap of at least m is provided. The through hole 203 is a wiring material 2
After forming 02, drill a hole up to 100μm in diameter,
When the thickness is 100 μm or less, the film is formed by etching using a photosensitive resin as a mask or by evaporation using a laser beam.
【００３０】可撓性フィルム２０１を半導体装置１０１
にかぶせた後、１６０〜２５０℃の温度で加熱すると、
図３（ｂ）に示したように、突起電極１０７の根元部周
囲にある半田１０６が溶融して、突起電極１０７と可撓
性フィルム２０１の配線材料２０２とが溶融固化した半
田１０６で接続する。The flexible film 201 is connected to the semiconductor device 101
After heating, heat at a temperature of 160-250 ° C.
As shown in FIG. 3B, the solder 106 around the base of the protruding electrode 107 is melted, and the protruding electrode 107 and the wiring material 202 of the flexible film 201 are connected by the melted and solidified solder 106. .
【００３１】図３（ｂ）では可撓性フィルム２０１の配
線材料２０２は、半導体装置１０１側のみで示してある
が、可撓性フィルム２０１の両側に配線材料２０２があ
っても良い。さらに、配線材料２０２は半導体装置１０
６の反対側のみにあっても良い。またさらに、可撓性フ
ィルム２０１が多層になっていても構わない。また、可
撓性フィルム２０１の配線材料２０２は貫通穴２０３の
縁までしか形成されていないが、貫通穴２０３の内壁に
形成されていても良く、可撓性フィルム２０１の両面の
配線材料２０２がつながっていても良い。In FIG. 3B, the wiring material 202 of the flexible film 201 is shown only on the semiconductor device 101 side, but the wiring material 202 may be provided on both sides of the flexible film 201. Further, the wiring material 202 is the semiconductor device 10
6 may be provided only on the opposite side. Further, the flexible film 201 may have a multilayer structure. Further, the wiring material 202 of the flexible film 201 is formed only up to the edge of the through hole 203, but may be formed on the inner wall of the through hole 203. It may be connected.
【００３２】可撓性フィルム２０１は半田１０６を溶融
する際の熱に耐える材料としてポリイミドなどが望まし
い。The flexible film 201 is preferably made of polyimide or the like as a material resistant to heat when the solder 106 is melted.
【００３３】図３（ｂ）の状態で、可撓性フィルム２０
１の配線材料２０２上に半導体装置１０１検査用のプロ
ーブを接触させて電気的な検査を行い、半導体装置１０
１の良否判定を行う。In the state shown in FIG.
An electrical inspection is performed by bringing a probe for inspecting the semiconductor device 101 into contact with the first wiring material 202 and the semiconductor device 10 is inspected.
1 is determined.
【００３４】半導体装置１０１の良否選別後、半導体装
置１０１と可撓性フィルム２０１とを絶縁樹脂２０４で
覆って、図３（ｃ）に示した半導体装置が完成する。After the quality of the semiconductor device 101 is determined, the semiconductor device 101 and the flexible film 201 are covered with the insulating resin 204 to complete the semiconductor device shown in FIG.
【００３５】図３（ｃ）において、可撓性フィルム２０
１の貫通穴２０３中にある突起電極１０７の厚さは可撓
性フィルム２０１の厚さと同じ場合を示したが、突起電
極の厚さは可撓性フィルム２０１の厚さより厚くても機
能上問題ない。しかし、最終的な半導体装置の厚さを薄
くする場合は、突起電極１０７の厚さは可撓性フィルム
２０１の厚さより薄い方が望ましい。In FIG. 3C, the flexible film 20
The thickness of the protruding electrode 107 in the through hole 203 is the same as the thickness of the flexible film 201. However, even if the thickness of the protruding electrode is larger than the thickness of the flexible film 201, there is a problem in function. Absent. However, when the thickness of the final semiconductor device is reduced, it is desirable that the thickness of the protruding electrode 107 be smaller than the thickness of the flexible film 201.
【００３６】絶縁樹脂２０４は半導体装置１０１側のみ
を覆う構造でも構わない。The insulating resin 204 may have a structure that covers only the semiconductor device 101 side.
【００３７】図４の平面図に本発明の実施例に用いる可
撓性フィルムの構造を示す。図４に示すように、可撓性
フィルム２０１にテープ送りガイド穴２０５を設け、配
線材料２０２と貫通穴２０３とを連続的に設けることに
より、従来の技術で説明した図６のＴＡＢのようにテー
プ状で形成することが可能である。このため、ＴＡＢ法
と同様に連続的に半導体装置１０１を接続でき、量産性
に優れる特徴がある。FIG. 4 is a plan view showing the structure of the flexible film used in the embodiment of the present invention. As shown in FIG. 4, a tape feed guide hole 205 is provided in a flexible film 201, and a wiring material 202 and a through hole 203 are provided continuously, as in TAB of FIG. It can be formed in a tape shape. For this reason, the semiconductor device 101 can be connected continuously as in the TAB method, which is excellent in mass productivity.
【００３８】本発明においては、従来のＴＡＢと異なり
インナーリードが必要ないため、インナーリードが折れ
曲がる不良の発生がなく、歩留まりが向上する効果が得
られる。またさらに、貫通穴をマトリックス状に形成で
きるため、ＴＡＢよりも多端子で微細な接続に対応でき
る。In the present invention, unlike the conventional TAB, the inner lead is not required, so that there is no occurrence of a defect that the inner lead is bent and the effect of improving the yield is obtained. Further, since the through holes can be formed in a matrix, it is possible to cope with finer connections with more terminals than TAB.
【００３９】図５は本発明の実施例に用いる可撓性フィ
ルム２０１の配線を共通化した場合の構造を示す。図５
に示したように、半導体装置１０１の入力などの共通化
可能な端子は配線材料２０２をバスライン配線２０２ａ
のように形成することが可能である。図５（ａ）では半
導体装置の入力対応端子のレイアウトを変更することに
より、可撓性フィルム２０１の配線材料２０２は片面の
みでバスライン化ができる。図５（ｂ）では配線材料２
０２は可撓性フィルム２０１の両面に形成するため半導
体装置１０１側の突起電極レイアウト変更による対応は
不要である。FIG. 5 shows a structure in which the wiring of the flexible film 201 used in the embodiment of the present invention is shared. FIG.
As shown in FIG. 2, terminals that can be shared, such as inputs of the semiconductor device 101, are connected to the bus line wiring 202a.
It can be formed as follows. In FIG. 5A, by changing the layout of the input corresponding terminals of the semiconductor device, the wiring material 202 of the flexible film 201 can be formed into a bus line on only one side. In FIG. 5B, the wiring material 2
No. 02 is formed on both surfaces of the flexible film 201, so that it is not necessary to cope with a change in the layout of the protruding electrodes on the semiconductor device 101 side.
【００４０】[0040]
【発明の効果】以上のように本発明の方法では、従来例
であるＴＡＢのインナーリードが無いために、インナー
リード曲がりに起因する不良を無くせる。このためＴＡ
Ｂに比較して実装歩留まりが向上し、製造コストを下げ
ることが可能となる。As described above, according to the method of the present invention, since there is no TAB inner lead as in the conventional example, it is possible to eliminate defects caused by inner lead bending. For this reason TA
As compared with B, the mounting yield is improved, and the manufacturing cost can be reduced.
【００４１】本発明の突起電極の根元部分は半田で補強
されるため、従来の突起電極よりも密着強度の優れた突
起電極が得られ、微細接続に対応でき、実装プロセス条
件範囲の拡大化が図れる効果がある。同一条件で接続を
行った場合には、実装品質の安定化が図れ、品質向上に
絶大な効果が得られる。Since the base of the protruding electrode of the present invention is reinforced with solder, a protruding electrode having better adhesion strength than the conventional protruding electrode can be obtained, it is possible to cope with fine connection, and the range of mounting process conditions can be expanded. There is an effect that can be achieved. If the connection is made under the same conditions, the mounting quality can be stabilized, and a great effect can be obtained for quality improvement.
【００４２】本発明の絶縁樹脂を半導体装置側のみで覆
う場合では、絶縁樹脂形成後の厚さはＴＡＢよりも薄く
することができる。When the insulating resin of the present invention is covered only on the semiconductor device side, the thickness after forming the insulating resin can be smaller than TAB.
【００４３】さらに、半導体装置を複数個接続する場合
は、入力側の配線を共通化してバスラインを形成するこ
とが可能となり、複数個の半導体装置を一括して実装す
ることが可能である。Further, when a plurality of semiconductor devices are connected, it is possible to form a bus line by sharing the wiring on the input side, and it is possible to mount a plurality of semiconductor devices collectively.
【図１】本発明の実施例における突起電極の製造方法を
工程順に示す断面図である。FIG. 1 is a cross-sectional view illustrating a method for manufacturing a bump electrode in an embodiment of the present invention in the order of steps.
【図２】本発明の実施例における突起電極の構造を示す
断面図である。FIG. 2 is a cross-sectional view illustrating a structure of a protruding electrode according to an embodiment of the present invention.
【図３】本発明の実施例における半導体装置の製造方法
を工程順に示す断面図である。FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in an embodiment of the present invention in the order of steps.
【図４】本発明の可撓性フィルムの構造を示す平面図で
ある。FIG. 4 is a plan view showing the structure of the flexible film of the present invention.
【図５】本発明の可撓性フィルムの構造を示す平面図で
ある。FIG. 5 is a plan view showing the structure of the flexible film of the present invention.
【図６】従来例である半導体装置の構造を示す断面図で
ある。FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device.
１０１ 半導体装置 １０４ 共通電極膜 １０５ 感光性樹脂 １０６ 半田 １０７ 突起電極 ２０１ 可撓性フィルム ２０２ 配線材料 ２０３ 貫通穴 ２０４ 絶縁樹脂 ３０１ インナーリード ３０２ 半導体装置用穴 DESCRIPTION OF SYMBOLS 101 Semiconductor device 104 Common electrode film 105 Photosensitive resin 106 Solder 107 Projecting electrode 201 Flexible film 202 Wiring material 203 Through hole 204 Insulating resin 301 Inner lead 302 Hole for semiconductor device
Claims (3)
料及び該突起電極が入る貫通穴を設けた可撓性フィルム
とを備える半導体装置であって、前記突起電極の根元部の外周に、該突起電極より高さが
低く、且つ前記突起電極と異なる材料の半田を有し 、該半田が前記配線材料と接続している ことを特徴とする
半導体装置 。 A semiconductor device provided with a protruding electrode, and a wiring member
Film having a through hole into which a protruding electrode enters
A height of which is higher than the height of the protruding electrode on the outer periphery of the base of the protruding electrode.
Low and have a solder material different from the protrusion electrodes, characterized in that the solder is connected to the wiring material
Semiconductor device .
装置の製造方法であって、前記半導体装置のアルミ電極が開口した保護膜上の全面
に共通電極膜を形成する工程と 、前記共通電極膜上の全面に第１の感光性樹脂を形成し、
前記アルミ電極中央部は残存させ該アルミ電極の周辺部
の該共通電極膜が露出するように該第１の感光性樹脂を
パターン形成する工程と 、前記第１の感光性樹脂から露出した前記共通電極膜上に
メッキにより開口を有する半田を形成し、前記第１の感
光性樹脂を除去する工程と 、全面に第２の感光性樹脂を形成し、前記半田の前記開口
内の前記共通電極膜が露出するように該第２の感光性樹
脂をパターン形成する工程と 、前記第２の感光性樹脂から露出した前記共通電極膜上に
メッキにより前記半田と異なる材料からなると共に前記
半田より高さが高い突起電極を形成し、前記第２の感光
性樹脂を除去する工程と 、前記半田と前記突起電極から露出した前記共通電極膜を
除去する工程とを有する ことを特徴とする半導体装置の
製造方法。2. A semiconductor having solder at the root of a protruding electrode.
A method of manufacturing a device , comprising: an entire surface of a protective film in which an aluminum electrode of the semiconductor device is opened.
Forming a common electrode film, and forming a first photosensitive resin on the entire surface of the common electrode film,
The center of the aluminum electrode is left and the periphery of the aluminum electrode
Of the first photosensitive resin so that the common electrode film of
Forming a pattern on the common electrode film exposed from the first photosensitive resin;
Forming a solder having an opening by plating;
Removing the photosensitive resin, forming a second photosensitive resin on the entire surface, and forming the opening in the solder;
The second photosensitive tree so that the common electrode film in
Forming a resin pattern on the common electrode film exposed from the second photosensitive resin.
Made of a material different from the solder by plating and
Forming a protruding electrode having a height higher than that of the solder;
Removing the conductive resin, removing the solder and the common electrode film exposed from the projecting electrode.
Removing the semiconductor device.
と、配線材料と前記突起電極が入る貫通穴を有する可撓
性フィルムを前記半導体装置上に配置し、前記半導体装
置と前記可撓性フィルムとを接続する工程とを有する半
導体装置の製造方法であって、前記突起電極の形成工程が、前記半導体装置のアルミ電
極上に開口を設けた半 田を形成し、その後、該半田の前
記開口内に前記半田より高く、且つ前記半田と異なる材
料の前記突起電極を形成する ことを特徴とする半導体装
置の製造方法 。3. A process for forming a bump electrode on a semiconductor device.
And a flexible material having a through hole into which the wiring material and the protruding electrode enter.
Disposing a conductive film on the semiconductor device;
Connecting the flexible film to the flexible film.
A method of manufacturing a conductor device , wherein the step of forming the protruding electrode includes forming an aluminum electrode of the semiconductor device.
Forming a semi-field having an opening on the electrode, then the previous solder
A material higher than the solder in the opening and different from the solder
A semiconductor device , wherein the protruding electrode of the material is formed.
Manufacturing method of the device .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28108093A JP3351878B2 (en) | 1993-11-10 | 1993-11-10 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28108093A JP3351878B2 (en) | 1993-11-10 | 1993-11-10 | Semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07135238A JPH07135238A (en) | 1995-05-23 |
| JP3351878B2 true JP3351878B2 (en) | 2002-12-03 |
Family
ID=17634053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28108093A Expired - Fee Related JP3351878B2 (en) | 1993-11-10 | 1993-11-10 | Semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3351878B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002231762A (en) * | 2001-02-01 | 2002-08-16 | Toppan Forms Co Ltd | Mounting method for ic chip and ic chip mounting body |
-
1993
- 1993-11-10 JP JP28108093A patent/JP3351878B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07135238A (en) | 1995-05-23 |
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