JPH01183836A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01183836A JPH01183836A JP886088A JP886088A JPH01183836A JP H01183836 A JPH01183836 A JP H01183836A JP 886088 A JP886088 A JP 886088A JP 886088 A JP886088 A JP 886088A JP H01183836 A JPH01183836 A JP H01183836A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- silanol
- film
- layer
- paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 5
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical compound O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 229910007156 Si(OH)4 Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005269 aluminizing Methods 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置の製造方法に係り、特にアルミ系の
配線を用いた装置のパッシベーション技術に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and particularly to a passivation technique for a device using aluminum wiring.
（ロ）従来の技術
従来、半導体装置のパッシベーション膜には、耐湿性に
優れ機械的強度の大きい窒化シリコン膜が用いられてい
る。この窒化シリコン膜は、半導体基板上に形成された
素子及び配線を覆うようにしてプラズマＣＶＤ法によっ
て堆積されるが、このような窒化シリコン膜には大きな
圧縮応力が発生するため、素子や配線の変形または破損
が生じる場合があった。特に装置の高集積化を図るため
に配線の幅を細く形成する場合には、配線の受ける応力
の影響は無視できないものであった。このため、例えば
特開昭６０−１１７６３３号公報に開示されている如く
、パッシベーション膜に発生する応力を吸収するための
緩衝膜をパッシベーション膜と基板との間に設けている
。この緩衝膜は、配線にアルミを用いた場合には、酸化
アルミ膜、アルミナ膜等が用いられ、その熱膨張係数は
、アルミとパッシベーション膜との熱膨張係数の間にあ
るように構成きれている。(B) Prior Art Conventionally, a silicon nitride film, which has excellent moisture resistance and high mechanical strength, has been used as a passivation film for semiconductor devices. This silicon nitride film is deposited by plasma CVD so as to cover the elements and wiring formed on the semiconductor substrate, but because such a silicon nitride film generates large compressive stress, it may damage the elements and wiring. Deformation or damage may occur. In particular, when the width of the wiring is narrowed in order to achieve high integration of the device, the influence of stress on the wiring cannot be ignored. For this reason, a buffer film is provided between the passivation film and the substrate to absorb the stress generated in the passivation film, as disclosed in, for example, Japanese Patent Laid-Open No. 60-117633. When aluminum is used for the wiring, this buffer film is made of aluminum oxide film, alumina film, etc., and its thermal expansion coefficient is between that of aluminum and the passivation film. There is.
（ハ）発明が解決しようとする課題
しかしながら、緩衝膜を形成する場合に於いても応力が
発生するために、応力に対して弱いアルミ系の配線を用
いて微細配線（特に線幅２μｍ以下）を行った場合には
配線の変形や破損を生じる虞れがあり、素子特性の劣化
を招いた。(c) Problems to be Solved by the Invention However, since stress is generated even when forming a buffer film, fine wiring (especially with a line width of 2 μm or less) using aluminum wiring, which is weak against stress, is required. If this was done, there was a risk that the wiring would be deformed or damaged, leading to deterioration of device characteristics.
そこで本発明は、素子及び配線が受ける応力を十分に減
少させて素子及び配線の変形、破損を防止し、装置の信
頼性を高めて歩留りの向上を図ることを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to sufficiently reduce the stress applied to elements and wiring to prevent deformation and damage to the elements and wiring, thereby increasing reliability of the device and improving yield.
（ニ）課題を解決するための手段
本発明は上記問題点に鑑みてなきれたものであり、素子
及びアルミ系配線が設けられた半導体基板上に熱硬化性
のシラノールペーストを塗布し、このペーストを加熱処
理して硬化させると共にシラノールに含まれるＯＨ基に
よって上記アルミ系配線の表面をアルミナ化させた後、
上記素子及び配線を保護するパッシベーション膜を形成
することを特徴とする。(d) Means for Solving the Problems The present invention was developed in view of the above-mentioned problems, and consists of coating a thermosetting silanol paste on a semiconductor substrate on which elements and aluminum wiring are provided. After heat-treating the paste to harden it and aluminizing the surface of the aluminum wiring using the OH group contained in the silanol,
A feature of the present invention is that a passivation film is formed to protect the above-mentioned elements and wiring.
くホ）作用
本発明によれば、上述の構成によりシラノールに含まれ
るＯＨ基とアルミ系配線とが加熱処理によって反応して
配線の表面にのみ緩衝膜として働くアルミナ層が形成さ
れるため、アルミナ層に発生する応力の影響はごく僅か
なものとなり、配線の変形、破損を防止できる。According to the present invention, with the above-described structure, the OH group contained in silanol and the aluminum wiring react with each other through heat treatment to form an alumina layer acting as a buffer film only on the surface of the wiring. The influence of stress generated in the layer is minimal, and deformation and damage to the wiring can be prevented.
（へ）実施例
本発明の一実施例を図面に従って説明する。第１図乃至
第３図は本発明に係る半導体装置の製造方法の一部工程
を示す工程別断面図である。(F) Embodiment An embodiment of the present invention will be described with reference to the drawings. 1 to 3 are step-by-step cross-sectional views showing some steps of the method for manufacturing a semiconductor device according to the present invention.
これらの図において、（１）は半導体基板、（２）（３
）はＰＳＧ（リンガラス）よりなる層間絶縁膜、（４）
はアルミニウムよりなる第１Ｗ１配線、（５）は第２層
配線、（６）はシラノールペーストが硬化せしめられた
Ｓ ＯＧ （５ｐｉｎ Ｏｎ Ｇｌａｓｓ ）膜、（７
）は窒化シリコンよりなるパッシベーション膜である。In these figures, (1) is a semiconductor substrate, (2) (3
) is an interlayer insulating film made of PSG (phosphorus glass), (4)
is the first W1 wiring made of aluminum, (5) is the second layer wiring, (6) is the SOG (5 pin on glass) film made of hardened silanol paste, (7
) is a passivation film made of silicon nitride.
本発明の特徴とするところは、第２層配線（５）を形成
した後にシラノールペーストを塗布してＳＯＧ膜（６）
を形成することにある。即ち、第１図に示すように半導
体基板（１）上に第１層及び第２層配線（４）（５）を
形成した後に、５ｉ（ＯＨ）４（シラノール）及びｐｔ
ｏａ （五酸化リン）を主成分とするシラノールペース
トを半導体基板（１）上に回転塗布し、これを４００℃
で加熱してＳＯＧ膜（６）を形成する。このとき、シラ
ノールに含まれるＯＨ基とアルミ配線とが反応して第１
層及び第２層配線（４）（５）のＳＯＧ膜（６）に接す
る表面にアルミナ層が形成される。そして、第３図に示
すようにプラズマＣＶＤ法によって窒化シリコンをＳＯ
Ｇ膜（６）上に堆積してパッシベーション膜（７）を形
成する。The feature of the present invention is that after forming the second layer wiring (5), silanol paste is applied to form the SOG film (6).
The goal is to form a That is, as shown in FIG. 1, after forming the first layer and second layer wiring (4) (5) on the semiconductor substrate (1), 5i(OH)4 (silanol) and pt
A silanol paste containing OA (phosphorous pentoxide) as a main component is spin-coated onto the semiconductor substrate (1), and heated at 400°C.
is heated to form an SOG film (6). At this time, the OH group contained in the silanol reacts with the aluminum wiring, causing the first
An alumina layer is formed on the surfaces of the layers and the second layer wirings (4) and (5) that are in contact with the SOG film (6). Then, as shown in Fig. 3, silicon nitride was converted into SO
A passivation film (7) is formed by depositing on the G film (6).
ここで、５ＯＧＩＩＩ（６）そのものは、パッシベーシ
ョン膜（７）に発生する圧縮応力を緩衝させる効果は小
さいが、アルミ配線表面に形成されたアルミナ層は機械
的強度が大きく圧縮応力を吸収するため、緩衝膜として
働き、素子及び配線の変形、破損が防止できる。Here, 5OGIII (6) itself has a small effect of buffering compressive stress generated in the passivation film (7), but the alumina layer formed on the aluminum wiring surface has high mechanical strength and absorbs compressive stress. It acts as a buffer film and can prevent deformation and damage to elements and wiring.
また、シラノールペーストを塗布してＳＯＧ膜（６）を
形成することによって素子及び配線の表面が平坦化され
るため、パッシベーション膜（７）のステップカバレー
ジが改善され、より良好なパッシベーション膜が得られ
る。Furthermore, by applying the silanol paste to form the SOG film (6), the surfaces of the elements and wiring are flattened, so the step coverage of the passivation film (7) is improved and a better passivation film can be obtained. .
（ト）発明の効果
本発明によれば、素子及び配線が設けられた半導体基板
表面にシラノールペーストを塗布してＳＯＧ膜を形成す
ることにより、シラノールに含まれるＯＨ基とアルミ系
配線とが反応して配線の表面にのみ緩衝膜として働くア
ルミナ層が形成されるため、配線がアルミナ層から受け
る応力の影響がごく僅かなものとなり配線の変形、破損
が防止でき装置の信頼性が高まり歩留りの向上を図るこ
とができる。(G) Effects of the Invention According to the present invention, by applying silanol paste to the surface of a semiconductor substrate on which elements and wiring are provided to form an SOG film, the OH groups contained in the silanol react with the aluminum wiring. Since the alumina layer that acts as a buffer film is formed only on the surface of the wiring, the influence of stress on the wiring from the alumina layer is minimal, preventing deformation and damage to the wiring, increasing the reliability of the equipment, and reducing yield. You can improve your performance.
第１図乃至第３図は本発明の一実施例を示す工程別断面
図である。
（１）・・・半導体基板、（２）（３）・・・層間絶縁
膜、（４）・・・第１欝配線、 （５）・・・第２Ｅ！
Ｉ配腺、 （６）・・・ＳＯＧ膜、（７）・・・パッシ
ベーション膜。FIGS. 1 to 3 are cross-sectional views showing steps of an embodiment of the present invention. (1)... Semiconductor substrate, (2) (3)... Interlayer insulating film, (4)... First depression wiring, (5)... Second E!
I gland, (6)...SOG film, (7)...passivation film.
Claims (2)
に熱硬化性のシラノールペーストを塗布し、このペース
トを加熱処理して硬化させると共にシラノールに含まれ
るＯＨ基によって上記アルミ系配線の表面をアルミナ化
させた後、上記素子及び配線を保護するパッシベーショ
ン膜を形成することを特徴とする半導体装置の製造方法
。(1) Thermosetting silanol paste is applied onto a semiconductor substrate on which elements and aluminum wiring are provided, and the paste is heat-treated to harden, and the surface of the aluminum wiring is cured by the OH groups contained in the silanol. A method for manufacturing a semiconductor device, comprising forming a passivation film for protecting the element and wiring after aluminization.
とを特徴とする請求項第１項に記載の半導体装置の製造
方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the passivation film is silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP886088A JPH01183836A (en) | 1988-01-19 | 1988-01-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP886088A JPH01183836A (en) | 1988-01-19 | 1988-01-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01183836A true JPH01183836A (en) | 1989-07-21 |
Family
ID=11704459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP886088A Pending JPH01183836A (en) | 1988-01-19 | 1988-01-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01183836A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
-
1988
- 1988-01-19 JP JP886088A patent/JPH01183836A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6383916B1 (en) * | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
| US7294871B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7294870B2 (en) | 1998-12-21 | 2007-11-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7329954B2 (en) | 1998-12-21 | 2008-02-12 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7368376B2 (en) | 1998-12-21 | 2008-05-06 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7372085B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7372155B2 (en) | 1998-12-21 | 2008-05-13 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7384864B2 (en) | 1998-12-21 | 2008-06-10 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US7405149B1 (en) | 1998-12-21 | 2008-07-29 | Megica Corporation | Post passivation method for semiconductor chip or wafer |
| US7420276B2 (en) | 1998-12-21 | 2008-09-02 | Megica Corporation | Post passivation structure for semiconductor chip or wafer |
| US7422976B2 (en) | 1998-12-21 | 2008-09-09 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
| US8546947B2 (en) | 2001-12-13 | 2013-10-01 | Megica Corporation | Chip structure and process for forming the same |
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