JPS6181631A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6181631A JPS6181631A JP59203204A JP20320484A JPS6181631A JP S6181631 A JPS6181631 A JP S6181631A JP 59203204 A JP59203204 A JP 59203204A JP 20320484 A JP20320484 A JP 20320484A JP S6181631 A JPS6181631 A JP S6181631A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- cvd
- wiring
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に信頼度の高い表面保護
膜を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a highly reliable surface protection film.
従来、半導体基板に不純物を拡散して素子を形成し各素
子をＡ４−？Ａｔ合金等の金属配線で接続した後、キズ
による不良の低減や耐湿性の向上を目的として、常圧の
ＣＶＤ（Ｃｈｅｍｉｃａｌ ＶａｐｏｒＤｅｐｏｓｉｔ
ｉｏｎ ）法やプラズマＣＶＤ法によって、シリコン酸
化膜、 ＰＳＧ（Ｐｈｏｓｐｈｏｒｏｕｓ ８ｉ１ｉ−
ｃａｔｅ Ｇｌａｓｓ ）膜、シリコン窒化膜を形成し
ていた。Conventionally, elements are formed by diffusing impurities into a semiconductor substrate, and each element is A4-? After connecting with metal wiring such as At alloy, atmospheric pressure CVD (Chemical Vapor Deposit) is applied to reduce defects due to scratches and improve moisture resistance.
ion) method or plasma CVD method, silicon oxide film, PSG (Phosphorous 8i1i-
cate glass) film and silicon nitride film were formed.
第２図及び第３図は従来の保護膜を有する半導体装置の
断面図を示す。両図において、ｌはシリコン基板で２は
約７０００１のシリコン酸化膜、３は１μｍの厚さのＡ
ｔ配線でちる。金属配線が形成された後、ハンドリンク
によるキズを防いだり耐湿性を向上させるために、第２
図のようにモノシラン（ＳｉＨ４）ａ酸素（０２）Ｉ７
オスフイン（ＰＨｓ）から、常圧下でＣＶＤ法によって
シリコン酸化膜中に五酸化燐（Ｐ２Ｏ３）が３から６モ
ルチ含まれるＰ８Ｇ膜４を、あるいは第３図のようにモ
ノ７ラン（８ｉＨ４）とアンモニア（ＮＨ３）を減圧状
態でプラズマ励起するプラズマＣＶＤ法によってシリコ
ン窒化膜５を形成していた。2 and 3 show cross-sectional views of a semiconductor device having a conventional protective film. In both figures, l is a silicon substrate, 2 is a silicon oxide film of approximately 70,001 mm, and 3 is a 1 μm thick silicon oxide film.
Chill with t wiring. After the metal wiring is formed, a second
As shown in the figure, monosilane (SiH4) a oxygen (02) I7
A P8G film 4 containing 3 to 6 moles of phosphorus pentoxide (P2O3) in a silicon oxide film is formed from osphine (PHs) by CVD under normal pressure, or a P8G film 4 containing 3 to 6 moles of phosphorus pentoxide (P2O3) is formed from osphine (PHs), or mono7ran (8iH4) and ammonia as shown in Figure 3. The silicon nitride film 5 was formed by a plasma CVD method in which (NH3) is plasma excited in a reduced pressure state.
上述による表面保護膜のうち、常圧ＣＶＤによるＰ８Ｇ
膜４は、その成長方式のためＡｔ配線段部でのステ、プ
カバレ、ジが悪くなシ、シかもＰＥＧ膜自体機械的強度
が弱いため、Ａｔ配線の段部でクラ、りが発生しやすく
なる。またプラズマＣＶＤによるシリコン窒化膜の場合
、機械的強度も強く段部でのステ、プカバレッジも良好
であるが、窒化膜の内部応力が平坦部では圧縮応力であ
るが、段部では引張応力となるためやはシ段部にクラ、
りが発生しやすくなる。Among the surface protective films described above, P8G produced by atmospheric pressure CVD
Due to its growth method, film 4 may have problems such as distortion, bulge, and warping at the stepped portions of the At wiring.Since the PEG film itself has low mechanical strength, cracks and cracks are likely to occur at the stepped portions of the At wiring. Become. Furthermore, in the case of a silicon nitride film produced by plasma CVD, it has strong mechanical strength and good step coverage at stepped portions, but the internal stress of the nitride film is compressive stress at flat portions, but becomes tensile stress at stepped portions. Narumeya is in the middle of the day,
This makes it more likely that the problem will occur.
上述した従来の半導体装置の表面保護膜は何れも金属配
線の膜厚が厚くなったシ、段部の傾斜が急峻になってく
ると、その上部に形成したＣＶＤ絶縁膜に金属配線の段
部のところで、り２ツクが発生しゃすくなル、半導体装
置の信頼度、特に耐湿性の向上を阻害する大きな要因と
なっていた。In all of the above-mentioned conventional surface protective films of semiconductor devices, when the film thickness of the metal wiring becomes thick and the slope of the stepped portion becomes steep, the stepped portion of the metal wiring is formed on the CVD insulating film formed on the top. However, the occurrence of leaks has been a major factor hindering the improvement of reliability, especially moisture resistance, of semiconductor devices.
本発明の半導体装置は上記問題点に着目してなされたも
ので、金属配線の上部にクラ、りの発生しない表面保護
膜を有する半導体装置を提供することを目的とする。The semiconductor device of the present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a semiconductor device having a surface protection film on which cracks and scratches do not occur over metal wiring.
本発明の半導体装置は、基板の一生面に形成された複数
個の素子と該複数個の各素子を接続する金属配線が形成
された半導体基板表面に表面保護膜として回転塗布法で
形成された第１の絶縁膜とＣＶＤ法で形成された第２の
絶縁膜よりなる複層の絶縁膜を有することＫよシ構成さ
れる。The semiconductor device of the present invention is formed by a spin coating method as a surface protective film on the surface of a semiconductor substrate on which a plurality of elements are formed on the entire surface of the substrate and metal wiring connecting each of the plurality of elements is formed. The device is configured to have a multilayer insulating film consisting of a first insulating film and a second insulating film formed by a CVD method.
次に１本発明について、図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.
第１図（ａ） 、 （ｂ）は本発明の一実施例並びにそ
の製造方法を説明するために工程順に示した断面図であ
る。なお、説明の都合上半導体基板表面に形成した素子
の表示は省略した。FIGS. 1(a) and 1(b) are cross-sectional views shown in order of steps to explain an embodiment of the present invention and its manufacturing method. Note that for convenience of explanation, elements formed on the surface of the semiconductor substrate are not shown.
まず、第１図（ａｌに示すように、複数個の素子が形成
されたシリコン基板ｌのシリコン熱酸化膜２上ＫＡｔ配
線３を形成し、しかる後ケイ素化合物（Ｒｎ ８ｉ （
ＯＨ）４−ｎ ）を有機溶剤に溶解したものを表面に回
転塗布する。これを窒素雰囲気中において３００℃で６
０分間、さらに４５０’Ｃで３０分間ベークして、シリ
コン酸化膜６を形成する。こうして段部で厚く平坦部で
薄いシリコン酸化膜を形成することによｐｈｔ配線によ
ってできた急峻な段をなだらかにすることができる。First, as shown in FIG. 1 (al), a KAt wiring 3 is formed on the silicon thermal oxide film 2 of a silicon substrate l on which a plurality of elements are formed, and then a silicon compound (Rn 8i (
A solution of OH)4-n) dissolved in an organic solvent is spin-coated onto the surface. This was heated at 300℃ in a nitrogen atmosphere for 6
A silicon oxide film 6 is formed by baking at 450'C for 30 minutes. By forming a silicon oxide film that is thick in the stepped portions and thin in the flat portions, the steep steps formed by the pht wiring can be smoothed out.
次に、第１図（ｂｌに示すように、塗布法で形成された
シリコン酸化膜６上に常圧ＣＶＤやプラズマＣＶＤによ
ってＰ２Ｏ膜やシリコン窒化膜のようなＣＶＤ絶縁膜７
を形成する。Next, as shown in FIG. 1 (bl), a CVD insulating film 7 such as a P2O film or a silicon nitride film is deposited on the silicon oxide film 6 formed by the coating method by atmospheric pressure CVD or plasma CVD.
form.
以上によシ基板の一生面に形成された複数個の素子とこ
れら複数個の各素子を接続する金属配線３が形成された
半導体基板ｌの表面に表面保護膜として回転塗布法で形
成された第１の絶縁膜６とＣＶＤ法で形成された第２の
絶縁膜７とよりなる複層の絶縁膜を有する半導体装置が
得られる。A surface protective film was formed by spin coating on the surface of the semiconductor substrate l on which the plurality of elements formed on the whole surface of the substrate and the metal wiring 3 connecting each of these plurality of elements were formed. A semiconductor device having a multilayer insulating film including the first insulating film 6 and the second insulating film 7 formed by the CVD method is obtained.
なお、本発明において、回転塗布法によって形成する第
１の絶縁膜はシリコン酸化膜に限定されず、ポリイミド
のような有機絶縁膜でもよい。In the present invention, the first insulating film formed by the spin coating method is not limited to a silicon oxide film, but may be an organic insulating film such as polyimide.
以上説明したように１本発明によれば、金属配線の膜厚
が厚くな）段差が大きくなったプ、Ａ、／＝金合金のよ
うに、ＲＩＥ（几ｅａｃｔｉｖｅ ＩＯＮＥｔｃｈｉ
ｎｇ ）を使って配線を形成して段部の傾斜が急峻にな
っても、その上に形成したＣＶＤ絶縁膜にクラ、りが発
生することがなくな）、半導体装置の信頼度特に耐湿性
を大幅に改善することができた。As explained above, according to the present invention, RIE (active IONETCH) can be
Even if the slope of the stepped portion becomes steep when wiring is formed using NG), the CVD insulating film formed on top of the wiring will not have cracks or cracks), improving the reliability of semiconductor devices, especially moisture resistance. was able to be significantly improved.
第１図（ａｌ 、 （ｂｌは本発明の一実施例及びその
製造方法を説明するために工程順に示した断面図、第２
図および第３図は何れも従来の保護膜を有する半導体装
置の断面図である。
ｌ・・・・・・半導体基板（シリコン基板）、２・・・
・・・シリコン熱酸化膜、３・・・・・・金属配線（Ａ
ｔ配線）、４・・・・・・ＣＶＤ ＰＥＧ膜、５・・・
・・・ＰＣＶＤ シリコン窒化膜、６・・・・・・第１
の絶縁膜（回転塗布シリコン酸化膜）、７・・・・・・
第２の絶縁膜（ＣＶＤ絶縁膜）。
代理人 弁理士 内 原 ８ °’ ：、’、ｐ
、：。
１・′ ”１
（αン
（ｂ）
第１ 図
３Ａｅ配東
第２ 凹
第３図Figure 1 (al, bl is a cross-sectional view shown in the order of steps to explain one embodiment of the present invention and its manufacturing method,
Both the figure and FIG. 3 are cross-sectional views of a semiconductor device having a conventional protective film. l... Semiconductor substrate (silicon substrate), 2...
...Silicon thermal oxide film, 3...Metal wiring (A
t wiring), 4...CVD PEG film, 5...
...PCVD silicon nitride film, 6...1st
Insulating film (spinning silicon oxide film), 7...
Second insulating film (CVD insulating film). Agent Patent Attorney Uchihara 8 °':,',p
, :. 1・' ”1 (αn(b) 1st Fig. 3Ae east arrangement 2nd concave Fig. 3
Claims (1)
の各素子を接続する金属配線が形成された半導体基板表
面に、表面保護膜として回転塗布法で形成された第１の
絶縁膜とＣＶＤ法で形成された第２の絶縁膜とよりなる
複層の絶縁膜を有することを特徴とする半導体装置。A first insulator formed as a surface protective film by a spin coating method on the surface of a semiconductor substrate on which a plurality of elements formed on one main surface of the substrate and metal wiring connecting each of the plurality of elements are formed. A semiconductor device comprising a multilayer insulating film including a film and a second insulating film formed by a CVD method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59203204A JPS6181631A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59203204A JPS6181631A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181631A true JPS6181631A (en) | 1986-04-25 |
Family
ID=16470188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59203204A Pending JPS6181631A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181631A (en) |
-
1984
- 1984-09-28 JP JP59203204A patent/JPS6181631A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4097889A (en) | Combination glass/low temperature deposited Siw Nx Hy O.sub.z | |
| US3745428A (en) | Semiconductor device having a composite film as a passivating film | |
| JPH03179778A (en) | Insulating board for forming thin film semiconductor | |
| JPS6181631A (en) | Semiconductor device | |
| US6657299B2 (en) | Semiconductor with a stress reduction layer and manufacturing method therefor | |
| JPH07226547A (en) | Magnetoresistance element and its manufacture | |
| JPS6247135A (en) | Manufacture of semiconductor device | |
| JPH01293632A (en) | Semiconductor device | |
| JPH0555199A (en) | Semiconductor device | |
| JPH06267935A (en) | Manufacture of semiconductor device | |
| JPH05234991A (en) | Semiconductor device | |
| JPS61296726A (en) | Manufacture of semiconductor device | |
| JPS58135645A (en) | Manufacture of semiconductor device | |
| JPH0419707B2 (en) | ||
| JP3327994B2 (en) | Method for manufacturing semiconductor device | |
| JPH03161932A (en) | Structure of surface protective film of semiconductor device and forming method of same surface protective film | |
| JPH06216118A (en) | Manufacture of semiconductor device | |
| JP2501209B2 (en) | Glass substrate and manufacturing method thereof | |
| KR100237355B1 (en) | Method for manufacturing semiconductor device | |
| JPS63213934A (en) | Semiconductor device | |
| JPS6150378B2 (en) | ||
| JPH01283938A (en) | Semiconductor device | |
| JPH0669361A (en) | Semiconductor device and its manufacture | |
| JPH06291253A (en) | Formation of dielectric film of electric charge storage section of semiconductor element | |
| JPH04122026A (en) | Manufacture of semiconductor device |